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GET /api/patches/8582/?format=api
{ "id": 8582, "url": "https://patches.dpdk.org/api/patches/8582/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446556153-18845-2-git-send-email-jerin.jacob@caviumnetworks.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446556153-18845-2-git-send-email-jerin.jacob@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446556153-18845-2-git-send-email-jerin.jacob@caviumnetworks.com", "date": "2015-11-03T13:09:02", "name": "[dpdk-dev,01/12] eal: arm64: add armv8-a version of rte_atomic_64.h", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5802beeb2509ba1b09ef713eda98054a4c740c93", "submitter": { "id": 305, "url": "https://patches.dpdk.org/api/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446556153-18845-2-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8582/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8582/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 09F6891B4;\n\tTue, 3 Nov 2015 14:10:06 +0100 (CET)", "from na01-bl2-obe.outbound.protection.outlook.com\n\t(mail-bl2on0057.outbound.protection.outlook.com [65.55.169.57])\n\tby dpdk.org (Postfix) with ESMTP id A486491B4\n\tfor <dev@dpdk.org>; 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SFP:1101; SCL:1; SRVR:BY2PR0701MB1974;\n\tH:localhost.caveonetworks.com; \n\tFPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: caviumnetworks.com does not\n\tdesignate permitted sender hosts)", "SpamDiagnosticOutput": "1:23", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Nov 2015 13:10:00.2669\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY2PR0701MB1974", "Subject": "[dpdk-dev] [PATCH 01/12] eal: arm64: add armv8-a version of\n\trte_atomic_64.h", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "except rte_?wb() functions other functions are used from\nRTE_FORCE_INTRINSICS=y scheme\n\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n .../common/include/arch/arm/rte_atomic.h | 4 +\n .../common/include/arch/arm/rte_atomic_64.h | 88 ++++++++++++++++++++++\n 2 files changed, 92 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_64.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\nindex f4f5783..f3f3b6e 100644\n--- a/lib/librte_eal/common/include/arch/arm/rte_atomic.h\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\n@@ -33,6 +33,10 @@\n #ifndef _RTE_ATOMIC_ARM_H_\n #define _RTE_ATOMIC_ARM_H_\n \n+#ifdef RTE_ARCH_64\n+#include <rte_atomic_64.h>\n+#else\n #include <rte_atomic_32.h>\n+#endif\n \n #endif /* _RTE_ATOMIC_ARM_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h\nnew file mode 100644\nindex 0000000..671caa7\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h\n@@ -0,0 +1,88 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) Cavium networks Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Cavium networks nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_ATOMIC_ARM64_H_\n+#define _RTE_ATOMIC_ARM64_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+#define dmb(opt) do { asm volatile(\"dmb \" #opt : : : \"memory\"); } while (0)\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_mb(void)\n+{\n+\tdmb(ish);\n+}\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_wmb(void)\n+{\n+\tdmb(ishst);\n+}\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_rmb(void)\n+{\n+\tdmb(ishld);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_ARM64_H_ */\n", "prefixes": [ "dpdk-dev", "01/12" ] }