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GET /api/patches/85809/?format=api
{ "id": 85809, "url": "https://patches.dpdk.org/api/patches/85809/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201228123302.3608-2-talshn@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201228123302.3608-2-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201228123302.3608-2-talshn@nvidia.com", "date": "2020-12-28T12:32:28", "name": "[v2,01/35] common/mlx5/windows: add missing DV and IBV definitions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bb990ab1a5c812c6b0090dbd456a629bfc6af769", "submitter": { "id": 1893, "url": "https://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201228123302.3608-2-talshn@nvidia.com/mbox/", "series": [ { "id": 14482, "url": "https://patches.dpdk.org/api/series/14482/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14482", "date": "2020-12-28T12:32:28", "name": "mlx5 Windows support - part #6", "version": 2, "mbox": "https://patches.dpdk.org/series/14482/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85809/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/85809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3CFEBA09FF;\n\tMon, 28 Dec 2020 13:33:42 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 60C8DCA04;\n\tMon, 28 Dec 2020 13:33:38 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id EAAFEC9F2\n for <dev@dpdk.org>; Mon, 28 Dec 2020 13:33:36 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n talshn@nvidia.com) with SMTP; 28 Dec 2020 14:33:32 +0200", "from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BSCXWnG001295;\n Mon, 28 Dec 2020 14:33:32 +0200" ], "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com,\n ophirmu@nvidia.com", "Date": "Mon, 28 Dec 2020 14:32:28 +0200", "Message-Id": "<20201228123302.3608-2-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20201228123302.3608-1-talshn@nvidia.com>", "References": "<20201217173037.11396-2-talshn@nvidia.com>\n <20201228123302.3608-1-talshn@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v2 01/35] common/mlx5/windows: add missing DV and\n\tIBV definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ophir Munk <ophirmu@nvidia.com>\n\nAdd missing DV and IBV definition to file mlx5_win_defs.h. The\ndefinitions originated from rdma-core library which is not part of\nWindows. They are referenced in shared files that must compile under\nWindows such as mlx5_flow_dv.c and mlx5_rxtx.c.\n\nSigned-off-by: Ophir Munk <ophirmu@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/windows/mlx5_win_defs.h | 141 ++++++++++++++++++++++++++++\n 1 file changed, 141 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h\nindex 72a3131f5e..e9569e4431 100644\n--- a/drivers/common/mlx5/windows/mlx5_win_defs.h\n+++ b/drivers/common/mlx5/windows/mlx5_win_defs.h\n@@ -22,4 +22,145 @@ enum {\n \tMLX5_CQE_RESP_ERR\t= 14,\n \tMLX5_CQE_INVALID\t= 15,\n };\n+\n+enum {\n+\tMLX5_OPCODE_NOP\t\t\t= 0x00,\n+\tMLX5_OPCODE_SEND_INVAL\t\t= 0x01,\n+\tMLX5_OPCODE_RDMA_WRITE\t\t= 0x08,\n+\tMLX5_OPCODE_RDMA_WRITE_IMM\t= 0x09,\n+\tMLX5_OPCODE_SEND\t\t= 0x0a,\n+\tMLX5_OPCODE_SEND_IMM\t\t= 0x0b,\n+\tMLX5_OPCODE_TSO\t\t\t= 0x0e,\n+\tMLX5_OPCODE_RDMA_READ\t\t= 0x10,\n+\tMLX5_OPCODE_ATOMIC_CS\t\t= 0x11,\n+\tMLX5_OPCODE_ATOMIC_FA\t\t= 0x12,\n+\tMLX5_OPCODE_ATOMIC_MASKED_CS\t= 0x14,\n+\tMLX5_OPCODE_ATOMIC_MASKED_FA\t= 0x15,\n+\tMLX5_OPCODE_FMR\t\t\t= 0x19,\n+\tMLX5_OPCODE_LOCAL_INVAL\t\t= 0x1b,\n+\tMLX5_OPCODE_CONFIG_CMD\t\t= 0x1f,\n+\tMLX5_OPCODE_UMR\t\t\t= 0x25,\n+\tMLX5_OPCODE_TAG_MATCHING\t= 0x28\n+};\n+\n+enum mlx5dv_cq_init_attr_mask {\n+\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE\t= 1 << 0,\n+\tMLX5DV_CQ_INIT_ATTR_MASK_FLAGS\t\t= 1 << 1,\n+\tMLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2,\n+};\n+\n+enum mlx5dv_cqe_comp_res_format {\n+\tMLX5DV_CQE_RES_FORMAT_HASH\t\t= 1 << 0,\n+\tMLX5DV_CQE_RES_FORMAT_CSUM\t\t= 1 << 1,\n+\tMLX5DV_CQE_RES_FORMAT_CSUM_STRIDX\t= 1 << 2,\n+};\n+\n+enum ibv_access_flags {\n+\tIBV_ACCESS_LOCAL_WRITE\t\t= 1,\n+\tIBV_ACCESS_REMOTE_WRITE\t\t= 1 << 1,\n+\tIBV_ACCESS_REMOTE_READ\t\t= 1 << 2,\n+\tIBV_ACCESS_REMOTE_ATOMIC\t= 1 << 3,\n+\tIBV_ACCESS_MW_BIND\t\t= 1 << 4,\n+\tIBV_ACCESS_ZERO_BASED\t\t= 1 << 5,\n+\tIBV_ACCESS_ON_DEMAND\t\t= 1 << 6,\n+};\n+\n+enum mlx5_ib_uapi_devx_create_event_channel_flags {\n+\tMLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,\n+};\n+\n+#define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \\\n+\tMLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA\n+\n+enum {\n+\tMLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR\t\t= 0x01,\n+\tMLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR\t\t= 0x02,\n+\tMLX5_CQE_SYNDROME_LOCAL_PROT_ERR\t\t= 0x04,\n+\tMLX5_CQE_SYNDROME_WR_FLUSH_ERR\t\t\t= 0x05,\n+\tMLX5_CQE_SYNDROME_MW_BIND_ERR\t\t\t= 0x06,\n+\tMLX5_CQE_SYNDROME_BAD_RESP_ERR\t\t\t= 0x10,\n+\tMLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR\t\t= 0x11,\n+\tMLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR\t\t= 0x12,\n+\tMLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR\t\t= 0x13,\n+\tMLX5_CQE_SYNDROME_REMOTE_OP_ERR\t\t\t= 0x14,\n+\tMLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR\t= 0x15,\n+\tMLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR\t\t= 0x16,\n+\tMLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR\t\t= 0x22,\n+};\n+\n+enum {\n+\tMLX5_ETH_WQE_L3_CSUM = (1 << 6),\n+\tMLX5_ETH_WQE_L4_CSUM = (1 << 7),\n+};\n+\n+/*\n+ * RX Hash fields enable to set which incoming packet's field should\n+ * participates in RX Hash. Each flag represent certain packet's field,\n+ * when the flag is set the field that is represented by the flag will\n+ * participate in RX Hash calculation.\n+ * Note: IPV4 and IPV6 flags can't be enabled together on the same QP,\n+ * TCP and UDP flags can't be enabled together on the same QP.\n+ */\n+enum ibv_rx_hash_fields {\n+\tIBV_RX_HASH_SRC_IPV4\t= 1 << 0,\n+\tIBV_RX_HASH_DST_IPV4\t= 1 << 1,\n+\tIBV_RX_HASH_SRC_IPV6\t= 1 << 2,\n+\tIBV_RX_HASH_DST_IPV6\t= 1 << 3,\n+\tIBV_RX_HASH_SRC_PORT_TCP\t= 1 << 4,\n+\tIBV_RX_HASH_DST_PORT_TCP\t= 1 << 5,\n+\tIBV_RX_HASH_SRC_PORT_UDP\t= 1 << 6,\n+\tIBV_RX_HASH_DST_PORT_UDP\t= 1 << 7,\n+\tIBV_RX_HASH_IPSEC_SPI\t\t= 1 << 8,\n+\tIBV_RX_HASH_INNER\t\t= (1 << 31),\n+};\n+\n+enum {\n+\tMLX5_RCV_DBR\t= 0,\n+\tMLX5_SND_DBR\t= 1,\n+};\n+\n+#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2\n+#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2\t0x0\n+#endif\n+#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL\n+#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL\t0x1\n+#endif\n+#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2\n+#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2\t0x2\n+#endif\n+#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL\n+#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL\t0x3\n+#endif\n+\n+struct mlx5_err_cqe {\n+\tuint8_t\t\trsvd0[32];\n+\tuint32_t\tsrqn;\n+\tuint8_t\t\trsvd1[18];\n+\tuint8_t\t\tvendor_err_synd;\n+\tuint8_t\t\tsyndrome;\n+\tuint32_t\ts_wqe_opcode_qpn;\n+\tuint16_t\twqe_counter;\n+\tuint8_t\t\tsignature;\n+\tuint8_t\t\top_own;\n+};\n+\n+struct mlx5_wqe_srq_next_seg {\n+\tuint8_t\t\t\trsvd0[2];\n+\trte_be16_t\t\tnext_wqe_index;\n+\tuint8_t\t\t\tsignature;\n+\tuint8_t\t\t\trsvd1[11];\n+};\n+\n+enum ibv_wq_state {\n+\tIBV_WQS_RESET,\n+\tIBV_WQS_RDY,\n+\tIBV_WQS_ERR,\n+\tIBV_WQS_UNKNOWN\n+};\n+\n+struct mlx5_wqe_data_seg {\n+\trte_be32_t\t\tbyte_count;\n+\trte_be32_t\t\tlkey;\n+\trte_be64_t\t\taddr;\n+};\n #endif /* __MLX5_WIN_DEFS_H__ */\n", "prefixes": [ "v2", "01/35" ] }