Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/85637/?format=api
{ "id": 85637, "url": "https://patches.dpdk.org/api/patches/85637/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201222050728.41000-5-feifei.wang2@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201222050728.41000-5-feifei.wang2@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201222050728.41000-5-feifei.wang2@arm.com", "date": "2020-12-22T05:07:25", "name": "[RFC,v1,4/6] app/eventdev: add release barriers for pipeline test", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8ce12023d42d0217e183362f1311c9e3e31022cb", "submitter": { "id": 1771, "url": "https://patches.dpdk.org/api/people/1771/?format=api", "name": "Feifei Wang", "email": "feifei.wang2@arm.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201222050728.41000-5-feifei.wang2@arm.com/mbox/", "series": [ { "id": 14414, "url": "https://patches.dpdk.org/api/series/14414/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14414", "date": "2020-12-22T05:07:21", "name": "refactor smp barriers in app/eventdev", "version": 1, "mbox": "https://patches.dpdk.org/series/14414/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85637/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D5B97A09EF;\n\tTue, 22 Dec 2020 06:09:02 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 53584CC61;\n\tTue, 22 Dec 2020 06:07:52 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 8A2E7CC55;\n Tue, 22 Dec 2020 06:07:50 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00B241042;\n Mon, 21 Dec 2020 21:07:49 -0800 (PST)", "from net-x86-dell-8268.shanghai.arm.com\n (net-x86-dell-8268.shanghai.arm.com [10.169.210.131])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BF4C13F718;\n Mon, 21 Dec 2020 21:07:45 -0800 (PST)" ], "From": "Feifei Wang <feifei.wang2@arm.com>", "To": "Jerin Jacob <jerinj@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>", "Cc": "dev@dpdk.org, nd@arm.com, Honnappa.Nagarahalli@arm.com,\n Feifei Wang <feifei.wang2@arm.com>, pbhagavatula@marvell.com,\n stable@dpdk.org, Phil Yang <phil.yang@arm.com>", "Date": "Tue, 22 Dec 2020 13:07:25 +0800", "Message-Id": "<20201222050728.41000-5-feifei.wang2@arm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201222050728.41000-1-feifei.wang2@arm.com>", "References": "<20201222050728.41000-1-feifei.wang2@arm.com>", "Subject": "[dpdk-dev] [RFC PATCH v1 4/6] app/eventdev: add release barriers\n\tfor pipeline test", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add release barriers before updating the processed packets for worker\nlcores to ensure the worker lcore has really finished data processing\nand then it can update the processed packets number.\n\nFixes: 314bcf58ca8f (\"app/eventdev: add pipeline queue worker functions\")\nCc: pbhagavatula@marvell.com\nCc: stable@dpdk.org\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nSigned-off-by: Feifei Wang <feifei.wang2@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n app/test-eventdev/test_pipeline_queue.c | 64 +++++++++++++++++++++----\n 1 file changed, 56 insertions(+), 8 deletions(-)", "diff": "diff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test-eventdev/test_pipeline_queue.c\nindex 7bebac34f..0c0ec0ceb 100644\n--- a/app/test-eventdev/test_pipeline_queue.c\n+++ b/app/test-eventdev/test_pipeline_queue.c\n@@ -30,7 +30,13 @@ pipeline_queue_worker_single_stage_tx(void *arg)\n \n \t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n \t\t\tpipeline_event_tx(dev, port, &ev);\n-\t\t\tw->processed_pkts++;\n+\n+\t\t\t/* release barrier here ensures stored operation\n+\t\t\t * of the event completes before the number of\n+\t\t\t * processed pkts is visible to the main core\n+\t\t\t */\n+\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t} else {\n \t\t\tev.queue_id++;\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n@@ -59,7 +65,13 @@ pipeline_queue_worker_single_stage_fwd(void *arg)\n \t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n-\t\tw->processed_pkts++;\n+\n+\t\t/* release barrier here ensures stored operation\n+\t\t * of the event completes before the number of\n+\t\t * processed pkts is visible to the main core\n+\t\t */\n+\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t__ATOMIC_RELEASE);\n \t}\n \n \treturn 0;\n@@ -84,7 +96,13 @@ pipeline_queue_worker_single_stage_burst_tx(void *arg)\n \t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n \t\t\t\tpipeline_event_tx(dev, port, &ev[i]);\n \t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\tw->processed_pkts++;\n+\n+\t\t\t\t/* release barrier here ensures stored operation\n+\t\t\t\t * of the event completes before the number of\n+\t\t\t\t * processed pkts is visible to the main core\n+\t\t\t\t */\n+\t\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\t} else {\n \t\t\t\tev[i].queue_id++;\n \t\t\t\tpipeline_fwd_event(&ev[i],\n@@ -121,7 +139,13 @@ pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n-\t\tw->processed_pkts += nb_rx;\n+\n+\t\t/* release barrier here ensures stored operation\n+\t\t * of the event completes before the number of\n+\t\t * processed pkts is visible to the main core\n+\t\t */\n+\t\t__atomic_fetch_add(&(w->processed_pkts), nb_rx,\n+\t\t\t\t__ATOMIC_RELEASE);\n \t}\n \n \treturn 0;\n@@ -146,7 +170,13 @@ pipeline_queue_worker_multi_stage_tx(void *arg)\n \n \t\tif (ev.queue_id == tx_queue[ev.mbuf->port]) {\n \t\t\tpipeline_event_tx(dev, port, &ev);\n-\t\t\tw->processed_pkts++;\n+\n+\t\t\t/* release barrier here ensures stored operation\n+\t\t\t * of the event completes before the number of\n+\t\t\t * processed pkts is visible to the main core\n+\t\t\t */\n+\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\tcontinue;\n \t\t}\n \n@@ -180,7 +210,13 @@ pipeline_queue_worker_multi_stage_fwd(void *arg)\n \t\t\tev.queue_id = tx_queue[ev.mbuf->port];\n \t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n-\t\t\tw->processed_pkts++;\n+\n+\t\t\t/* release barrier here ensures stored operation\n+\t\t\t * of the event completes before the number of\n+\t\t\t * processed pkts is visible to the main core\n+\t\t\t */\n+\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t} else {\n \t\t\tev.queue_id++;\n \t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n@@ -214,7 +250,13 @@ pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n \t\t\tif (ev[i].queue_id == tx_queue[ev[i].mbuf->port]) {\n \t\t\t\tpipeline_event_tx(dev, port, &ev[i]);\n \t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\tw->processed_pkts++;\n+\n+\t\t\t\t/* release barrier here ensures stored operation\n+\t\t\t\t * of the event completes before the number of\n+\t\t\t\t * processed pkts is visible to the main core\n+\t\t\t\t */\n+\t\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\t\tcontinue;\n \t\t\t}\n \n@@ -254,7 +296,13 @@ pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n \t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t\t\tpipeline_fwd_event(&ev[i],\n \t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n-\t\t\t\tw->processed_pkts++;\n+\n+\t\t\t\t/* release barrier here ensures stored operation\n+\t\t\t\t * of the event completes before the number of\n+\t\t\t\t * processed pkts is visible to the main core\n+\t\t\t\t */\n+\t\t\t\t__atomic_fetch_add(&(w->processed_pkts), 1,\n+\t\t\t\t\t\t__ATOMIC_RELEASE);\n \t\t\t} else {\n \t\t\t\tev[i].queue_id++;\n \t\t\t\tpipeline_fwd_event(&ev[i],\n", "prefixes": [ "RFC", "v1", "4/6" ] }