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GET /api/patches/8548/?format=api
{ "id": 8548, "url": "https://patches.dpdk.org/api/patches/8548/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446508048-16744-3-git-send-email-viktorin@rehivetech.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446508048-16744-3-git-send-email-viktorin@rehivetech.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446508048-16744-3-git-send-email-viktorin@rehivetech.com", "date": "2015-11-02T23:47:15", "name": "[dpdk-dev,v6,02/15] eal/arm: byte order operations for ARM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6313f334ccfba762925dec2c0031b736eb74b69f", "submitter": { "id": 292, "url": "https://patches.dpdk.org/api/people/292/?format=api", "name": "Jan Viktorin", "email": "viktorin@rehivetech.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446508048-16744-3-git-send-email-viktorin@rehivetech.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8548/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8548/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 66E1D8E8C;\n\tTue, 3 Nov 2015 00:50:24 +0100 (CET)", "from wes1-so1.wedos.net (wes1-so1.wedos.net [46.28.106.15])\n\tby dpdk.org (Postfix) with ESMTP id E60018E7E\n\tfor <dev@dpdk.org>; Tue, 3 Nov 2015 00:50:20 +0100 (CET)", "from pcviktorin.fit.vutbr.cz (pcviktorin.fit.vutbr.cz\n\t[147.229.13.147])\n\tby wes1-so1.wedos.net (Postfix) with ESMTPSA id 3nqWFm3w6VzgL;\n\tTue, 3 Nov 2015 00:50:20 +0100 (CET)" ], "From": "Jan Viktorin <viktorin@rehivetech.com>", "To": "david.marchand@6wind.com, David Hunt <david.hunt@intel.com>,\n\tThomas Monjalon <thomas.monjalon@6wind.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>", "Date": "Tue, 3 Nov 2015 00:47:15 +0100", "Message-Id": "<1446508048-16744-3-git-send-email-viktorin@rehivetech.com>", "X-Mailer": "git-send-email 2.6.2", "In-Reply-To": "<1446508048-16744-1-git-send-email-viktorin@rehivetech.com>", "References": "<1446508048-16744-1-git-send-email-viktorin@rehivetech.com>", "Cc": "Vlastimil Kosar <kosar@rehivetech.com>, dev@dpdk.org", "Subject": "[dpdk-dev] [PATCH v6 02/15] eal/arm: byte order operations for ARM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vlastimil Kosar <kosar@rehivetech.com>\n\nThis patch adds architecture specific byte order operations\nfor ARM. The architecture supports both big and little endian.\nIt requires RTE_FORCE_INTRINSICS=y.\n\nSigned-off-by: Vlastimil Kosar <kosar@rehivetech.com>\nSigned-off-by: Jan Viktorin <viktorin@rehivetech.com>\n---\nv4: fix passing params to asm volatile for checkpatch\n\nv6: disable intrinsics, however, fix the bswap16 in older GCC\n---\n .../common/include/arch/arm/rte_byteorder.h | 107 +++++++++++++++++++++\n 1 file changed, 107 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_byteorder.h b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h\nnew file mode 100644\nindex 0000000..3f2dd1f\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h\n@@ -0,0 +1,107 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of RehiveTech nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_BYTEORDER_ARM_H_\n+#define _RTE_BYTEORDER_ARM_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_byteorder.h\"\n+\n+/* fix missing __builtin_bswap16 for gcc older then 4.8 */\n+#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))\n+\n+static inline uint16_t rte_arch_bswap16(uint16_t _x)\n+{\n+\tregister uint16_t x = _x;\n+\n+\tasm volatile (\"rev16 %0,%1\"\n+\t\t : \"=r\" (x)\n+\t\t : \"r\" (x)\n+\t\t );\n+\treturn x;\n+}\n+\n+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \\\n+\t\t\t\t rte_constant_bswap16(x) : \\\n+\t\t\t\t rte_arch_bswap16(x)))\n+#endif\n+\n+/* ARM architecture is bi-endian (both big and little). */\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define rte_cpu_to_le_16(x) (x)\n+#define rte_cpu_to_le_32(x) (x)\n+#define rte_cpu_to_le_64(x) (x)\n+\n+#define rte_cpu_to_be_16(x) rte_bswap16(x)\n+#define rte_cpu_to_be_32(x) rte_bswap32(x)\n+#define rte_cpu_to_be_64(x) rte_bswap64(x)\n+\n+#define rte_le_to_cpu_16(x) (x)\n+#define rte_le_to_cpu_32(x) (x)\n+#define rte_le_to_cpu_64(x) (x)\n+\n+#define rte_be_to_cpu_16(x) rte_bswap16(x)\n+#define rte_be_to_cpu_32(x) rte_bswap32(x)\n+#define rte_be_to_cpu_64(x) rte_bswap64(x)\n+\n+#else /* RTE_BIG_ENDIAN */\n+\n+#define rte_cpu_to_le_16(x) rte_bswap16(x)\n+#define rte_cpu_to_le_32(x) rte_bswap32(x)\n+#define rte_cpu_to_le_64(x) rte_bswap64(x)\n+\n+#define rte_cpu_to_be_16(x) (x)\n+#define rte_cpu_to_be_32(x) (x)\n+#define rte_cpu_to_be_64(x) (x)\n+\n+#define rte_le_to_cpu_16(x) rte_bswap16(x)\n+#define rte_le_to_cpu_32(x) rte_bswap32(x)\n+#define rte_le_to_cpu_64(x) rte_bswap64(x)\n+\n+#define rte_be_to_cpu_16(x) (x)\n+#define rte_be_to_cpu_32(x) (x)\n+#define rte_be_to_cpu_64(x) (x)\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_BYTEORDER_ARM_H_ */\n", "prefixes": [ "dpdk-dev", "v6", "02/15" ] }