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GET /api/patches/8547/?format=api
https://patches.dpdk.org/api/patches/8547/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446508048-16744-2-git-send-email-viktorin@rehivetech.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446508048-16744-2-git-send-email-viktorin@rehivetech.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446508048-16744-2-git-send-email-viktorin@rehivetech.com", "date": "2015-11-02T23:47:14", "name": "[dpdk-dev,v6,01/15] eal/arm: atomic operations for ARM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "37496844afa4265cf9eb01132813e0d1ca6f4b23", "submitter": { "id": 292, "url": "https://patches.dpdk.org/api/people/292/?format=api", "name": "Jan Viktorin", "email": "viktorin@rehivetech.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446508048-16744-2-git-send-email-viktorin@rehivetech.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8547/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8547/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 33EEF8E89;\n\tTue, 3 Nov 2015 00:50:23 +0100 (CET)", "from wes1-so1.wedos.net (wes1-so1.wedos.net [46.28.106.15])\n\tby dpdk.org (Postfix) with ESMTP id B5F2C8E7D\n\tfor <dev@dpdk.org>; Tue, 3 Nov 2015 00:50:20 +0100 (CET)", "from pcviktorin.fit.vutbr.cz (pcviktorin.fit.vutbr.cz\n\t[147.229.13.147])\n\tby wes1-so1.wedos.net (Postfix) with ESMTPSA id 3nqWFm2kzTzgD;\n\tTue, 3 Nov 2015 00:50:20 +0100 (CET)" ], "From": "Jan Viktorin <viktorin@rehivetech.com>", "To": "david.marchand@6wind.com, David Hunt <david.hunt@intel.com>,\n\tThomas Monjalon <thomas.monjalon@6wind.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>", "Date": "Tue, 3 Nov 2015 00:47:14 +0100", "Message-Id": "<1446508048-16744-2-git-send-email-viktorin@rehivetech.com>", "X-Mailer": "git-send-email 2.6.2", "In-Reply-To": "<1446508048-16744-1-git-send-email-viktorin@rehivetech.com>", "References": "<1446508048-16744-1-git-send-email-viktorin@rehivetech.com>", "Cc": "Vlastimil Kosar <kosar@rehivetech.com>, dev@dpdk.org", "Subject": "[dpdk-dev] [PATCH v6 01/15] eal/arm: atomic operations for ARM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vlastimil Kosar <kosar@rehivetech.com>\n\nThis patch adds architecture specific atomic operation file\nfor ARM architecture. The RTE_FORCE_INTRINSICS=y is required.\n\nSigned-off-by: Vlastimil Kosar <kosar@rehivetech.com>\nSigned-off-by: Jan Viktorin <viktorin@rehivetech.com>\n---\nv1 -> v2:\n* improve rte_wmb()\n* use __atomic_* or __sync_*? (may affect the required GCC version)\n\nv4:\n* checkpatch complaints about volatile keyword (but seems to be OK to me)\n* checkpatch complaints about do { ... } while (0) for single statement\n with asm volatile (but I didn't find a way how to write it without\n the checkpatch complaints)\n* checkpatch is now happy with whitespaces\n\nv6:\n* separate for 32/64 architectures\n* drop the atomic implementation and require to use RTE_FORCE_INTRINSICS\n---\n .../common/include/arch/arm/rte_atomic.h | 38 +++++++++++\n .../common/include/arch/arm/rte_atomic_32.h | 74 ++++++++++++++++++++++\n 2 files changed, 112 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\nnew file mode 100644\nindex 0000000..f4f5783\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\n@@ -0,0 +1,38 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of RehiveTech nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_ATOMIC_ARM_H_\n+#define _RTE_ATOMIC_ARM_H_\n+\n+#include <rte_atomic_32.h>\n+\n+#endif /* _RTE_ATOMIC_ARM_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h\nnew file mode 100644\nindex 0000000..9ae1e78\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h\n@@ -0,0 +1,74 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of RehiveTech nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_ATOMIC_ARM32_H_\n+#define _RTE_ATOMIC_ARM32_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ */\n+#define\trte_mb() __sync_synchronize()\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ */\n+#define\trte_wmb() do { asm volatile (\"dmb st\" : : : \"memory\"); } while (0)\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ */\n+#define\trte_rmb() __sync_synchronize()\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_ARM32_H_ */\n", "prefixes": [ "dpdk-dev", "v6", "01/15" ] }{ "id": 8547, "url": "