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GET /api/patches/8541/?format=api
{ "id": 8541, "url": "https://patches.dpdk.org/api/patches/8541/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1446476869-22378-2-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1446476869-22378-2-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1446476869-22378-2-git-send-email-helin.zhang@intel.com", "date": "2015-11-02T15:07:48", "name": "[dpdk-dev,v5,1/2] i40e: add selecting GRE key length", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c58ea16f1d0d987018c52c11e3438f89105f524a", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1446476869-22378-2-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8541/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 686418E7B;\n\tMon, 2 Nov 2015 16:08:03 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id EADDE8E7B\n\tfor <dev@dpdk.org>; Mon, 2 Nov 2015 16:08:00 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 02 Nov 2015 07:08:00 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 02 Nov 2015 07:07:58 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id tA2F7ufi005651;\n\tMon, 2 Nov 2015 23:07:56 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid tA2F7raf022419; Mon, 2 Nov 2015 23:07:55 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id tA2F7rE2022415; \n\tMon, 2 Nov 2015 23:07:53 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,234,1444719600\"; d=\"scan'208\";a=\"592567867\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 2 Nov 2015 23:07:48 +0800", "Message-Id": "<1446476869-22378-2-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1446476869-22378-1-git-send-email-helin.zhang@intel.com>", "References": "<1446180860-28509-1-git-send-email-helin.zhang@intel.com>\n\t<1446476869-22378-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 1/2] i40e: add selecting GRE key length", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "By default, only first 3 bytes of GRE key will be used for hash or FD\ncalculation. With these changes, it can select 3 or 4 bytes of GRE key\nfor hash or FD calculation.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nSigned-off-by: Andrey Chilikin <andrey.chilikin@intel.com>\n---\n doc/guides/rel_notes/release_2_2.rst | 2 +\n drivers/net/i40e/i40e_ethdev.c | 87 ++++++++++++++++++++++++++++++++++--\n lib/librte_ether/rte_eth_ctrl.h | 20 +++++++++\n 3 files changed, 106 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst\nindex f42f0d4..5286233 100644\n--- a/doc/guides/rel_notes/release_2_2.rst\n+++ b/doc/guides/rel_notes/release_2_2.rst\n@@ -61,6 +61,8 @@ New Features\n \n * **Added RSS/FD input set granularity on Intel X710/XL710.**\n \n+* **Added selecting different GRE key length for input set on Intel X710/XL710.**\n+\n \n Resolved Issues\n ---------------\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 75c368f..3c11a2e 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -5597,7 +5597,7 @@ i40e_pf_config_rss(struct i40e_pf *pf)\n \n static int\n i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n-\t\t\tstruct rte_eth_tunnel_filter_conf *filter)\n+\t\t\t struct rte_eth_tunnel_filter_conf *filter)\n {\n \tif (pf == NULL || filter == NULL) {\n \t\tPMD_DRV_LOG(ERR, \"Invalid parameter\");\n@@ -5629,9 +5629,85 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n \treturn 0;\n }\n \n+#define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000\n+#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))\n static int\n-i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n-\t\t\tvoid *arg)\n+i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n+{\n+\tuint32_t val, reg;\n+\tint ret = -EINVAL;\n+\n+\tval = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));\n+\tPMD_DRV_LOG(DEBUG, \"Read original GL_PRS_FVBM with 0x%08x\\n\", val);\n+\n+\tif (len == 3) {\n+\t\treg = val | I40E_GL_PRS_FVBM_MSK_ENA;\n+\t} else if (len == 4) {\n+\t\treg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported GRE key length of %u\", len);\n+\t\treturn ret;\n+\t}\n+\n+\tif (reg != val) {\n+\t\tret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),\n+\t\t\t\t\t\t reg, NULL);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t} else {\n+\t\tret = 0;\n+\t}\n+\tPMD_DRV_LOG(DEBUG, \"Read modified GL_PRS_FVBM with 0x%08x\\n\",\n+\t\t I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)\n+{\n+\tint ret = -EINVAL;\n+\n+\tif (!hw || !cfg)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cfg->cfg_type) {\n+\tcase RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:\n+\t\tret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Unknown config type %u\", cfg->cfg_type);\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,\n+\t\t\t enum rte_filter_op filter_op,\n+\t\t\t void *arg)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret = I40E_ERR_PARAM;\n+\n+\tswitch (filter_op) {\n+\tcase RTE_ETH_FILTER_SET:\n+\t\tret = i40e_dev_global_config_set(hw,\n+\t\t\t(struct rte_eth_global_cfg *)arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown operation %u\", filter_op);\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_tunnel_filter_handle(struct rte_eth_dev *dev,\n+\t\t\t enum rte_filter_op filter_op,\n+\t\t\t void *arg)\n {\n \tstruct rte_eth_tunnel_filter_conf *filter;\n \tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n@@ -5646,6 +5722,7 @@ i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n \tcase RTE_ETH_FILTER_NOP:\n \t\tif (!(pf->flags & I40E_FLAG_VXLAN))\n \t\t\tret = I40E_NOT_SUPPORTED;\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_ADD:\n \t\tret = i40e_dev_tunnel_filter_set(pf, filter, 1);\n \t\tbreak;\n@@ -6639,6 +6716,10 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \n \tswitch (filter_type) {\n+\tcase RTE_ETH_FILTER_NONE:\n+\t\t/* For global configuration */\n+\t\tret = i40e_filter_ctrl_global_config(dev, filter_op, arg);\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_HASH:\n \t\tret = i40e_hash_filter_ctrl(dev, filter_op, arg);\n \t\tbreak;\ndiff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h\nindex ae73c36..f71669c 100644\n--- a/lib/librte_ether/rte_eth_ctrl.h\n+++ b/lib/librte_ether/rte_eth_ctrl.h\n@@ -295,6 +295,26 @@ struct rte_eth_tunnel_filter_conf {\n \tuint16_t queue_id; /** < queue number. */\n };\n \n+/**\n+ * Global eth device configuration type.\n+ */\n+enum rte_eth_global_cfg_type {\n+\tRTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,\n+\tRTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,\n+\tRTE_ETH_GLOBAL_CFG_TYPE_MAX,\n+};\n+\n+/**\n+ * Global eth device configuration.\n+ */\n+struct rte_eth_global_cfg {\n+\tenum rte_eth_global_cfg_type cfg_type; /**< Global config type. */\n+\tunion {\n+\t\tuint8_t gre_key_len; /**< Valid GRE key length in byte. */\n+\t\tuint64_t reserved; /**< Reserve space for future use. */\n+\t} cfg;\n+};\n+\n #define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */\n #define RTE_ETH_INSET_SIZE_MAX 128 /** < Max length of input set. */\n \n", "prefixes": [ "dpdk-dev", "v5", "1/2" ] }