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{
    "id": 85315,
    "url": "https://patches.dpdk.org/api/patches/85315/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1608205475-20067-11-git-send-email-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1608205475-20067-11-git-send-email-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-11-git-send-email-michaelba@nvidia.com",
    "date": "2020-12-17T11:44:28",
    "name": "[10/17] common/mlx5: share DevX SQ creation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "5b825b6fb2bb161656051836d9c73827569a05b7",
    "submitter": {
        "id": 1949,
        "url": "https://patches.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1608205475-20067-11-git-send-email-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 14348,
            "url": "https://patches.dpdk.org/api/series/14348/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14348",
            "date": "2020-12-17T11:44:23",
            "name": "common/mlx5: share DevX resources creations",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/14348/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/85315/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/85315/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 545FAA09F6;\n\tThu, 17 Dec 2020 12:47:28 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8DEDECA64;\n\tThu, 17 Dec 2020 12:45:10 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id AB955CA26\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:50 +0200",
            "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2Z004524;\n Thu, 17 Dec 2020 13:44:50 +0200"
        ],
        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Date": "Thu, 17 Dec 2020 11:44:28 +0000",
        "Message-Id": "<1608205475-20067-11-git-send-email-michaelba@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH 10/17] common/mlx5: share DevX SQ creation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The SQ object in DevX is created in several places and in several\ndifferent drivers.\nIn all places almost all the details are the same, and in particular the\nallocations of the required resources.\n\nAdd a structure that contains all the resources, and provide creation\nand release functions for it.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_devx.c | 122 +++++++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common_devx.h |  20 +++++-\n 2 files changed, 140 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c\nindex 324c6ea..46404d8 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.c\n+++ b/drivers/common/mlx5/mlx5_common_devx.c\n@@ -155,3 +155,125 @@\n \trte_errno = ret;\n \treturn -rte_errno;\n }\n+\n+/**\n+ * Destroy DevX Send Queue.\n+ *\n+ * @param[in] sq\n+ *   DevX SQ to destroy.\n+ */\n+void\n+mlx5_devx_sq_destroy(struct mlx5_devx_sq *sq)\n+{\n+\tif (sq->sq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sq->sq));\n+\tif (sq->umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(sq->umem_obj));\n+\tif (sq->umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)sq->umem_buf);\n+}\n+\n+/**\n+ * Create Send Queue using DevX API.\n+ *\n+ * Get a pointer to partially initialized attributes structure, and updates the\n+ * following fields:\n+ *   wq_type\n+ *   wq_umem_valid\n+ *   wq_umem_id\n+ *   wq_umem_offset\n+ *   dbr_umem_valid\n+ *   dbr_umem_id\n+ *   dbr_addr\n+ *   log_wq_stride\n+ *   log_wq_sz\n+ *   log_wq_pg_sz\n+ * All other fields are updated by caller.\n+ *\n+ * @param[in] ctx\n+ *   Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] sq_obj\n+ *   Pointer to SQ to create.\n+ * @param[in] log_wqbb_n\n+ *   Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ *   Pointer to SQ attributes structure.\n+ * @param[in] socket\n+ *   Socket to use for allocation.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n,\n+\t\t    struct mlx5_devx_create_sq_attr *attr, int socket)\n+{\n+\tstruct mlx5_devx_obj *sq = NULL;\n+\tstruct mlx5dv_devx_umem *umem_obj = NULL;\n+\tvoid *umem_buf = NULL;\n+\tsize_t page_size = rte_mem_page_size();\n+\tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n+\tuint32_t umem_size, umem_dbrec;\n+\tuint16_t sq_size = 1 << log_wqbb_n;\n+\tint ret;\n+\n+\tif (page_size == (size_t)-1 || alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get page_size.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Allocate memory buffer for WQEs and doorbell record. */\n+\tumem_size = MLX5_WQE_SIZE * sq_size;\n+\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\tumem_size += MLX5_DBR_SIZE;\n+\tumem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n+\t\t\t       alignment, socket);\n+\tif (!umem_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for SQ.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Register allocated buffer in user space with DevX. */\n+\tumem_obj = mlx5_glue->devx_umem_reg(ctx, (void *)(uintptr_t)umem_buf,\n+\t\t\t\t\t    umem_size, IBV_ACCESS_LOCAL_WRITE);\n+\tif (!umem_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to register umem for SQ.\");\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\t/* Fill attributes for SQ object creation. */\n+\tattr->wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n+\tattr->wq_attr.wq_umem_valid = 1;\n+\tattr->wq_attr.wq_umem_id = mlx5_os_get_umem_id(sq_obj->umem_obj);\n+\tattr->wq_attr.wq_umem_offset = 0;\n+\tattr->wq_attr.dbr_umem_valid = 1;\n+\tattr->wq_attr.dbr_umem_id = attr->wq_attr.wq_umem_id;\n+\tattr->wq_attr.dbr_addr = umem_dbrec;\n+\tattr->wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n+\tattr->wq_attr.log_wq_sz = log_wqbb_n;\n+\tattr->wq_attr.log_wq_pg_sz = rte_log2_u32(page_size);\n+\t/* Create send queue object with DevX. */\n+\tsq = mlx5_devx_cmd_create_sq(ctx, attr);\n+\tif (!sq) {\n+\t\tDRV_LOG(ERR, \"Can't create DevX SQ object.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tsq_obj->umem_buf = umem_buf;\n+\tsq_obj->umem_obj = umem_obj;\n+\tsq_obj->sq = sq;\n+\tsq_obj->db_rec = RTE_PTR_ADD(sq_obj->umem_buf, umem_dbrec);\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tif (sq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sq));\n+\tif (umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(umem_obj));\n+\tif (umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)umem_buf);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\n+\n+\ndiff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h\nindex 31cb804..88d520b 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.h\n+++ b/drivers/common/mlx5/mlx5_common_devx.h\n@@ -18,11 +18,27 @@ struct mlx5_devx_cq {\n \tvolatile uint32_t *db_rec; /* The CQ doorbell record. */\n };\n \n+/* DevX Send Queue structure. */\n+struct mlx5_devx_sq {\n+\tstruct mlx5_devx_obj *sq; /* The SQ DevX object. */\n+\tstruct mlx5dv_devx_umem *umem_obj; /* The SQ umem object. */\n+\tunion {\n+\t\tvolatile void *umem_buf;\n+\t\tvolatile struct mlx5_wqe *wqes; /* The SQ ring buffer. */\n+\t};\n+\tvolatile uint32_t *db_rec; /* The SQ doorbell record. */\n+};\n+\n+\n /* mlx5_common_devx.c */\n \n void mlx5_devx_cq_destroy(struct mlx5_devx_cq *cq);\n int mlx5_devx_cq_create(void *ctx, struct mlx5_devx_cq *cq_obj,\n-\t\t\tuint16_t log_desc_n, struct mlx5_devx_cq_attr *attr,\n-\t\t\tint socket);\n+\t\t\tuint16_t log_desc_n,\n+\t\t\tstruct mlx5_devx_cq_attr *attr, int socket);\n+void mlx5_devx_sq_destroy(struct mlx5_devx_sq *sq);\n+int mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj,\n+\t\t\tuint16_t log_wqbb_n,\n+\t\t\tstruct mlx5_devx_create_sq_attr *attr, int socket);\n \n #endif /* RTE_PMD_MLX5_COMMON_DEVX_H_ */\n",
    "prefixes": [
        "10/17"
    ]
}