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GET /api/patches/85248/?format=api
{ "id": 85248, "url": "https://patches.dpdk.org/api/patches/85248/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201216142511.13660-6-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201216142511.13660-6-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201216142511.13660-6-shirik@nvidia.com", "date": "2020-12-16T14:25:10", "name": "[RFC,5/6] net/mlx5: add GTP PSC item translation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "01b9975d10941c757805e29b45cbd86fcfde908d", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201216142511.13660-6-shirik@nvidia.com/mbox/", "series": [ { "id": 14332, "url": "https://patches.dpdk.org/api/series/14332/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14332", "date": "2020-12-16T14:25:05", "name": "add GTP PSC extension header support", "version": 1, "mbox": "https://patches.dpdk.org/series/14332/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85248/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85248/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E98EBA09EF;\n\tWed, 16 Dec 2020 15:26:44 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2EF46C9EE;\n\tWed, 16 Dec 2020 15:25:35 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 149E1C9D6\n for <dev@dpdk.org>; Wed, 16 Dec 2020 15:25:31 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 16 Dec 2020 16:25:28 +0200", "from nvidia.com (c-236-2-60-065.mtl.labs.mlnx [10.236.2.65])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BGEPF6g015188;\n Wed, 16 Dec 2020 16:25:28 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, rasland@nvidia.com", "Date": "Wed, 16 Dec 2020 16:25:10 +0200", "Message-Id": "<20201216142511.13660-6-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20201216142511.13660-1-shirik@nvidia.com>", "References": "<1599118768-13265-1-git-send-email-shirik@nvidia.com>\n <20201216142511.13660-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [RFC 5/6] net/mlx5: add GTP PSC item translation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds the translation function which\nsets the qfi, PDU type.\n\nThe next extension header which indicates the following\nextension header type is set to 0x85 - a PDU session\ncontainer.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 85 +++++++++++++++++++++++++++++++++\n 1 file changed, 85 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 4f7a756214..897f70c22c 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7903,6 +7903,81 @@ flow_dv_translate_item_gtp(void *matcher, void *key,\n \t\t rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));\n }\n \n+/**\n+ * Add GTP PSC item to matcher.\n+ *\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ */\n+static int\n+flow_dv_translate_item_gtp_psc(void *matcher, void *key,\n+\t\t\t const struct rte_flow_item *item)\n+{\n+\tconst struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;\n+\tconst struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;\n+\tvoid *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,\n+\t\t\tmisc_parameters_3);\n+\tvoid *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);\n+\tunion {\n+\t\tuint32_t w32;\n+\t\tstruct {\n+\t\t\tuint16_t seq_num;\n+\t\t\tuint8_t npdu_num;\n+\t\t\tuint8_t next_ext_header_type;\n+\t\t};\n+\t} dw_2;\n+\tuint8_t gtp_flags;\n+\n+\t/* Always set E-flag match on one, regardless of GTP item settings. */\n+\tgtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);\n+\tgtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;\n+\tMLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);\n+\tgtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);\n+\tgtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;\n+\tMLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);\n+\t/*Set next extension header type. */\n+\tdw_2.seq_num = 0;\n+\tdw_2.npdu_num = 0;\n+\tdw_2.next_ext_header_type = 0xff;\n+\tMLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,\n+\t\t rte_cpu_to_be_32(dw_2.w32));\n+\tdw_2.seq_num = 0;\n+\tdw_2.npdu_num = 0;\n+\tdw_2.next_ext_header_type = 0x85;\n+\tMLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,\n+\t\t rte_cpu_to_be_32(dw_2.w32));\n+\tif (gtp_psc_v) {\n+\t\tunion {\n+\t\t\tuint32_t w32;\n+\t\t\tstruct {\n+\t\t\t\tuint8_t len;\n+\t\t\t\tuint8_t pdu_type;\n+\t\t\t\tuint8_t qfi;\n+\t\t\t\tuint8_t reserved;\n+\t\t\t};\n+\t\t} dw_0;\n+\n+\t\t/*Set extension header PDU type and Qos. */\n+\t\tif (!gtp_psc_m)\n+\t\t\tgtp_psc_m = &rte_flow_item_gtp_psc_mask;\n+\t\tdw_0.w32 = 0;\n+\t\tdw_0.pdu_type = gtp_psc_m->pdu_type;\n+\t\tdw_0.qfi = gtp_psc_m->qfi;\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,\n+\t\t\t rte_cpu_to_be_32(dw_0.w32));\n+\t\tdw_0.w32 = 0;\n+\t\tdw_0.pdu_type = gtp_psc_v->pdu_type & gtp_psc_m->pdu_type;\n+\t\tdw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,\n+\t\t\t rte_cpu_to_be_32(dw_0.w32));\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Add eCPRI item to matcher and to the value.\n *\n@@ -10585,6 +10660,16 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tmatcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);\n \t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n+\t\t\tret = flow_dv_translate_item_gtp_psc(match_mask,\n+\t\t\t\t\t\t\t match_value,\n+\t\t\t\t\t\t\t items);\n+\t\t\tif (ret)\n+\t\t\t\treturn rte_flow_error_set(error, -ret,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t\"cannot create GTP PSC item\");\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GTP_PSC;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_ECPRI:\n \t\t\tif (!mlx5_flex_parser_ecpri_exist(dev)) {\n \t\t\t\t/* Create it only the first time to be used. */\n", "prefixes": [ "RFC", "5/6" ] }