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GET /api/patches/85236/?format=api
{ "id": 85236, "url": "https://patches.dpdk.org/api/patches/85236/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1608123735-3662-4-git-send-email-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1608123735-3662-4-git-send-email-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1608123735-3662-4-git-send-email-shirik@nvidia.com", "date": "2020-12-16T13:02:10", "name": "[RFC,v3,3/8] common/mlx5: check GENEVE TLV support in HCA attributes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b6b3f28d818abb4e9433f99e2bb75cd85fdec320", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1608123735-3662-4-git-send-email-shirik@nvidia.com/mbox/", "series": [ { "id": 14330, "url": "https://patches.dpdk.org/api/series/14330/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14330", "date": "2020-12-16T13:02:07", "name": "ethdev: introduce GENEVE header TLV option item", "version": 3, "mbox": "https://patches.dpdk.org/series/14330/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85236/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/85236/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB798A09EF;\n\tWed, 16 Dec 2020 14:03:08 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 35FECC9C4;\n\tWed, 16 Dec 2020 14:02:51 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id D0CF3C9C2\n for <dev@dpdk.org>; Wed, 16 Dec 2020 14:02:49 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 16 Dec 2020 15:02:44 +0200", "from nvidia.com (nps-server-11.mtl.labs.mlnx [10.7.12.71])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BGD2M1C011463;\n Wed, 16 Dec 2020 15:02:44 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, rasland@nvidia.com", "Date": "Wed, 16 Dec 2020 15:02:10 +0200", "Message-Id": "<1608123735-3662-4-git-send-email-shirik@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1608123735-3662-1-git-send-email-shirik@nvidia.com>", "References": "<1599118768-13265-1-git-send-email-shirik@nvidia.com>\n <1608123735-3662-1-git-send-email-shirik@nvidia.com>", "Subject": "[dpdk-dev] [RFC v3 3/8] common/mlx5: check GENEVE TLV support in\n\tHCA attributes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is preparation step to support match on GENEVE TLV option.\n\nIn this Patch we add the HCA attributes that will allow\nsupporting GENEVE TLV option matching.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 4 ++++\n drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++---\n 3 files changed, 36 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 9c1d188..a6d052d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -693,6 +693,10 @@ struct mlx5_devx_obj *\n \tattr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);\n \tattr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t flex_parser_protocols);\n+\tattr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tmax_geneve_tlv_options);\n+\tattr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tmax_geneve_tlv_option_data_len);\n \tattr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);\n \tattr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n@@ -720,6 +724,9 @@ struct mlx5_devx_obj *\n \tattr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n \t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);\n+\tattr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 726e9f5..58e619f 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -96,6 +96,8 @@ struct mlx5_hca_attr {\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\n+\tuint32_t max_geneve_tlv_options;\n+\tuint32_t max_geneve_tlv_option_data_len;\n \tuint32_t hairpin:1;\n \tuint32_t log_max_hairpin_queues:5;\n \tuint32_t log_max_hairpin_wq_data_sz:5;\n@@ -115,6 +117,7 @@ struct mlx5_hca_attr {\n \tuint32_t regex:1;\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n+\tuint32_t geneve_tlv_opt;\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n };\n@@ -469,6 +472,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,\n __rte_internal\n int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,\n \t\t\t\tuint32_t arg, uint32_t *data, uint32_t dw_cnt);\n+\n /**\n * Create virtio queue counters object DevX API.\n *\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 58d1804..5b20533 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -787,7 +787,7 @@ struct mlx5_ifc_fte_match_set_misc3_bits {\n \tu8 icmp_code[0x8];\n \tu8 icmpv6_type[0x8];\n \tu8 icmpv6_code[0x8];\n-\tu8 reserved_at_120[0x20];\n+\tu8 geneve_tlv_option_0_data[0x20];\n \tu8 gtpu_teid[0x20];\n \tu8 gtpu_msg_type[0x08];\n \tu8 gtpu_msg_flags[0x08];\n@@ -1065,6 +1065,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n+\t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -1363,8 +1365,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_500[0x20];\n \tu8 num_of_uars_per_page[0x20];\n \tu8 flex_parser_protocols[0x20];\n-\tu8 reserved_at_560[0x20];\n-\tu8 reserved_at_580[0x3c];\n+\tu8 max_geneve_tlv_options[0x8];\n+\tu8 reserved_at_568[0x3];\n+\tu8 max_geneve_tlv_option_data_len[0x5];\n+\tu8 reserverd_at_570[0x4c];\n \tu8 mini_cqe_resp_stride_index[0x1];\n \tu8 cqe_128_always[0x1];\n \tu8 cqe_compression_128[0x1];\n@@ -2232,6 +2236,7 @@ struct mlx5_ifc_create_cq_in_bits {\n };\n \n enum {\n+\tMLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n@@ -2266,6 +2271,17 @@ struct mlx5_ifc_virtio_q_counters_bits {\n \tu8 reserved_at_180[0x50];\n };\n \n+struct mlx5_ifc_geneve_tlv_option_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x18];\n+\tu8 geneve_option_fte_index[0x8];\n+\tu8 option_class[0x10];\n+\tu8 option_type[0x8];\n+\tu8 reserved_at_78[0x3];\n+\tu8 option_data_length[0x5];\n+\tu8 reserved_at_80[0x180];\n+};\n+\n struct mlx5_ifc_create_virtio_q_counters_in_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n@@ -2275,6 +2291,12 @@ struct mlx5_ifc_query_virtio_q_counters_out_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n };\n+\n+struct mlx5_ifc_create_geneve_tlv_option_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n+};\n+\n enum {\n \tMLX5_VIRTQ_STATE_INIT = 0,\n \tMLX5_VIRTQ_STATE_RDY = 1,\n", "prefixes": [ "RFC", "v3", "3/8" ] }