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GET /api/patches/85188/?format=api
{ "id": 85188, "url": "https://patches.dpdk.org/api/patches/85188/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201215073119.404947-3-lizh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201215073119.404947-3-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201215073119.404947-3-lizh@nvidia.com", "date": "2020-12-15T07:31:13", "name": "[RFC,2/8] common/mlx5: add definitions for ASO flow meter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1ad65c53f695f1e07869e3937dce1c01ec1f2769", "submitter": { "id": 1967, "url": "https://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201215073119.404947-3-lizh@nvidia.com/mbox/", "series": [ { "id": 14302, "url": "https://patches.dpdk.org/api/series/14302/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14302", "date": "2020-12-15T07:31:11", "name": "net/mlx5: enhancement metering support", "version": 1, "mbox": "https://patches.dpdk.org/series/14302/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85188/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B04D4A09E9;\n\tTue, 15 Dec 2020 08:32:10 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0BE74C9BC;\n\tTue, 15 Dec 2020 08:31:42 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id D3510C9BC\n for <dev@dpdk.org>; Tue, 15 Dec 2020 08:31:40 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 15 Dec 2020 09:31:35 +0200", "from nvidia.com (c-236-2-240-245.mtl.labs.mlnx [10.236.2.245])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BF7VOkE005436;\n Tue, 15 Dec 2020 09:31:35 +0200" ], "From": "Li Zhang <lizh@nvidia.com>", "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com", "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com", "Date": "Tue, 15 Dec 2020 09:31:13 +0200", "Message-Id": "<20201215073119.404947-3-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20201215073119.404947-1-lizh@nvidia.com>", "References": "<20201215073119.404947-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [RFC 2/8] common/mlx5: add definitions for ASO flow meter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds different PRM definitions, related to ASO flow meter\nfeature, in MLX5 PMD code.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 75 ++++++++++++++++++++++++++++++++--\n 1 file changed, 71 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 48fe54625f..de85b05066 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1066,6 +1066,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n \t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n \n@@ -1418,7 +1420,15 @@ struct mlx5_ifc_qos_cap_bits {\n \tu8 reserved_at_c0[0x10];\n \tu8 max_qos_para_vport[0x10];\n \tu8 max_tsar_bw_share[0x20];\n-\tu8 reserved_at_100[0x6e8];\n+\tu8 nic_element_type[0x10];\n+\tu8 nic_tsar_type[0x10];\n+\tu8 reserved_at_120[0x3];\n+\tu8 log_meter_aso_granularity[0x5];\n+\tu8 reserved_at_128[0x3];\n+\tu8 log_meter_aso_max_alloc[0x5];\n+\tu8 reserved_at_130[0x3];\n+\tu8 log_max_num_meter_aso[0x5];\n+\tu8 reserved_at_138[0x6b0];\n };\n \n struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n@@ -2159,6 +2169,8 @@ struct mlx5_ifc_flow_meter_parameters_bits {\n \tu8 eir_mantissa[0x8];\n \tu8 reserved_at_8[0x60];\t\t// 14h-1Ch\n };\n+#define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)\n+#define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8\n \n enum {\n \tMLX5_CQE_SIZE_64B = 0x0,\n@@ -2243,6 +2255,7 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n+\tMLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,\n };\n \n@@ -2251,7 +2264,9 @@ struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n \tu8 reserved_at_10[0x20];\n \tu8 obj_type[0x10];\n \tu8 obj_id[0x20];\n-\tu8 reserved_at_60[0x20];\n+\tu8 reserved_at_60[0x3];\n+\tu8 log_obj_range[0x5];\n+\tu8 reserved_at_58[0x18];\n };\n \n struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n@@ -2393,6 +2408,18 @@ struct mlx5_ifc_create_flow_hit_aso_in_bits {\n \tstruct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;\n };\n \n+struct mlx5_ifc_flow_meter_aso_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x48];\n+\tu8 access_pd[0x18];\n+\tu8 reserved_at_a0[0x160];\n+\tu8 parameters[0x200];\n+};\n+\n+struct mlx5_ifc_create_flow_meter_aso_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;\n+};\n enum mlx5_access_aso_opc_mod {\n \tASO_OPC_MOD_IPSEC = 0x0,\n \tASO_OPC_MOD_CONNECTION_TRACKING = 0x1,\n@@ -2446,11 +2473,51 @@ struct mlx5_aso_cseg {\n \tuint64_t data_mask;\n } __rte_packed;\n \n+/* A meter data segment - 2 per ASO WQE. */\n+struct mlx5_aso_mtr_dseg {\n+\tuint32_t v_bo_sc_bbog_mm;\n+\t/*\n+\t * bit 31: valid, 30: bucket overflow, 28-29: start color,\n+\t * 27: both buckets on green, 24-25: meter mode.\n+\t */\n+\tuint32_t reserved;\n+\tuint32_t cbs_cir;\n+\t/*\n+\t * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,\n+\t * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.\n+\t */\n+\tuint32_t c_tokens;\n+\tuint32_t ebs_eir;\n+\t/*\n+\t * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,\n+\t * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.\n+\t */\n+\tuint32_t e_tokens;\n+\tuint64_t timestamp;\n+} __rte_packed;\n+\n+#define ASO_DSEG_VALID_OFFSET\t 31\n+#define ASO_DSEG_BO_OFFSET\t 30\n+#define ASO_DSEG_SC_OFFSET\t 28\n+#define ASO_DSEG_CBS_EXP_OFFSET\t 24\n+#define ASO_DSEG_CBS_MAN_OFFSET\t 16\n+#define ASO_DSEG_CIR_EXP_MASK\t 0x1F\n+#define ASO_DSEG_CIR_EXP_OFFSET\t 8\n+#define ASO_DSEG_EBS_EXP_OFFSET\t 24\n+#define ASO_DSEG_EBS_MAN_OFFSET\t 16\n+#define ASO_DSEG_EXP_MASK\t 0x1F\n+#define ASO_DSEG_MAN_MASK\t 0xFF\n+\n #define MLX5_ASO_WQE_DSEG_SIZE\t0x40\n+#define MLX5_ASO_METERS_PER_WQE 2\n+#define MLX5_ASO_MTRS_PER_POOL 128\n \n-/* ASO WQE Data segment. */\n+/* ASO WQE data segment. */\n struct mlx5_aso_dseg {\n-\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n+\tunion {\n+\t\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n+\t\tstruct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];\n+\t};\n } __rte_packed;\n \n /* ASO WQE. */\n", "prefixes": [ "RFC", "2/8" ] }