get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/85159/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 85159,
    "url": "https://patches.dpdk.org/api/patches/85159/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201215060519.302145-3-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201215060519.302145-3-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201215060519.302145-3-qi.z.zhang@intel.com",
    "date": "2020-12-15T06:04:54",
    "name": "[02/27] net/ice/base: increased control queue timeout",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d105f51513781a0d9aca03ce2ccca994eb415603",
    "submitter": {
        "id": 504,
        "url": "https://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201215060519.302145-3-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 14300,
            "url": "https://patches.dpdk.org/api/series/14300/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14300",
            "date": "2020-12-15T06:04:52",
            "name": "ice base code update",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/14300/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/85159/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/85159/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 167C0A09E9;\n\tTue, 15 Dec 2020 07:02:13 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 66FDAC99E;\n\tTue, 15 Dec 2020 07:01:34 +0100 (CET)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 618F8DE0\n for <dev@dpdk.org>; Tue, 15 Dec 2020 07:01:30 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Dec 2020 22:01:28 -0800",
            "from dpdk51.sh.intel.com ([10.67.111.142])\n by orsmga002.jf.intel.com with ESMTP; 14 Dec 2020 22:01:27 -0800"
        ],
        "IronPort-SDR": [
            "\n SKCogV7bS4QexsEaGw8lxhzo+BANrb8CqNW2YTNxGEQoR0ls0NNwnlGmtxYaLYatiWOPJ6WCWM\n lirQOHFJh6Kw==",
            "\n Ebiw0sBLnL6ekYtAytm0y/iEvfCv5F2GzY9yc72iNLQaVubHUbFE68xc9speRnuzJidb0kJF1s\n +F8hViLwxsSw=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9835\"; a=\"193200213\"",
            "E=Sophos;i=\"5.78,420,1599548400\"; d=\"scan'208\";a=\"193200213\"",
            "E=Sophos;i=\"5.78,420,1599548400\"; d=\"scan'208\";a=\"351723305\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Fabio Pricoco <fabio.pricoco@intel.com>",
        "Date": "Tue, 15 Dec 2020 14:04:54 +0800",
        "Message-Id": "<20201215060519.302145-3-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.26.2",
        "In-Reply-To": "<20201215060519.302145-1-qi.z.zhang@intel.com>",
        "References": "<20201215060519.302145-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 02/27] net/ice/base: increased control queue\n\ttimeout",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "250 msec timeout is insufficient for some AQ commands. Advice from FW\nteam was to increase the timeout. Increased to 1 second.\n\nSigned-off-by: Fabio Pricoco <fabio.pricoco@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_controlq.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h\nindex e5e0001788..84c114f7a4 100644\n--- a/drivers/net/ice/base/ice_controlq.h\n+++ b/drivers/net/ice/base/ice_controlq.h\n@@ -32,8 +32,8 @@ enum ice_ctl_q {\n \tICE_CTL_Q_MAILBOX,\n };\n \n-/* Control Queue timeout settings - max delay 250ms */\n-#define ICE_CTL_Q_SQ_CMD_TIMEOUT\t2500  /* Count 2500 times */\n+/* Control Queue timeout settings - max delay 1s */\n+#define ICE_CTL_Q_SQ_CMD_TIMEOUT\t10000 /* Count 10000 times */\n #define ICE_CTL_Q_SQ_CMD_USEC\t\t100   /* Check every 100usec */\n #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT\t10    /* Count 10 times */\n #define ICE_CTL_Q_ADMIN_INIT_MSEC\t100   /* Check every 100msec */\n",
    "prefixes": [
        "02/27"
    ]
}