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GET /api/patches/84215/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 84215,
    "url": "https://patches.dpdk.org/api/patches/84215/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201116091326.10511-4-getelson@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201116091326.10511-4-getelson@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201116091326.10511-4-getelson@nvidia.com",
    "date": "2020-11-16T09:13:23",
    "name": "[v3,3/6] net/mlx5: fix structure passing method in function call",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "91f5ecea500b128bbb559a25360e64b41826fd12",
    "submitter": {
        "id": 1882,
        "url": "https://patches.dpdk.org/api/people/1882/?format=api",
        "name": "Gregory Etelson",
        "email": "getelson@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201116091326.10511-4-getelson@nvidia.com/mbox/",
    "series": [
        {
            "id": 13899,
            "url": "https://patches.dpdk.org/api/series/13899/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13899",
            "date": "2020-11-16T09:13:20",
            "name": "restore tunnel offload functionality in mlx5",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/13899/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/84215/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/84215/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 257D9A04DB;\n\tMon, 16 Nov 2020 10:14:51 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D8D01C914;\n\tMon, 16 Nov 2020 10:13:52 +0100 (CET)",
            "from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com\n [216.228.121.64]) by dpdk.org (Postfix) with ESMTP id 0123EC902\n for <dev@dpdk.org>; Mon, 16 Nov 2020 10:13:49 +0100 (CET)",
            "from hqmail.nvidia.com (Not Verified[216.228.121.13]) by\n hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA)\n id <B5fb242c40000>; Mon, 16 Nov 2020 01:13:40 -0800",
            "from nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13)\n with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n Mon, 16 Nov 2020 09:13:45 +0000"
        ],
        "From": "Gregory Etelson <getelson@nvidia.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Shahaf Shuler\n <shahafs@nvidia.com>",
        "Date": "Mon, 16 Nov 2020 11:13:23 +0200",
        "Message-ID": "<20201116091326.10511-4-getelson@nvidia.com>",
        "X-Mailer": "git-send-email 2.29.2",
        "In-Reply-To": "<20201116091326.10511-1-getelson@nvidia.com>",
        "References": "<20201111071417.21177-1-getelson@nvidia.com>\n <20201116091326.10511-1-getelson@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "quoted-printable",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.124.1.5]",
        "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n t=1605518020; bh=dBLrfjTzWKBnUmvo/6TPCg+6xgVFZ4cpCpbC6CAEI1M=;\n h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:\n References:MIME-Version:Content-Transfer-Encoding:Content-Type:\n X-Originating-IP:X-ClientProxiedBy;\n b=EeCh8VOeaIQxcgFs0UqK6oqUPooVsl/98W81SEPmZZ1BOipOjCkfBfFJ1FnjAcyZF\n QRwDlN/i5rMAGo7SqGSxiC2RIn1X+aIB+hdoZIdfXx7vAeUd6U4rLmUuRB/EGoxFLt\n i1lfgVObmBo9C8PUrycxHE3hAMGqHAYMHkkQq2DFWWfESUkz0QYthIDHK03/vKamhr\n Z3JhI2XYMPUpbya5buVbDuvjTNVP0rOzHVT6hA3fToejbbwAhSMcUUsZ2gXAYknE6T\n fD3CvNnn7tpcyPd7p1rRm3sTRvhF97MzsF1yti3y/3F2BYBGyqzIzu7VYZTjOJiByN\n yZ5YfbJ0JNocg==",
        "Subject": "[dpdk-dev] [PATCH v3 3/6] net/mlx5: fix structure passing method in\n\tfunction call",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Tunnel offload implementation introduced 64 bit-field flow_grp_info\nstructure. Since the structure size is 64 bits, the code passed that\ntype by value in function calls.\n\nThe patch changes that structure passing method to reference.\n\nFixes: 4ec6360de37d (\"net/mlx5: implement tunnel offload\")\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c    | 20 +++++++++++---------\n drivers/net/mlx5/mlx5_flow.h    |  4 ++--\n drivers/net/mlx5/mlx5_flow_dv.c | 10 +++++-----\n 3 files changed, 18 insertions(+), 16 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex e4fe78df4c..4216d3d18d 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -6769,9 +6769,11 @@ mlx5_flow_tunnel_grp2tbl_create_cb(struct mlx5_hlist *list,\n \n static int\n flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table,\n-\t\t    struct flow_grp_info grp_info, struct rte_flow_error *error)\n+\t\t    const struct flow_grp_info *grp_info,\n+\t\t    struct rte_flow_error *error)\n {\n-\tif (grp_info.transfer && grp_info.external && grp_info.fdb_def_rule) {\n+\tif (grp_info->transfer && grp_info->external &&\n+\t    grp_info->fdb_def_rule) {\n \t\tif (group == UINT32_MAX)\n \t\t\treturn rte_flow_error_set\n \t\t\t\t\t\t(error, EINVAL,\n@@ -6828,25 +6830,25 @@ int\n mlx5_flow_group_to_table(struct rte_eth_dev *dev,\n \t\t\t const struct mlx5_flow_tunnel *tunnel,\n \t\t\t uint32_t group, uint32_t *table,\n-\t\t\t struct flow_grp_info grp_info,\n+\t\t\t const struct flow_grp_info *grp_info,\n \t\t\t struct rte_flow_error *error)\n {\n \tint ret;\n \tbool standard_translation;\n \n-\tif (!grp_info.skip_scale && grp_info.external &&\n+\tif (!grp_info->skip_scale && grp_info->external &&\n \t    group < MLX5_MAX_TABLES_EXTERNAL)\n \t\tgroup *= MLX5_FLOW_TABLE_FACTOR;\n \tif (is_tunnel_offload_active(dev)) {\n-\t\tstandard_translation = !grp_info.external ||\n-\t\t\t\t\tgrp_info.std_tbl_fix;\n+\t\tstandard_translation = !grp_info->external ||\n+\t\t\t\t\tgrp_info->std_tbl_fix;\n \t} else {\n \t\tstandard_translation = true;\n \t}\n \tDRV_LOG(DEBUG,\n \t\t\"port %u group=%#x transfer=%d external=%d fdb_def_rule=%d translate=%s\",\n-\t\tdev->data->port_id, group, grp_info.transfer,\n-\t\tgrp_info.external, grp_info.fdb_def_rule,\n+\t\tdev->data->port_id, group, grp_info->transfer,\n+\t\tgrp_info->external, grp_info->fdb_def_rule,\n \t\tstandard_translation ? \"STANDARD\" : \"TUNNEL\");\n \tif (standard_translation)\n \t\tret = flow_group_to_table(dev->data->port_id, group, table,\n@@ -7343,7 +7345,7 @@ flow_tunnel_add_default_miss(struct rte_eth_dev *dev,\n \tmiss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY;\n \tmiss_attr.group = jump_data->group;\n \tret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group,\n-\t\t\t\t       &flow_table, grp_info, error);\n+\t\t\t\t       &flow_table, &grp_info, error);\n \tif (ret)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t  RTE_FLOW_ERROR_TYPE_ACTION_CONF,\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex fbc6173fcb..c33c0fee7c 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1273,8 +1273,8 @@ tunnel_use_standard_attr_group_translate\n int mlx5_flow_group_to_table(struct rte_eth_dev *dev,\n \t\t\t     const struct mlx5_flow_tunnel *tunnel,\n \t\t\t     uint32_t group, uint32_t *table,\n-\t\t\t     struct flow_grp_info flags,\n-\t\t\t\t struct rte_flow_error *error);\n+\t\t\t     const struct flow_grp_info *flags,\n+\t\t\t     struct rte_flow_error *error);\n uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,\n \t\t\t\t     int tunnel, uint64_t layer_types,\n \t\t\t\t     uint64_t hash_fields);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 62d9ca9ffb..25ab9adee6 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -3935,7 +3935,7 @@ flow_dv_validate_action_jump(struct rte_eth_dev *dev,\n \ttarget_group =\n \t\t((const struct rte_flow_action_jump *)action->conf)->group;\n \tret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,\n-\t\t\t\t       grp_info, error);\n+\t\t\t\t       &grp_info, error);\n \tif (ret)\n \t\treturn ret;\n \tif (attributes->group == target_group &&\n@@ -5103,7 +5103,7 @@ static int\n flow_dv_validate_attributes(struct rte_eth_dev *dev,\n \t\t\t    const struct mlx5_flow_tunnel *tunnel,\n \t\t\t    const struct rte_flow_attr *attributes,\n-\t\t\t    struct flow_grp_info grp_info,\n+\t\t\t    const struct flow_grp_info *grp_info,\n \t\t\t    struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -5258,7 +5258,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t}\n \tgrp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate\n \t\t\t\t(dev, tunnel, attr, items, actions);\n-\tret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);\n+\tret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);\n \tif (ret < 0)\n \t\treturn ret;\n \tis_root = (uint64_t)ret;\n@@ -9597,7 +9597,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \tgrp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate\n \t\t\t\t(dev, tunnel, attr, items, actions);\n \tret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,\n-\t\t\t\t       grp_info, error);\n+\t\t\t\t       &grp_info, error);\n \tif (ret)\n \t\treturn ret;\n \tdev_flow->dv.group = table;\n@@ -9944,7 +9944,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\tret = mlx5_flow_group_to_table(dev, tunnel,\n \t\t\t\t\t\t       jump_group,\n \t\t\t\t\t\t       &table,\n-\t\t\t\t\t\t       grp_info, error);\n+\t\t\t\t\t\t       &grp_info, error);\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \t\t\ttbl = flow_dv_tbl_resource_get(dev, table, attr->egress,\n",
    "prefixes": [
        "v3",
        "3/6"
    ]
}