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GET /api/patches/84047/?format=api
{ "id": 84047, "url": "https://patches.dpdk.org/api/patches/84047/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1605171103-312387-1-git-send-email-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1605171103-312387-1-git-send-email-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1605171103-312387-1-git-send-email-suanmingm@nvidia.com", "date": "2020-11-12T08:51:43", "name": "net/mlx5: fix counter offset support discover", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9161b6999494def0fccb98fc5fe912578709e68f", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1605171103-312387-1-git-send-email-suanmingm@nvidia.com/mbox/", "series": [ { "id": 13833, "url": "https://patches.dpdk.org/api/series/13833/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13833", "date": "2020-11-12T08:51:43", "name": "net/mlx5: fix counter offset support discover", "version": 1, "mbox": "https://patches.dpdk.org/series/13833/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/84047/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/84047/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4088BA09D3;\n\tThu, 12 Nov 2020 09:51:56 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 15D875953;\n\tThu, 12 Nov 2020 09:51:54 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 3B3C0593A\n for <dev@dpdk.org>; Thu, 12 Nov 2020 09:51:52 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 12 Nov 2020 10:51:49 +0200", "from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0AC8plLn004889;\n Thu, 12 Nov 2020 10:51:48 +0200" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "viacheslavo@nvidia.com, matan@nvidia.com", "Cc": "rasland@nvidia.com, dev@dpdk.org", "Date": "Thu, 12 Nov 2020 16:51:43 +0800", "Message-Id": "<1605171103-312387-1-git-send-email-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH] net/mlx5: fix counter offset support discover", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, the counter offset support is discovered by creating the\nrule with invalid offset counter and jump action in root table. If\nthe rule creation fails with EINVAL errno, that mean counter offset\nis not supported in root table.\n\nHowever, jump action may not be supported in some rdma-core version.\nIn this case, the discover code will not work properly.\n\nThis commits changes the jump action to generic drop action. That\nmakes the discover code to be more compatible.\n\nFixes: 994829e695c0 (\"net/mlx5: remove single counter container\")\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 22 +++++-----------------\n 1 file changed, 5 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 78c710f..bb2898f 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -12294,19 +12294,15 @@ struct mlx5_cache_entry *\n \t\t.match_mask = (void *)&mask,\n \t};\n \tvoid *actions[2] = { 0 };\n-\tstruct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;\n+\tstruct mlx5_flow_tbl_resource *tbl = NULL;\n \tstruct mlx5_devx_obj *dcs = NULL;\n \tvoid *matcher = NULL;\n \tvoid *flow = NULL;\n-\tint i, ret = -1;\n+\tint ret = -1;\n \n \ttbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);\n \tif (!tbl)\n \t\tgoto err;\n-\tdest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false,\n-\t\t\t\t\t NULL, 0, 0, NULL);\n-\tif (!dest_tbl)\n-\t\tgoto err;\n \tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);\n \tif (!dcs)\n \t\tgoto err;\n@@ -12314,10 +12310,7 @@ struct mlx5_cache_entry *\n \t\t\t\t\t\t &actions[0]);\n \tif (ret)\n \t\tgoto err;\n-\tret = mlx5_flow_os_create_flow_action_dest_flow_tbl\n-\t\t\t\t(dest_tbl->obj, &actions[1]);\n-\tif (ret)\n-\t\tgoto err;\n+\tactions[1] = priv->drop_queue.hrxq->action;\n \tdv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);\n \tret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,\n \t\t\t\t\t &matcher);\n@@ -12346,17 +12339,12 @@ struct mlx5_cache_entry *\n \t\t\t\t \"support detection\");\n \t\tret = 0;\n \t}\n-\tfor (i = 0; i < 2; i++) {\n-\t\tif (actions[i])\n-\t\t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n-\t\t\t\t (actions[i]));\n-\t}\n+\tif (actions[0])\n+\t\tclaim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));\n \tif (matcher)\n \t\tclaim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));\n \tif (tbl)\n \t\tflow_dv_tbl_resource_release(MLX5_SH(dev), tbl);\n-\tif (dest_tbl)\n-\t\tflow_dv_tbl_resource_release(MLX5_SH(dev), dest_tbl);\n \tif (dcs)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(dcs));\n \treturn ret;\n", "prefixes": [] }