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GET /api/patches/83508/?format=api
{ "id": 83508, "url": "https://patches.dpdk.org/api/patches/83508/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201103083717.10935-5-marchana@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201103083717.10935-5-marchana@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201103083717.10935-5-marchana@marvell.com", "date": "2020-11-03T08:37:17", "name": "[4/4] common/cpt: remove redundant structure", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "cb4e6b15af653faedec0f8157b0e00bd3d50df34", "submitter": { "id": 1515, "url": "https://patches.dpdk.org/api/people/1515/?format=api", "name": "Archana Muniganti", "email": "marchana@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201103083717.10935-5-marchana@marvell.com/mbox/", "series": [ { "id": 13607, "url": "https://patches.dpdk.org/api/series/13607/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13607", "date": "2020-11-03T08:37:13", "name": "code cleanup and improvements", "version": 1, "mbox": "https://patches.dpdk.org/series/13607/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/83508/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/83508/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 78BB6A0521;\n\tTue, 3 Nov 2020 09:38:41 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 61B4FC848;\n\tTue, 3 Nov 2020 09:37:40 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id E437FC846\n for <dev@dpdk.org>; Tue, 3 Nov 2020 09:37:38 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 0A38MKmo011648; Tue, 3 Nov 2020 00:37:37 -0800", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 34h59mvrg8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 03 Nov 2020 00:37:37 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 3 Nov 2020 00:37:35 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 3 Nov 2020 00:37:36 -0800", "from hyd1409.caveonetworks.com (unknown [10.29.45.15])\n by maili.marvell.com (Postfix) with ESMTP id 4FF9B3F7040;\n Tue, 3 Nov 2020 00:37:34 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=JiTu2EpicHOpnEMxll/OrX271BfZaazlCOnrZAKXNgw=;\n b=DUupPKT1qhGZ3L4vxN/5hPzpZEfAjtpZrsAJaOpKwNGhNadcLi+RFs1vGiuzBVAVVwxK\n uXU1Nzou0yxmNh1BRr1wpQt6ef9jCgMtvD5AN7/CWd4T5yuyEms3AFdgVy6U4yHA9d1S\n zgF4pBAfABs8Twn2Uc8wrldrsCwu1q0f8h+BvthH6LZjTVekfPaXZ23PdJonCS/daShZ\n beE1EMApgHtrMI+IzGm1CvA3n9rnUpP+FskpBBlbVKwQ1Y6KKW7wzQEKaL5fHTP4Rufv\n irwA4RhY1vBzXMRIjhCnTRal4P3RlwEPdqE1WBz11vkHnH/Bs0FYrnmy9VIQA6vRV6SO Bw==", "From": "Archana Muniganti <marchana@marvell.com>", "To": "<akhil.goyal@nxp.com>, <anoobj@marvell.com>, <adwivedi@marvell.com>", "CC": "Archana Muniganti <marchana@marvell.com>, <dev@dpdk.org>", "Date": "Tue, 3 Nov 2020 14:07:17 +0530", "Message-ID": "<20201103083717.10935-5-marchana@marvell.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20201103083717.10935-1-marchana@marvell.com>", "References": "<20201103083717.10935-1-marchana@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737\n definitions=2020-11-03_05:2020-11-02,\n 2020-11-03 signatures=0", "Subject": "[dpdk-dev] [PATCH 4/4] common/cpt: remove redundant structure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Replaced structure 'rid' which has single field with its\nfield itself.\n\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\n---\n drivers/common/cpt/cpt_common.h | 7 +------\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 10 +++++-----\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 13 +++++++------\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 13 ++++++-------\n 4 files changed, 19 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nindex f61495e458..7fea0ca879 100644\n--- a/drivers/common/cpt/cpt_common.h\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -27,11 +27,6 @@ struct cpt_qp_meta_info {\n \tint lb_mlen;\n };\n \n-struct rid {\n-\t/** Request id of a crypto operation */\n-\tuintptr_t rid;\n-};\n-\n /*\n * Pending queue structure\n *\n@@ -40,7 +35,7 @@ struct pending_queue {\n \t/** Pending requests count */\n \tuint64_t pending_count;\n \t/** Array of pending requests */\n-\tstruct rid *rid_queue;\n+\tuintptr_t *req_queue;\n \t/** Tail of queue to be used for enqueue */\n \tuint16_t enq_tail;\n \t/** Head of queue to be used for dequeue */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex ce546c2ffe..c6b1a5197d 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -535,7 +535,7 @@ otx_cpt_get_resource(const struct rte_cryptodev *dev, uint8_t group,\n \tlen = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);\n \n \t/* For pending queue */\n-\tlen += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\tlen += qlen * sizeof(uintptr_t);\n \n \t/* So that instruction queues start as pg size aligned */\n \tlen = RTE_ALIGN(len, pg_sz);\n@@ -570,14 +570,14 @@ otx_cpt_get_resource(const struct rte_cryptodev *dev, uint8_t group,\n \t}\n \n \t/* Pending queue setup */\n-\tcptvf->pqueue.rid_queue = (struct rid *)mem;\n+\tcptvf->pqueue.req_queue = (uintptr_t *)mem;\n \tcptvf->pqueue.enq_tail = 0;\n \tcptvf->pqueue.deq_head = 0;\n \tcptvf->pqueue.pending_count = 0;\n \n-\tmem += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n-\tlen -= qlen * RTE_ALIGN(sizeof(struct rid), 8);\n-\tdma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\tmem += qlen * sizeof(uintptr_t);\n+\tlen -= qlen * sizeof(uintptr_t);\n+\tdma_addr += qlen * sizeof(uintptr_t);\n \n \t/* Alignment wastage */\n \tused_len = alloc_len - len;\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex 0a0c50a363..9f731f8cc9 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -430,7 +430,7 @@ otx_cpt_request_enqueue(struct cpt_instance *instance,\n \t/* Default mode of software queue */\n \tmark_cpt_inst(instance);\n \n-\tpqueue->rid_queue[pqueue->enq_tail].rid = (uintptr_t)user_req;\n+\tpqueue->req_queue[pqueue->enq_tail] = (uintptr_t)user_req;\n \n \t/* We will use soft queue length here to limit requests */\n \tMOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);\n@@ -823,7 +823,6 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,\n \tstruct cpt_instance *instance = (struct cpt_instance *)qptr;\n \tstruct cpt_request_info *user_req;\n \tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n-\tstruct rid *rid_e;\n \tuint8_t cc[nb_ops];\n \tint i, count, pcount;\n \tuint8_t ret;\n@@ -837,11 +836,13 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,\n \tcount = (nb_ops > pcount) ? pcount : nb_ops;\n \n \tfor (i = 0; i < count; i++) {\n-\t\trid_e = &pqueue->rid_queue[pqueue->deq_head];\n-\t\tuser_req = (struct cpt_request_info *)(rid_e->rid);\n+\t\tuser_req = (struct cpt_request_info *)\n+\t\t\t\tpqueue->req_queue[pqueue->deq_head];\n \n-\t\tif (likely((i+1) < count))\n-\t\t\trte_prefetch_non_temporal((void *)rid_e[1].rid);\n+\t\tif (likely((i+1) < count)) {\n+\t\t\trte_prefetch_non_temporal(\n+\t\t\t\t(void *)pqueue->req_queue[i+1]);\n+\t\t}\n \n \t\tret = check_nb_command_id(user_req, instance);\n \ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex fe76fe38c2..c337398242 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -192,7 +192,7 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \tsize_div40 = (iq_len + 40 - 1) / 40 + 1;\n \n \t/* For pending queue */\n-\tlen = iq_len * RTE_ALIGN(sizeof(struct rid), 8);\n+\tlen = iq_len * sizeof(uintptr_t);\n \n \t/* Space for instruction group memory */\n \tlen += size_div40 * 16;\n@@ -229,12 +229,12 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \t}\n \n \t/* Initialize pending queue */\n-\tqp->pend_q.rid_queue = (struct rid *)va;\n+\tqp->pend_q.req_queue = (uintptr_t *)va;\n \tqp->pend_q.enq_tail = 0;\n \tqp->pend_q.deq_head = 0;\n \tqp->pend_q.pending_count = 0;\n \n-\tused_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);\n+\tused_len = iq_len * sizeof(uintptr_t);\n \tused_len += size_div40 * 16;\n \tused_len = RTE_ALIGN(used_len, pg_sz);\n \tiova += used_len;\n@@ -520,7 +520,7 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n \t} while (lmt_status == 0);\n \n-\tpend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;\n+\tpend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;\n \n \t/* We will use soft queue length here to limit requests */\n \tMOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);\n@@ -977,7 +977,6 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tstruct cpt_request_info *req;\n \tstruct rte_crypto_op *cop;\n \tuint8_t cc[nb_ops];\n-\tstruct rid *rid;\n \tuintptr_t *rsp;\n \tvoid *metabuf;\n \n@@ -989,8 +988,8 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \t\tnb_ops = nb_pending;\n \n \tfor (i = 0; i < nb_ops; i++) {\n-\t\trid = &pend_q->rid_queue[pend_q->deq_head];\n-\t\treq = (struct cpt_request_info *)(rid->rid);\n+\t\treq = (struct cpt_request_info *)\n+\t\t\t\tpend_q->req_queue[pend_q->deq_head];\n \n \t\tcc[i] = otx2_cpt_compcode_get(req);\n \n", "prefixes": [ "4/4" ] }