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GET /api/patches/83418/?format=api
{ "id": 83418, "url": "https://patches.dpdk.org/api/patches/83418/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1604327899-60126-7-git-send-email-oulijun@huawei.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1604327899-60126-7-git-send-email-oulijun@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1604327899-60126-7-git-send-email-oulijun@huawei.com", "date": "2020-11-02T14:38:17", "name": "[6/8] net/hns3: fix visit unsupported QL register error", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "be0bef51f64d7e7eae16b009a5671804e4abf2c3", "submitter": { "id": 1675, "url": "https://patches.dpdk.org/api/people/1675/?format=api", "name": "Lijun Ou", "email": "oulijun@huawei.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1604327899-60126-7-git-send-email-oulijun@huawei.com/mbox/", "series": [ { "id": 13574, "url": "https://patches.dpdk.org/api/series/13574/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13574", "date": "2020-11-02T14:38:11", "name": "misc fixes for hns3", "version": 1, "mbox": "https://patches.dpdk.org/series/13574/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/83418/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/83418/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22982A04E7;\n\tMon, 2 Nov 2020 15:40:02 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 421C7C958;\n\tMon, 2 Nov 2020 15:38:07 +0100 (CET)", "from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191])\n by dpdk.org (Postfix) with ESMTP id E8E34C91A\n for <dev@dpdk.org>; Mon, 2 Nov 2020 15:37:59 +0100 (CET)", "from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58])\n by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CPwW66bLfzLsmd\n for <dev@dpdk.org>; Mon, 2 Nov 2020 22:37:54 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id\n 14.3.487.0; Mon, 2 Nov 2020 22:37:47 +0800" ], "From": "Lijun Ou <oulijun@huawei.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <linuxarm@huawei.com>", "Date": "Mon, 2 Nov 2020 22:38:17 +0800", "Message-ID": "<1604327899-60126-7-git-send-email-oulijun@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1604327899-60126-1-git-send-email-oulijun@huawei.com>", "References": "<1604327899-60126-1-git-send-email-oulijun@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 6/8] net/hns3: fix visit unsupported QL register\n\terror", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Hongbo Zheng <zhenghongbo3@huawei.com>\n\nIf hardware does not support QL(quantity limiter), the int_ql_max\nis 0, software should confirm ql_value is less than int_ql_max\nbefore write QL register. This patch add check of int_ql_max\nvalue from firmware and delete the unused variable coalesce_mode.\n\nFixes: 27911a6e62e5 (\"net/hns3: add Rx interrupts compatibility\")\nCc: stable@dpdk.org\n\nSigned-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.c | 8 ++++++--\n drivers/net/hns3/hns3_ethdev.h | 22 ++++------------------\n drivers/net/hns3/hns3_ethdev_vf.c | 8 ++++++--\n drivers/net/hns3/hns3_rxtx.c | 7 ++++++-\n 4 files changed, 22 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 1e382f1..180b313 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -2291,6 +2291,10 @@ hns3_init_ring_with_vector(struct hns3_hw *hw)\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);\n+\t\t/*\n+\t\t * QL(quantity limiter) is not used currently, just set 0 to\n+\t\t * close it.\n+\t\t */\n \t\thns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);\n \n \t\tret = hns3_bind_ring_with_vector(hw, vec, false,\n@@ -2952,6 +2956,7 @@ hns3_set_default_dev_specifications(struct hns3_hw *hw)\n \thw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;\n \thw->rss_key_size = HNS3_RSS_KEY_SIZE;\n \thw->max_tm_rate = HNS3_ETHER_MAX_RATE;\n+\thw->intr.int_ql_max = HNS3_INTR_QL_NONE;\n }\n \n static void\n@@ -2965,6 +2970,7 @@ hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)\n \thw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);\n \thw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);\n \thw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);\n+\thw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);\n }\n \n static int\n@@ -3031,7 +3037,6 @@ hns3_get_capability(struct hns3_hw *hw)\n \tif (revision < PCI_REVISION_ID_HIP09_A) {\n \t\thns3_set_default_dev_specifications(hw);\n \t\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;\n-\t\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;\n \t\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;\n \t\thw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;\n \t\thw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;\n@@ -3050,7 +3055,6 @@ hns3_get_capability(struct hns3_hw *hw)\n \t}\n \n \thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;\n-\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;\n \thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;\n \thw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;\n \thw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex a2b61ff..531a6cb 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -379,12 +379,11 @@ struct hns3_reset_data {\n #define HNS3_INTR_MAPPING_VEC_RSV_ONE\t\t0\n #define HNS3_INTR_MAPPING_VEC_ALL\t\t1\n \n-#define HNS3_INTR_COALESCE_NON_QL\t\t0\n-#define HNS3_INTR_COALESCE_QL\t\t\t1\n-\n #define HNS3_INTR_COALESCE_GL_UINT_2US\t\t0\n #define HNS3_INTR_COALESCE_GL_UINT_1US\t\t1\n \n+#define HNS3_INTR_QL_NONE\t\t\t0\n+\n struct hns3_queue_intr {\n \t/*\n \t * interrupt mapping mode.\n@@ -406,27 +405,14 @@ struct hns3_queue_intr {\n \t */\n \tuint8_t mapping_mode;\n \t/*\n-\t * interrupt coalesce mode.\n-\t * value range:\n-\t * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL\n-\t *\n-\t * - HNS3_INTR_COALESCE_NON_QL\n-\t * For some versions of hardware network engine, hardware doesn't\n-\t * support QL(quanity limiter) algorithm for interrupt coalesce\n-\t * of queue's interrupt.\n-\t *\n-\t * - HNS3_INTR_COALESCE_QL\n-\t * In this mode, hardware support QL(quanity limiter) algorithm for\n-\t * interrupt coalesce of queue's interrupt.\n-\t */\n-\tuint8_t coalesce_mode;\n-\t/*\n \t * The unit of GL(gap limiter) configuration for interrupt coalesce of\n \t * queue's interrupt.\n \t * value range:\n \t * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US\n \t */\n \tuint8_t gl_unit;\n+\t/* The max QL(quantity limiter) value */\n+\tuint16_t int_ql_max;\n };\n \n #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM\t\t0\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex c903e07..088a46f 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -757,6 +757,10 @@ hns3vf_init_ring_with_vector(struct hns3_hw *hw)\n \t\thns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,\n \t\t\t\t HNS3_TQP_INTR_GL_DEFAULT);\n \t\thns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);\n+\t\t/*\n+\t\t * QL(quantity limiter) is not used currently, just set 0 to\n+\t\t * close it.\n+\t\t */\n \t\thns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);\n \n \t\tret = hns3vf_bind_ring_with_vector(hw, vec, false,\n@@ -1149,6 +1153,7 @@ hns3vf_set_default_dev_specifications(struct hns3_hw *hw)\n \thw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;\n \thw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;\n \thw->rss_key_size = HNS3_RSS_KEY_SIZE;\n+\thw->intr.int_ql_max = HNS3_INTR_QL_NONE;\n }\n \n static void\n@@ -1161,6 +1166,7 @@ hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)\n \thw->max_non_tso_bd_num = req0->max_non_tso_bd_num;\n \thw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);\n \thw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);\n+\thw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);\n }\n \n static int\n@@ -1210,7 +1216,6 @@ hns3vf_get_capability(struct hns3_hw *hw)\n \tif (revision < PCI_REVISION_ID_HIP09_A) {\n \t\thns3vf_set_default_dev_specifications(hw);\n \t\thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;\n-\t\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;\n \t\thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;\n \t\thw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;\n \t\thw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;\n@@ -1228,7 +1233,6 @@ hns3vf_get_capability(struct hns3_hw *hw)\n \t}\n \n \thw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;\n-\thw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;\n \thw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;\n \thw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;\n \thw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex c82116d..afb1e7d 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -851,7 +851,12 @@ hns3_set_queue_intr_ql(struct hns3_hw *hw, uint16_t queue_id, uint16_t ql_value)\n {\n \tuint32_t addr;\n \n-\tif (hw->intr.coalesce_mode == HNS3_INTR_COALESCE_NON_QL)\n+\t/*\n+\t * int_ql_max == 0 means the hardware does not support QL,\n+\t * QL regs config is not permitted if QL is not supported,\n+\t * here just return.\n+\t */\n+\tif (hw->intr.int_ql_max == HNS3_INTR_QL_NONE)\n \t\treturn;\n \n \taddr = HNS3_TQP_INTR_TX_QL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;\n", "prefixes": [ "6/8" ] }