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GET /api/patches/82881/?format=api
{ "id": 82881, "url": "https://patches.dpdk.org/api/patches/82881/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1604050872-24997-9-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1604050872-24997-9-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1604050872-24997-9-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-10-30T09:40:56", "name": "[v8,08/23] event/dlb: add probe-time hardware init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8195773cb76c64acc124291665441488ad987234", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1604050872-24997-9-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 13495, "url": "https://patches.dpdk.org/api/series/13495/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13495", "date": "2020-10-30T09:40:48", "name": "Add DLB PMD", "version": 8, "mbox": "https://patches.dpdk.org/series/13495/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82881/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/82881/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 03F50A04DF;\n\tFri, 30 Oct 2020 10:42:20 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F2345BE87;\n\tFri, 30 Oct 2020 10:39:56 +0100 (CET)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id 1459FBBA4\n for <dev@dpdk.org>; Fri, 30 Oct 2020 10:39:33 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Oct 2020 02:39:32 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 30 Oct 2020 02:39:32 -0700" ], "IronPort-SDR": [ "\n QXM8CEvbNS7/5XsqJrlBVTkgYQUIbBEjrh2etn9/yrusV0MOs6EThT/7fVCgnCywHcCcTNGmss\n f6EW6d4jGL+Q==", "\n ioGmoUYV8q/J6OgJrhjME7wRaSNy1eY+/j7I7TGccQ8t1moRKvRNuHzgXJOvwFHNTmKZyijVZd\n WZChE+0Wv/zw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9789\"; a=\"230219303\"", "E=Sophos;i=\"5.77,432,1596524400\"; d=\"scan'208\";a=\"230219303\"", "E=Sophos;i=\"5.77,432,1596524400\"; d=\"scan'208\";a=\"527062078\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Fri, 30 Oct 2020 04:40:56 -0500", "Message-Id": "<1604050872-24997-9-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1604050872-24997-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20200612212434.6852-2-timothy.mcdaniel@intel.com>\n <1604050872-24997-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v8 08/23] event/dlb: add probe-time hardware init", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds probe-time low level hardware\ninitialization. It also adds probe-time init for both\nprimary and secondary DPDK processes.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb/dlb.c | 158 +++++++++++++++-\n drivers/event/dlb/meson.build | 3 +-\n drivers/event/dlb/pf/base/dlb_resource.c | 302 +++++++++++++++++++++++++++++++\n drivers/event/dlb/pf/dlb_main.c | 20 +-\n drivers/event/dlb/pf/dlb_pf.c | 86 ++++++++-\n 5 files changed, 561 insertions(+), 8 deletions(-)\n create mode 100644 drivers/event/dlb/pf/base/dlb_resource.c", "diff": "diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nindex 8008a50..57b2837 100644\n--- a/drivers/event/dlb/dlb.c\n+++ b/drivers/event/dlb/dlb.c\n@@ -42,10 +42,92 @@\n #if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)\n #error \"RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member max_event_queues\"\n #endif\n+static struct rte_event_dev_info evdev_dlb_default_info = {\n+\t.driver_name = \"\", /* probe will set */\n+\t.min_dequeue_timeout_ns = DLB_MIN_DEQUEUE_TIMEOUT_NS,\n+\t.max_dequeue_timeout_ns = DLB_MAX_DEQUEUE_TIMEOUT_NS,\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB_MAX_NUM_LDB_QUEUES)\n+\t.max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,\n+#else\n+\t.max_event_queues = DLB_MAX_NUM_LDB_QUEUES,\n+#endif\n+\t.max_event_queue_flows = DLB_MAX_NUM_FLOWS,\n+\t.max_event_queue_priority_levels = DLB_QID_PRIORITIES,\n+\t.max_event_priority_levels = DLB_QID_PRIORITIES,\n+\t.max_event_ports = DLB_MAX_NUM_LDB_PORTS,\n+\t.max_event_port_dequeue_depth = DLB_MAX_CQ_DEPTH,\n+\t.max_event_port_enqueue_depth = DLB_MAX_ENQUEUE_DEPTH,\n+\t.max_event_port_links = DLB_MAX_NUM_QIDS_PER_LDB_CQ,\n+\t.max_num_events = DLB_MAX_NUM_LDB_CREDITS,\n+\t.max_single_link_event_port_queue_pairs = DLB_MAX_NUM_DIR_PORTS,\n+\t.event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |\n+\t\t\t RTE_EVENT_DEV_CAP_EVENT_QOS |\n+\t\t\t RTE_EVENT_DEV_CAP_BURST_MODE |\n+\t\t\t RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |\n+\t\t\t RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |\n+\t\t\t RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),\n+};\n \n struct process_local_port_data\n dlb_port[DLB_MAX_NUM_PORTS][NUM_DLB_PORT_TYPES];\n \n+static int\n+dlb_hw_query_resources(struct dlb_eventdev *dlb)\n+{\n+\tstruct dlb_hw_dev *handle = &dlb->qm_instance;\n+\tstruct dlb_hw_resource_info *dlb_info = &handle->info;\n+\tint ret;\n+\n+\tret = dlb_iface_get_num_resources(handle,\n+\t\t\t\t\t &dlb->hw_rsrc_query_results);\n+\tif (ret) {\n+\t\tDLB_LOG_ERR(\"get dlb num resources, err=%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Complete filling in device resource info returned to evdev app,\n+\t * overriding any default values.\n+\t * The capabilities (CAPs) were set at compile time.\n+\t */\n+\n+\tevdev_dlb_default_info.max_event_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues;\n+\n+\tevdev_dlb_default_info.max_event_ports =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_ports;\n+\n+\tevdev_dlb_default_info.max_num_events =\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_ldb_credits;\n+\n+\t/* Save off values used when creating the scheduling domain. */\n+\n+\thandle->info.num_sched_domains =\n+\t\tdlb->hw_rsrc_query_results.num_sched_domains;\n+\n+\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\tdlb->hw_rsrc_query_results.max_contiguous_ldb_credits;\n+\n+\thandle->info.hw_rsrc_max.num_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues +\n+\t\tdlb->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_queues =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_queues;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_ports =\n+\t\tdlb->hw_rsrc_query_results.num_ldb_ports;\n+\n+\thandle->info.hw_rsrc_max.num_dir_ports =\n+\t\tdlb->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.reorder_window_size =\n+\t\tdlb->hw_rsrc_query_results.num_hist_list_entries;\n+\n+\trte_memcpy(dlb_info, &handle->info.hw_rsrc_max, sizeof(*dlb_info));\n+\n+\treturn 0;\n+}\n+\n /* Wrapper for string to int conversion. Substituted for atoi(...), which is\n * unsafe.\n */\n@@ -227,9 +309,54 @@ dlb_primary_eventdev_probe(struct rte_eventdev *dev,\n \t\t\t const char *name,\n \t\t\t struct dlb_devargs *dlb_args)\n {\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(name);\n-\tRTE_SET_USED(dlb_args);\n+\tstruct dlb_eventdev *dlb;\n+\tint err;\n+\n+\tdlb = dev->data->dev_private;\n+\n+\tdlb->event_dev = dev; /* backlink */\n+\n+\tevdev_dlb_default_info.driver_name = name;\n+\n+\tdlb->max_num_events_override = dlb_args->max_num_events;\n+\tdlb->num_dir_credits_override = dlb_args->num_dir_credits_override;\n+\tdlb->defer_sched = dlb_args->defer_sched;\n+\tdlb->num_atm_inflights_per_queue = dlb_args->num_atm_inflights;\n+\n+\t/* Open the interface.\n+\t * For vdev mode, this means open the dlb kernel module.\n+\t */\n+\terr = dlb_iface_open(&dlb->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_iface_get_device_version(&dlb->qm_instance, &dlb->revision);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"dlb: failed to get the device version, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_hw_query_resources(dlb);\n+\tif (err) {\n+\t\tDLB_LOG_ERR(\"get resources err=%d for %s\\n\", err, name);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_iface_get_cq_poll_mode(&dlb->qm_instance, &dlb->poll_mode);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"dlb: failed to get the poll mode, err=%d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\trte_spinlock_init(&dlb->qm_instance.resource_lock);\n+\n+\tdlb_iface_low_level_io_init(dlb);\n+\n+\tdlb_entry_points_init(dev);\n \n \treturn 0;\n }\n@@ -238,8 +365,29 @@ int\n dlb_secondary_eventdev_probe(struct rte_eventdev *dev,\n \t\t\t const char *name)\n {\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(name);\n+\tstruct dlb_eventdev *dlb;\n+\tint err;\n+\n+\tdlb = dev->data->dev_private;\n+\n+\tevdev_dlb_default_info.driver_name = name;\n+\n+\terr = dlb_iface_open(&dlb->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb_hw_query_resources(dlb);\n+\tif (err) {\n+\t\tDLB_LOG_ERR(\"get resources err=%d for %s\\n\", err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb_iface_low_level_io_init(dlb);\n+\n+\tdlb_entry_points_init(dev);\n \n \treturn 0;\n }\ndiff --git a/drivers/event/dlb/meson.build b/drivers/event/dlb/meson.build\nindex 8707d3d..9777178 100644\n--- a/drivers/event/dlb/meson.build\n+++ b/drivers/event/dlb/meson.build\n@@ -10,7 +10,8 @@ endif\n sources = files('dlb.c',\n \t\t'dlb_iface.c',\n \t\t'pf/dlb_main.c',\n-\t\t'pf/dlb_pf.c'\n+\t\t'pf/dlb_pf.c',\n+\t\t'pf/base/dlb_resource.c'\n )\n \n deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']\ndiff --git a/drivers/event/dlb/pf/base/dlb_resource.c b/drivers/event/dlb/pf/base/dlb_resource.c\nnew file mode 100644\nindex 0000000..9c4267b\n--- /dev/null\n+++ b/drivers/event/dlb/pf/base/dlb_resource.c\n@@ -0,0 +1,302 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include \"dlb_hw_types.h\"\n+#include \"../../dlb_user.h\"\n+#include \"dlb_resource.h\"\n+#include \"dlb_osdep.h\"\n+#include \"dlb_osdep_bitmap.h\"\n+#include \"dlb_osdep_types.h\"\n+#include \"dlb_regs.h\"\n+\n+void dlb_disable_dp_vasr_feature(struct dlb_hw *hw)\n+{\n+\tunion dlb_dp_dir_csr_ctrl r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_DP_DIR_CSR_CTRL);\n+\n+\tr0.field.cfg_vasr_dis = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_DP_DIR_CSR_CTRL, r0.val);\n+}\n+\n+void dlb_enable_excess_tokens_alarm(struct dlb_hw *hw)\n+{\n+\tunion dlb_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.val |= 1 << DLB_CHP_CFG_EXCESS_TOKENS_SHIFT;\n+\n+\tDLB_CSR_WR(hw, DLB_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+void dlb_hw_enable_sparse_ldb_cq_mode(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_cq_mode r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_CQ_MODE);\n+\n+\tr0.field.ldb_cq64 = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_CQ_MODE, r0.val);\n+}\n+\n+void dlb_hw_enable_sparse_dir_cq_mode(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_cq_mode r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_CQ_MODE);\n+\n+\tr0.field.dir_cq64 = 1;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_CQ_MODE, r0.val);\n+}\n+\n+void dlb_hw_disable_pf_to_vf_isr_pend_err(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_sys_alarm_int_enable r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_SYS_ALARM_INT_ENABLE);\n+\n+\tr0.field.pf_to_vf_isr_pend_error = 0;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_SYS_ALARM_INT_ENABLE, r0.val);\n+}\n+\n+void dlb_hw_get_num_resources(struct dlb_hw *hw,\n+\t\t\t struct dlb_get_num_resources_args *arg)\n+{\n+\tstruct dlb_function_resources *rsrcs;\n+\tstruct dlb_bitmap *map;\n+\n+\trsrcs = &hw->pf;\n+\n+\targ->num_sched_domains = rsrcs->num_avail_domains;\n+\n+\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n+\n+\targ->num_ldb_ports = rsrcs->num_avail_ldb_ports;\n+\n+\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n+\n+\tmap = rsrcs->avail_aqed_freelist_entries;\n+\n+\targ->num_atomic_inflights = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_atomic_inflights =\n+\t\tdlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_hist_list_entries;\n+\n+\targ->num_hist_list_entries = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_hist_list_entries =\n+\t\tdlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_qed_freelist_entries;\n+\n+\targ->num_ldb_credits = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_ldb_credits = dlb_bitmap_longest_set_range(map);\n+\n+\tmap = rsrcs->avail_dqed_freelist_entries;\n+\n+\targ->num_dir_credits = dlb_bitmap_count(map);\n+\n+\targ->max_contiguous_dir_credits = dlb_bitmap_longest_set_range(map);\n+\n+\targ->num_ldb_credit_pools = rsrcs->num_avail_ldb_credit_pools;\n+\n+\targ->num_dir_credit_pools = rsrcs->num_avail_dir_credit_pools;\n+}\n+\n+static void dlb_init_fn_rsrc_lists(struct dlb_function_resources *rsrc)\n+{\n+\tdlb_list_init_head(&rsrc->avail_domains);\n+\tdlb_list_init_head(&rsrc->used_domains);\n+\tdlb_list_init_head(&rsrc->avail_ldb_queues);\n+\tdlb_list_init_head(&rsrc->avail_ldb_ports);\n+\tdlb_list_init_head(&rsrc->avail_dir_pq_pairs);\n+\tdlb_list_init_head(&rsrc->avail_ldb_credit_pools);\n+\tdlb_list_init_head(&rsrc->avail_dir_credit_pools);\n+}\n+\n+static void dlb_init_domain_rsrc_lists(struct dlb_domain *domain)\n+{\n+\tdlb_list_init_head(&domain->used_ldb_queues);\n+\tdlb_list_init_head(&domain->used_ldb_ports);\n+\tdlb_list_init_head(&domain->used_dir_pq_pairs);\n+\tdlb_list_init_head(&domain->used_ldb_credit_pools);\n+\tdlb_list_init_head(&domain->used_dir_credit_pools);\n+\tdlb_list_init_head(&domain->avail_ldb_queues);\n+\tdlb_list_init_head(&domain->avail_ldb_ports);\n+\tdlb_list_init_head(&domain->avail_dir_pq_pairs);\n+\tdlb_list_init_head(&domain->avail_ldb_credit_pools);\n+\tdlb_list_init_head(&domain->avail_dir_credit_pools);\n+}\n+\n+int dlb_resource_init(struct dlb_hw *hw)\n+{\n+\tstruct dlb_list_entry *list;\n+\tunsigned int i;\n+\n+\t/* For optimal load-balancing, ports that map to one or more QIDs in\n+\t * common should not be in numerical sequence. This is application\n+\t * dependent, but the driver interleaves port IDs as much as possible\n+\t * to reduce the likelihood of this. This initial allocation maximizes\n+\t * the average distance between an ID and its immediate neighbors (i.e.\n+\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n+\t * 3, etc.).\n+\t */\n+\tu32 init_ldb_port_allocation[DLB_MAX_NUM_LDB_PORTS] = {\n+\t\t0, 31, 62, 29, 60, 27, 58, 25, 56, 23, 54, 21, 52, 19, 50, 17,\n+\t\t48, 15, 46, 13, 44, 11, 42, 9, 40, 7, 38, 5, 36, 3, 34, 1,\n+\t\t32, 63, 30, 61, 28, 59, 26, 57, 24, 55, 22, 53, 20, 51, 18, 49,\n+\t\t16, 47, 14, 45, 12, 43, 10, 41, 8, 39, 6, 37, 4, 35, 2, 33\n+\t};\n+\n+\t/* Zero-out resource tracking data structures */\n+\tmemset(&hw->rsrcs, 0, sizeof(hw->rsrcs));\n+\tmemset(&hw->pf, 0, sizeof(hw->pf));\n+\n+\tdlb_init_fn_rsrc_lists(&hw->pf);\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DOMAINS; i++) {\n+\t\tmemset(&hw->domains[i], 0, sizeof(hw->domains[i]));\n+\t\tdlb_init_domain_rsrc_lists(&hw->domains[i]);\n+\t\thw->domains[i].parent_func = &hw->pf;\n+\t}\n+\n+\t/* Give all resources to the PF driver */\n+\thw->pf.num_avail_domains = DLB_MAX_NUM_DOMAINS;\n+\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n+\t\tlist = &hw->domains[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_domains, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_queues = DLB_MAX_NUM_LDB_QUEUES;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n+\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_queues, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_ports = DLB_MAX_NUM_LDB_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_ports; i++) {\n+\t\tstruct dlb_ldb_port *port;\n+\n+\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_ports, &port->func_list);\n+\t}\n+\n+\thw->pf.num_avail_dir_pq_pairs = DLB_MAX_NUM_DIR_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n+\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_dir_pq_pairs, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_credit_pools = DLB_MAX_NUM_LDB_CREDIT_POOLS;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_credit_pools; i++) {\n+\t\tlist = &hw->rsrcs.ldb_credit_pools[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_ldb_credit_pools, list);\n+\t}\n+\n+\thw->pf.num_avail_dir_credit_pools = DLB_MAX_NUM_DIR_CREDIT_POOLS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_credit_pools; i++) {\n+\t\tlist = &hw->rsrcs.dir_credit_pools[i].func_list;\n+\n+\t\tdlb_list_add(&hw->pf.avail_dir_credit_pools, list);\n+\t}\n+\n+\t/* There are 5120 history list entries, which allows us to overprovision\n+\t * the inflight limit (4096) by 1k.\n+\t */\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t &hw->pf.avail_hist_list_entries,\n+\t\t\t DLB_MAX_NUM_HIST_LIST_ENTRIES))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_hist_list_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t &hw->pf.avail_qed_freelist_entries,\n+\t\t\t DLB_MAX_NUM_LDB_CREDITS))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_qed_freelist_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t &hw->pf.avail_dqed_freelist_entries,\n+\t\t\t DLB_MAX_NUM_DIR_CREDITS))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_dqed_freelist_entries))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_alloc(hw,\n+\t\t\t &hw->pf.avail_aqed_freelist_entries,\n+\t\t\t DLB_MAX_NUM_AQOS_ENTRIES))\n+\t\treturn -1;\n+\n+\tif (dlb_bitmap_fill(hw->pf.avail_aqed_freelist_entries))\n+\t\treturn -1;\n+\n+\t/* Initialize the hardware resource IDs */\n+\tfor (i = 0; i < DLB_MAX_NUM_DOMAINS; i++)\n+\t\thw->domains[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_QUEUES; i++)\n+\t\thw->rsrcs.ldb_queues[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_PORTS; i++)\n+\t\thw->rsrcs.ldb_ports[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DIR_PORTS; i++)\n+\t\thw->rsrcs.dir_pq_pairs[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_LDB_CREDIT_POOLS; i++)\n+\t\thw->rsrcs.ldb_credit_pools[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_DIR_CREDIT_POOLS; i++)\n+\t\thw->rsrcs.dir_credit_pools[i].id = i;\n+\n+\tfor (i = 0; i < DLB_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\thw->rsrcs.sn_groups[i].id = i;\n+\t\t/* Default mode (0) is 32 sequence numbers per queue */\n+\t\thw->rsrcs.sn_groups[i].mode = 0;\n+\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 32;\n+\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void dlb_resource_free(struct dlb_hw *hw)\n+{\n+\tdlb_bitmap_free(hw->pf.avail_hist_list_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_qed_freelist_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_dqed_freelist_entries);\n+\n+\tdlb_bitmap_free(hw->pf.avail_aqed_freelist_entries);\n+}\n+\n+void dlb_hw_disable_vf_to_pf_isr_pend_err(struct dlb_hw *hw)\n+{\n+\tunion dlb_sys_sys_alarm_int_enable r0;\n+\n+\tr0.val = DLB_CSR_RD(hw, DLB_SYS_SYS_ALARM_INT_ENABLE);\n+\n+\tr0.field.vf_to_pf_isr_pend_error = 0;\n+\n+\tDLB_CSR_WR(hw, DLB_SYS_SYS_ALARM_INT_ENABLE, r0.val);\n+}\ndiff --git a/drivers/event/dlb/pf/dlb_main.c b/drivers/event/dlb/pf/dlb_main.c\nindex c10c36c..2f4a828 100644\n--- a/drivers/event/dlb/pf/dlb_main.c\n+++ b/drivers/event/dlb/pf/dlb_main.c\n@@ -223,12 +223,18 @@ dlb_probe(struct rte_pci_device *pdev)\n \tif (ret)\n \t\tgoto init_driver_state_fail;\n \n+\tret = dlb_resource_init(&dlb_dev->hw);\n+\tif (ret)\n+\t\tgoto resource_init_fail;\n+\n \tdlb_dev->revision = os_get_dev_revision(&dlb_dev->hw);\n \n \tdlb_pf_init_hardware(dlb_dev);\n \n \treturn dlb_dev;\n \n+resource_init_fail:\n+\tdlb_resource_free(&dlb_dev->hw);\n init_driver_state_fail:\n mask_ur_err_fail:\n dlb_reset_fail:\n@@ -564,5 +570,17 @@ dlb_pf_init_driver_state(struct dlb_dev *dlb_dev)\n void\n dlb_pf_init_hardware(struct dlb_dev *dlb_dev)\n {\n-\tRTE_SET_USED(dlb_dev);\n+\tdlb_disable_dp_vasr_feature(&dlb_dev->hw);\n+\n+\tdlb_enable_excess_tokens_alarm(&dlb_dev->hw);\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0) {\n+\t\tdlb_hw_enable_sparse_ldb_cq_mode(&dlb_dev->hw);\n+\t\tdlb_hw_enable_sparse_dir_cq_mode(&dlb_dev->hw);\n+\t}\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0) {\n+\t\tdlb_hw_disable_pf_to_vf_isr_pend_err(&dlb_dev->hw);\n+\t\tdlb_hw_disable_vf_to_pf_isr_pend_err(&dlb_dev->hw);\n+\t}\n }\ndiff --git a/drivers/event/dlb/pf/dlb_pf.c b/drivers/event/dlb/pf/dlb_pf.c\nindex 05fd76c..7fc85e9 100644\n--- a/drivers/event/dlb/pf/dlb_pf.c\n+++ b/drivers/event/dlb/pf/dlb_pf.c\n@@ -35,9 +35,93 @@\n #include \"base/dlb_resource.h\"\n \n static void\n-dlb_pf_iface_fn_ptrs_init(void)\n+dlb_pf_low_level_io_init(struct dlb_eventdev *dlb __rte_unused)\n {\n+\tint i;\n+\n+\t/* Addresses will be initialized at port create */\n+\tfor (i = 0; i < DLB_MAX_NUM_PORTS; i++) {\n+\t\t/* First directed ports */\n+\n+\t\t/* producer port */\n+\t\tdlb_port[i][DLB_DIR].pp_addr = NULL;\n+\n+\t\t/* popcount */\n+\t\tdlb_port[i][DLB_DIR].ldb_popcount = NULL;\n+\t\tdlb_port[i][DLB_DIR].dir_popcount = NULL;\n+\n+\t\t/* consumer queue */\n+\t\tdlb_port[i][DLB_DIR].cq_base = NULL;\n+\t\tdlb_port[i][DLB_DIR].mmaped = true;\n+\n+\t\t/* Now load balanced ports */\n+\n+\t\t/* producer port */\n+\t\tdlb_port[i][DLB_LDB].pp_addr = NULL;\n+\n+\t\t/* popcount */\n+\t\tdlb_port[i][DLB_LDB].ldb_popcount = NULL;\n+\t\tdlb_port[i][DLB_LDB].dir_popcount = NULL;\n+\n+\t\t/* consumer queue */\n+\t\tdlb_port[i][DLB_LDB].cq_base = NULL;\n+\t\tdlb_port[i][DLB_LDB].mmaped = true;\n+\t}\n+}\n+\n+static int\n+dlb_pf_open(struct dlb_hw_dev *handle, const char *name)\n+{\n+\tRTE_SET_USED(handle);\n+\tRTE_SET_USED(name);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_device_version(struct dlb_hw_dev *handle,\n+\t\t\t uint8_t *revision)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\t*revision = dlb_dev->revision;\n \n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_num_resources(struct dlb_hw_dev *handle,\n+\t\t\t struct dlb_get_num_resources_args *rsrcs)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\tdlb_hw_get_num_resources(&dlb_dev->hw, rsrcs);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb_pf_get_cq_poll_mode(struct dlb_hw_dev *handle,\n+\t\t\tenum dlb_cq_poll_modes *mode)\n+{\n+\tstruct dlb_dev *dlb_dev = (struct dlb_dev *)handle->pf_dev;\n+\n+\tif (dlb_dev->revision >= DLB_REV_B0)\n+\t\t*mode = DLB_CQ_POLL_MODE_SPARSE;\n+\telse\n+\t\t*mode = DLB_CQ_POLL_MODE_STD;\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb_pf_iface_fn_ptrs_init(void)\n+{\n+\tdlb_iface_low_level_io_init = dlb_pf_low_level_io_init;\n+\tdlb_iface_open = dlb_pf_open;\n+\tdlb_iface_get_device_version = dlb_pf_get_device_version;\n+\tdlb_iface_get_num_resources = dlb_pf_get_num_resources;\n+\tdlb_iface_get_cq_poll_mode = dlb_pf_get_cq_poll_mode;\n }\n \n /* PCI DEV HOOKS */\n", "prefixes": [ "v8", "08/23" ] }