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GET /api/patches/82844/?format=api
{ "id": 82844, "url": "https://patches.dpdk.org/api/patches/82844/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1604008681-414157-6-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1604008681-414157-6-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1604008681-414157-6-git-send-email-matan@nvidia.com", "date": "2020-10-29T21:57:58", "name": "[5/8] common/mlx5: add definitions for ASO flow hit", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d11686e74828291a10fe9d9334b16f0f1d13cd45", "submitter": { "id": 1911, "url": "https://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1604008681-414157-6-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 13477, "url": "https://patches.dpdk.org/api/series/13477/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13477", "date": "2020-10-29T21:57:53", "name": "net/mlx5: support flow hit steering action", "version": 1, "mbox": "https://patches.dpdk.org/series/13477/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82844/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82844/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D0D70A04B5;\n\tThu, 29 Oct 2020 22:59:36 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3D29FCB1A;\n\tThu, 29 Oct 2020 22:58:19 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 8B2FDCAB6\n for <dev@dpdk.org>; Thu, 29 Oct 2020 22:58:11 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 29 Oct 2020 23:58:05 +0200", "from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09TLw4Ts022832;\n Thu, 29 Oct 2020 23:58:04 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@nvidia.com>", "Date": "Thu, 29 Oct 2020 21:57:58 +0000", "Message-Id": "<1604008681-414157-6-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1604008681-414157-1-git-send-email-matan@nvidia.com>", "References": "<1604008681-414157-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 5/8] common/mlx5: add definitions for ASO flow hit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nThis patch adds different PRM definitions, related to ASO flow hit\nfeature, in MLX5 PMD code.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 ++\n drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++-\n 2 files changed, 67 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 7c552a3..a738cd2 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -126,6 +126,8 @@ has_sym_args = [\n \t'MLX5_OPCODE_SEND_EN' ],\n \t[ 'HAVE_MLX5_OPCODE_WAIT', 'infiniband/mlx5dv.h',\n \t'MLX5_OPCODE_WAIT' ],\n+ [ 'HAVE_MLX5_OPCODE_ACCESS_ASO', 'infiniband/mlx5dv.h',\n+ 'MLX5_OPCODE_ACCESS_ASO' ],\n \t[ 'HAVE_SUPPORTED_40000baseKR4_Full', 'linux/ethtool.h',\n \t'SUPPORTED_40000baseKR4_Full' ],\n \t[ 'HAVE_SUPPORTED_40000baseCR4_Full', 'linux/ethtool.h',\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9514aba..cd50d13 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -120,7 +120,7 @@\n \t\t\t\t MLX5_WQE_DSEG_SIZE + \\\n \t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE)\n \n-/* Missed in mlv5dv.h, should define here. */\n+/* Missed in mlx5dv.h, should define here. */\n #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW\n #define MLX5_OPCODE_ENHANCED_MPSW 0x29u\n #endif\n@@ -133,6 +133,10 @@\n #define MLX5_OPCODE_WAIT 0x0fu\n #endif\n \n+#ifndef HAVE_MLX5_OPCODE_ACCESS_ASO\n+#define MLX5_OPCODE_ACCESS_ASO 0x2du\n+#endif\n+\n /* CQE value to inform that VLAN is stripped. */\n #define MLX5_CQE_VLAN_STRIPPED (1u << 0)\n \n@@ -2348,6 +2352,66 @@ struct mlx5_ifc_create_flow_hit_aso_in_bits {\n \tstruct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;\n };\n \n+enum mlx5_access_aso_op_mod {\n+\tASO_OP_MOD_IPSEC = 0x0,\n+\tASO_OP_MOD_CONNECTION_TRACKING = 0x1,\n+\tASO_OP_MOD_POLICER = 0x2,\n+\tASO_OP_MOD_RACE_AVOIDANCE = 0x3,\n+\tASO_OP_MOD_FLOW_HIT = 0x4,\n+};\n+\n+enum mlx5_aso_data_mask_mode {\n+\tBITWISE_64BIT = 0x0,\n+\tBYTEWISE_64BYTE = 0x1,\n+\tCALCULATED_64BYTE = 0x2,\n+};\n+\n+enum mlx5_aso_pre_cond_op {\n+\tASO_OP_ALWAYS_FALSE = 0x0,\n+\tASO_OP_ALWAYS_TRUE = 0x1,\n+\tASO_OP_EQUAL = 0x2,\n+\tASO_OP_NOT_EQUAL = 0x3,\n+\tASO_OP_GREATER_OR_EQUAL = 0x4,\n+\tASO_OP_LESSER_OR_EQUAL = 0x5,\n+\tASO_OP_LESSER = 0x6,\n+\tASO_OP_GREATER = 0x7,\n+\tASO_OP_CYCLIC_GREATER = 0x8,\n+\tASO_OP_CYCLIC_LESSER = 0x9,\n+};\n+\n+enum mlx5_aso_op {\n+\tASO_OPER_LOGICAL_AND = 0x0,\n+\tASO_OPER_LOGICAL_OR = 0x1,\n+};\n+\n+/* ASO WQE CTRL segment. */\n+struct mlx5_aso_cseg {\n+\tuint32_t va_h;\n+\tuint32_t va_l_ro;\n+\tuint32_t lkey;\n+\tuint32_t operand_masks;\n+\tuint32_t condition_0_data;\n+\tuint32_t condition_0_mask;\n+\tuint32_t condition_1_data;\n+\tuint32_t condition_1_mask;\n+\tuint64_t bitwise_data;\n+\tuint64_t data_mask;\n+} __rte_packed;\n+\n+#define MLX5_ASO_WQE_DSEG_SIZE\t0x40\n+\n+/* ASO WQE Data segment. */\n+struct mlx5_aso_dseg {\n+\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n+} __rte_packed;\n+\n+/* ASO WQE. */\n+struct mlx5_aso_wqe {\n+\tstruct mlx5_wqe_cseg general_cseg;\n+\tstruct mlx5_aso_cseg aso_cseg;\n+\tstruct mlx5_aso_dseg aso_dseg;\n+} __rte_packed;\n+\n enum {\n \tMLX5_QP_ST_RC = 0x0,\n };\n", "prefixes": [ "5/8" ] }