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GET /api/patches/82445/?format=api
{ "id": 82445, "url": "https://patches.dpdk.org/api/patches/82445/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-69-ophirmu@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027232335.31427-69-ophirmu@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027232335.31427-69-ophirmu@nvidia.com", "date": "2020-10-27T23:23:31", "name": "[v1,68/72] net/mlx5: use HAVE_INFINIBAND_VERBS_H in shared code", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4a6f7f029e81deab00d8d26ebe6550c232dab6cf", "submitter": { "id": 1908, "url": "https://patches.dpdk.org/api/people/1908/?format=api", "name": "Ophir Munk", "email": "ophirmu@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-69-ophirmu@nvidia.com/mbox/", "series": [ { "id": 13395, "url": "https://patches.dpdk.org/api/series/13395/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13395", "date": "2020-10-27T23:22:23", "name": "mlx5 Windows support - part #5", "version": 1, "mbox": "https://patches.dpdk.org/series/13395/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82445/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 166A2A04B5;\n\tWed, 28 Oct 2020 00:42:04 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E5AFC884;\n\tWed, 28 Oct 2020 00:25:36 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 0708E2E1E\n for <dev@dpdk.org>; Wed, 28 Oct 2020 00:24:02 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n ophirmu@nvidia.com) with SMTP; 28 Oct 2020 01:23:59 +0200", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RNNrsK026642;\n Wed, 28 Oct 2020 01:23:59 +0200" ], "From": "Ophir Munk <ophirmu@nvidia.com>", "To": "dev@dpdk.org, Raslan Darawsheh <rasland@nvidia.com>", "Cc": "Ophir Munk <ophirmu@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Tal Shnaiderman <talshn@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>", "Date": "Tue, 27 Oct 2020 23:23:31 +0000", "Message-Id": "<20201027232335.31427-69-ophirmu@nvidia.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20201027232335.31427-1-ophirmu@nvidia.com>", "References": "<20201027232335.31427-1-ophirmu@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 68/72] net/mlx5: use HAVE_INFINIBAND_VERBS_H\n\tin shared code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Use macro HAVE_INFINIBAND_VERBS_H to successfully compile files both\nunder Linux and Windows (or any non Linux in general). Under Windows\nthis macro:\n1. Hides Verbs references.\n2. Exposes required DV structs that are under ifdefs related to rdma\ncore.\n\nLinux code under definitions such as #ifdef HAVE_IBV_FLOW_DV_SUPPORT is\nrequired unconditionally under Windows however those definitions are\nnever effective without rdma-core presence. Therefore update the #ifdef\ncondition to consider HAVE_INFINIBAND_VERBS_H as well (undefined macro\nwhen running without an rdma-core library).\n\nFor example:\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n\nSigned-off-by: Ophir Munk <ophirmu@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 2 +-\n drivers/net/mlx5/mlx5.h | 4 ++--\n drivers/net/mlx5/mlx5_devx.c | 8 ++++----\n drivers/net/mlx5/mlx5_flow.c | 2 +-\n drivers/net/mlx5/mlx5_flow.h | 16 +++++++---------\n drivers/net/mlx5/mlx5_flow_dv.c | 2 +-\n drivers/net/mlx5/mlx5_flow_verbs.c | 6 ++++++\n 7 files changed, 22 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex f4b466f..19d8497 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -187,7 +187,7 @@ static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =\n static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;\n \n static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t{\n \t\t.size = sizeof(struct mlx5_flow_dv_encap_decap_resource),\n \t\t.trunk_size = 64,\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c8192df..3f0211a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -33,7 +33,7 @@\n #include \"mlx5_autoconf.h\"\n \n enum mlx5_ipool_index {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tMLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */\n \tMLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */\n \tMLX5_IPOOL_TAG, /* Pool for tag resource. */\n@@ -746,7 +746,7 @@ struct mlx5_hrxq {\n \t\tvoid *qp; /* Verbs queue pair. */\n \t\tstruct mlx5_devx_obj *tir; /* DevX TIR object. */\n \t};\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tvoid *action; /* DV QP action pointer. */\n #endif\n \tuint64_t hash_fields; /* Verbs Hash fields. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 1aff17c..e03832f 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -854,7 +854,7 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tif (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir,\n \t\t\t\t\t\t\t &hrxq->action)) {\n \t\trte_errno = errno;\n@@ -1024,7 +1024,7 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \treturn 0;\n }\n \n-#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n+#if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)\n /**\n * Release DevX SQ resources.\n *\n@@ -1326,7 +1326,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \n \tif (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)\n \t\treturn mlx5_txq_obj_hairpin_new(dev, idx);\n-#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET\n+#if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H)\n \tDRV_LOG(ERR, \"Port %u Tx queue %u cannot create with DevX, no UAR.\",\n \t\t dev->data->port_id, idx);\n \trte_errno = ENOMEM;\n@@ -1426,7 +1426,7 @@ mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)\n \tif (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {\n \t\tif (txq_obj->tis)\n \t\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));\n-#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n+#if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t} else {\n \t\tmlx5_txq_release_devx_resources(txq_obj);\n #endif\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 93ed113..f009178 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -51,7 +51,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops;\n \n const struct mlx5_flow_driver_ops *flow_drv_ops[] = {\n \t[MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops,\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t[MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops,\n #endif\n \t[MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops,\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 8b5a93f..4819930 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -592,12 +592,6 @@ struct mlx5_flow_dv_dest_array_resource {\n \t/**< Action resources. */\n };\n \n-/* Verbs specification header. */\n-struct ibv_spec_header {\n-\tenum ibv_flow_spec_type type;\n-\tuint16_t size;\n-};\n-\n /* RSS description. */\n struct mlx5_flow_rss_desc {\n \tuint32_t level;\n@@ -651,7 +645,7 @@ struct mlx5_flow_handle {\n \t\tuint32_t rix_default_fate;\n \t\t/**< Indicates default miss fate action. */\n \t};\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tstruct mlx5_flow_handle_dv dvh;\n #endif\n } __rte_packed;\n@@ -661,7 +655,7 @@ struct mlx5_flow_handle {\n * structure in Verbs. No DV flows attributes will be accessed.\n * Macro offsetof() could also be used here.\n */\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n #define MLX5_FLOW_HANDLE_VERBS_SIZE \\\n \t(sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))\n #else\n@@ -699,6 +693,7 @@ struct mlx5_flow_dv_workspace {\n \t/**< Pointer to the destination array resource. */\n };\n \n+#ifdef HAVE_INFINIBAND_VERBS_H\n /*\n * Maximal Verbs flow specifications & actions size.\n * Some elements are mutually exclusive, but enough space should be allocated.\n@@ -755,6 +750,7 @@ struct mlx5_flow_verbs_workspace {\n \tuint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];\n \t/**< Specifications & actions buffer of verbs flow. */\n };\n+#endif /* HAVE_INFINIBAND_VERBS_H */\n \n /** Maximal number of device sub-flows supported. */\n #define MLX5_NUM_MAX_DEV_FLOWS 32\n@@ -769,10 +765,12 @@ struct mlx5_flow {\n \tbool external; /**< true if the flow is created external to PMD. */\n \tuint8_t ingress; /**< 1 if the flow is ingress. */\n \tunion {\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t\tstruct mlx5_flow_dv_workspace dv;\n #endif\n+#ifdef HAVE_INFINIBAND_VERBS_H\n \t\tstruct mlx5_flow_verbs_workspace verbs;\n+#endif\n \t};\n \tstruct mlx5_flow_handle *handle;\n \tuint32_t handle_idx; /* Index of the mlx5 flow handle memory. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 5c772e7..f1de2d3 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -34,7 +34,7 @@\n #include \"mlx5_flow_os.h\"\n #include \"mlx5_rxtx.h\"\n \n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \n #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS\n #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex 6bcc009..d6d3834 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -39,6 +39,12 @@ static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = {\n \t{ 9, 10, 11 }, { 12, 13, 14 },\n };\n \n+/* Verbs specification header. */\n+struct ibv_spec_header {\n+\tenum ibv_flow_spec_type type;\n+\tuint16_t size;\n+};\n+\n /**\n * Discover the maximum number of priority available.\n *\n", "prefixes": [ "v1", "68/72" ] }