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GET /api/patches/82419/?format=api
{ "id": 82419, "url": "https://patches.dpdk.org/api/patches/82419/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-31-ophirmu@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027232335.31427-31-ophirmu@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027232335.31427-31-ophirmu@nvidia.com", "date": "2020-10-27T23:22:53", "name": "[v1,30/72] common/mlx5/windows: add OS reg/dereg MR", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7a23924d7d6c8d8db79e7075e3ea778b26a9527f", "submitter": { "id": 1908, "url": "https://patches.dpdk.org/api/people/1908/?format=api", "name": "Ophir Munk", "email": "ophirmu@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-31-ophirmu@nvidia.com/mbox/", "series": [ { "id": 13395, "url": "https://patches.dpdk.org/api/series/13395/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13395", "date": "2020-10-27T23:22:23", "name": "mlx5 Windows support - part #5", "version": 1, "mbox": "https://patches.dpdk.org/series/13395/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82419/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82419/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BCCACA04B5;\n\tWed, 28 Oct 2020 00:33:53 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7176FACAA;\n\tWed, 28 Oct 2020 00:24:59 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 3B56B34EE\n for <dev@dpdk.org>; Wed, 28 Oct 2020 00:24:01 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n ophirmu@nvidia.com) with SMTP; 28 Oct 2020 01:23:56 +0200", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RNNrrg026642;\n Wed, 28 Oct 2020 01:23:55 +0200" ], "From": "Ophir Munk <ophirmu@nvidia.com>", "To": "dev@dpdk.org, Raslan Darawsheh <rasland@nvidia.com>", "Cc": "Ophir Munk <ophirmu@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Tal Shnaiderman <talshn@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>", "Date": "Tue, 27 Oct 2020 23:22:53 +0000", "Message-Id": "<20201027232335.31427-31-ophirmu@nvidia.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20201027232335.31427-1-ophirmu@nvidia.com>", "References": "<20201027232335.31427-1-ophirmu@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 30/72] common/mlx5/windows: add OS reg/dereg MR", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commits implements Windows API for MR registration and\nderegistration. It is based on DevX. Is support the relaxed ordering\nflow in Windows by checking the capabilities and machine type.\n\nSigned-off-by: Ophir Munk <ophirmu@nvidia.com>\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_mr.h | 1 +\n drivers/common/mlx5/rte_common_mlx5_exports.def | 2 +\n drivers/common/mlx5/windows/mlx5_common_os.c | 78 +++++++++++++++++++++++++\n drivers/common/mlx5/windows/mlx5_common_os.h | 7 +++\n 4 files changed, 88 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h\nindex a2c426d..c4f87a5 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.h\n+++ b/drivers/common/mlx5/mlx5_common_mr.h\n@@ -28,6 +28,7 @@ struct mlx5_pmd_mr {\n \tvoid\t\t *addr;\n \tsize_t\t\t len;\n \tvoid\t\t *obj; /* verbs mr object or devx umem object. */\n+\tstruct mlx5_devx_obj *mkey; /* devx mkey object. */\n };\n \n /**\ndiff --git a/drivers/common/mlx5/rte_common_mlx5_exports.def b/drivers/common/mlx5/rte_common_mlx5_exports.def\nindex 1d12e71..23eee59 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_exports.def\n+++ b/drivers/common/mlx5/rte_common_mlx5_exports.def\n@@ -61,5 +61,7 @@ EXPORTS\n \tmlx5_free\n \tmlx5_os_alloc_pd\n \tmlx5_os_dealloc_pd\n+\tmlx5_os_dereg_mr\n+\tmlx5_os_reg_mr\n \tmlx5_os_umem_reg\n \tmlx5_os_umem_dereg\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c\nindex c8343ad..52d609a 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.c\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.c\n@@ -14,6 +14,8 @@\n #include \"mlx5_devx_cmds.h\"\n #include \"mlx5_common_utils.h\"\n #include <mlx5_common.h>\n+#include \"mlx5_common_os.h\"\n+#include \"mlx5_malloc.h\"\n \n /**\n * Initialization routine for run-time dependency on external lib\n@@ -129,3 +131,79 @@ mlx5_os_umem_dereg(void *pumem)\n \tmlx5_free(umem);\n \treturn err;\n }\n+\n+/**\n+ * Register mr. Given protection doamin pointer, pointer to addr and length\n+ * register the memory region.\n+ *\n+ * @param[in] pd\n+ * Pointer to protection domain context (type mlx5_pd).\n+ * @param[in] addr\n+ * Pointer to memory start address (type devx_device_ctx).\n+ * @param[in] length\n+ * Lengtoh of the memory to register.\n+ * @param[out] pmd_mr\n+ * pmd_mr struct set with lkey, address, length, pointer to mr object, mkey\n+ *\n+ * @return\n+ * 0 on successful registration, -1 otherwise\n+ */\n+int\n+mlx5_os_reg_mr(void *pd,\n+\t void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr)\n+{\n+\tstruct mlx5_devx_mkey_attr mkey_attr;\n+\tstruct mlx5_pd *mlx5_pd = (struct mlx5_pd *)pd;\n+\tstruct mlx5_hca_attr attr;\n+\n+\tif (!pd || !addr) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -1;\n+\t}\n+\tmemset(pmd_mr, 0, sizeof(*pmd_mr));\n+\tif (mlx5_devx_cmd_query_hca_attr(mlx5_pd->devx_ctx, &attr))\n+\t\treturn -1;\n+\tpmd_mr->addr = addr;\n+\tpmd_mr->len = length;\n+\tpmd_mr->obj = mlx5_os_umem_reg(mlx5_pd->devx_ctx, pmd_mr->addr,\n+\t\t\t\t pmd_mr->len, IBV_ACCESS_LOCAL_WRITE);\n+\tif (!pmd_mr->obj)\n+\t\treturn -1;\n+\tmkey_attr.addr = (uintptr_t)addr;\n+\tmkey_attr.size = length;\n+\tmkey_attr.umem_id = ((struct mlx5_devx_umem *)(pmd_mr->obj))->umem_id;\n+\tmkey_attr.pd = mlx5_pd->pdn;\n+\tmkey_attr.log_entity_size = 0;\n+\tmkey_attr.pg_access = 0;\n+\tmkey_attr.klm_array = NULL;\n+\tmkey_attr.klm_num = 0;\n+\tmkey_attr.relaxed_ordering_read = 0;\n+\tmkey_attr.relaxed_ordering_write = 0;\n+\tif (!haswell_broadwell_cpu) {\n+\t\tmkey_attr.relaxed_ordering_write = attr.relaxed_ordering_write;\n+\t\tmkey_attr.relaxed_ordering_read = attr.relaxed_ordering_read;\n+\t}\n+\tpmd_mr->mkey = mlx5_devx_cmd_mkey_create(mlx5_pd->devx_ctx, &mkey_attr);\n+\tif (!pmd_mr->mkey) {\n+\t\tclaim_zero(mlx5_os_umem_dereg(pmd_mr->obj));\n+\t\treturn -1;\n+\t}\n+\tpmd_mr->lkey = pmd_mr->mkey->id;\n+\treturn 0;\n+}\n+\n+/**\n+ * De-register mr.\n+ *\n+ * @param[in] pmd_mr\n+ * Pointer to PMD mr object\n+ */\n+void\n+mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr)\n+{\n+\tif (pmd_mr && pmd_mr->mkey)\n+\t\tclaim_zero(mlx5_glue->devx_obj_destroy(pmd_mr->mkey->obj));\n+\tif (pmd_mr && pmd_mr->obj)\n+\t\tclaim_zero(mlx5_os_umem_dereg(pmd_mr->obj));\n+\tmemset(pmd_mr, 0, sizeof(*pmd_mr));\n+}\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h\nindex decb5ac..ba16641 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.h\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.h\n@@ -7,9 +7,13 @@\n \n #include <stdio.h>\n \n+#include <rte_errno.h>\n+\n #include \"mlx5_autoconf.h\"\n #include \"mlx5_glue.h\"\n #include \"mlx5_malloc.h\"\n+#include \"mlx5_common_mr.h\"\n+#include \"mlx5_win_ext.h\"\n \n /**\n * This API allocates aligned or non-aligned memory. The free can be on either\n@@ -144,4 +148,7 @@ void *mlx5_os_alloc_pd(void *ctx);\n int mlx5_os_dealloc_pd(void *pd);\n void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access);\n int mlx5_os_umem_dereg(void *pumem);\n+int mlx5_os_reg_mr(void *pd,\n+\t\t void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr);\n+void mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr);\n #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */\n", "prefixes": [ "v1", "30/72" ] }