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GET /api/patches/82406/?format=api
{ "id": 82406, "url": "https://patches.dpdk.org/api/patches/82406/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-20-ophirmu@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201027232335.31427-20-ophirmu@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201027232335.31427-20-ophirmu@nvidia.com", "date": "2020-10-27T23:22:42", "name": "[v1,19/72] common/mlx5: extend DevX query hca attributes command", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c3fc9ab6567e160d269daf0872c0f019fc5d890a", "submitter": { "id": 1908, "url": "https://patches.dpdk.org/api/people/1908/?format=api", "name": "Ophir Munk", "email": "ophirmu@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201027232335.31427-20-ophirmu@nvidia.com/mbox/", "series": [ { "id": 13395, "url": "https://patches.dpdk.org/api/series/13395/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13395", "date": "2020-10-27T23:22:23", "name": "mlx5 Windows support - part #5", "version": 1, "mbox": "https://patches.dpdk.org/series/13395/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82406/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82406/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BF5DA04B5;\n\tWed, 28 Oct 2020 00:29:27 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AB4745AB7;\n\tWed, 28 Oct 2020 00:24:40 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 9F4662DCC\n for <dev@dpdk.org>; Wed, 28 Oct 2020 00:24:00 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n ophirmu@nvidia.com) with SMTP; 28 Oct 2020 01:23:54 +0200", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RNNrrV026642;\n Wed, 28 Oct 2020 01:23:54 +0200" ], "From": "Ophir Munk <ophirmu@nvidia.com>", "To": "dev@dpdk.org, Raslan Darawsheh <rasland@nvidia.com>", "Cc": "Ophir Munk <ophirmu@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Tal Shnaiderman <talshn@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>", "Date": "Tue, 27 Oct 2020 23:22:42 +0000", "Message-Id": "<20201027232335.31427-20-ophirmu@nvidia.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20201027232335.31427-1-ophirmu@nvidia.com>", "References": "<20201027232335.31427-1-ophirmu@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 19/72] common/mlx5: extend DevX query hca\n\tattributes command", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tal Shnaiderman <talshn@nvidia.com>\n\nExtend DevX API mlx5_devx_cmd_query_hca_attr() to report on max number\nof available objects including: CQ, QP, PD, SRQ.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 11 +++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 10 +++++++++-\n drivers/common/mlx5/mlx5_prm.h | 1 +\n 3 files changed, 21 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 27eff5f..ee1baf8 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -718,6 +718,14 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);\n \tattr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t regexp_num_of_engines);\n+\tattr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);\n+\tattr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);\n+\tattr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);\n+\tattr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);\n+\tattr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);\n+\tattr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);\n+\tattr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);\n+\tattr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\n@@ -832,6 +840,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->tunnel_stateless_gtp = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, tunnel_stateless_gtp);\n+\tattr->rss_ind_tbl_cap = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, rss_ind_tbl_cap);\n \tif (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)\n \t\treturn 0;\n \tif (attr->eth_virt) {\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 25cf12e..b654e42 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -107,6 +107,15 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_ft_sampler_num:8;\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n+\tint log_max_qp_sz;\n+\tint log_max_cq_sz;\n+\tint log_max_qp;\n+\tint log_max_cq;\n+\tuint32_t log_max_pd;\n+\tuint32_t log_max_mrw_sz;\n+\tuint32_t log_max_srq;\n+\tuint32_t log_max_srq_sz;\n+\tuint32_t rss_ind_tbl_cap;\n };\n \n struct mlx5_devx_wq_attr {\n@@ -483,5 +492,4 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);\n __rte_internal\n int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,\n \t\t\t\t struct mlx5_devx_virtio_q_couners_attr *attr);\n-\n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex d342263..8b9b694 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -649,6 +649,7 @@ typedef uint8_t u8;\n #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \\\n \t\t\t\t\t\t __mlx5_64_off(typ, fld)))\n #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)\n+#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)\n \n struct mlx5_ifc_fte_match_set_misc_bits {\n \tu8 gre_c_present[0x1];\n", "prefixes": [ "v1", "19/72" ] }