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GET /api/patches/82298/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 82298,
    "url": "https://patches.dpdk.org/api/patches/82298/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603801650-442376-11-git-send-email-suanmingm@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1603801650-442376-11-git-send-email-suanmingm@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1603801650-442376-11-git-send-email-suanmingm@nvidia.com",
    "date": "2020-10-27T12:27:05",
    "name": "[v3,10/34] net/mlx5: create global default miss action",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b97812d773d6e0da9ac820890ed37ff1ffa49c2a",
    "submitter": {
        "id": 1887,
        "url": "https://patches.dpdk.org/api/people/1887/?format=api",
        "name": "Suanming Mou",
        "email": "suanmingm@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603801650-442376-11-git-send-email-suanmingm@nvidia.com/mbox/",
    "series": [
        {
            "id": 13372,
            "url": "https://patches.dpdk.org/api/series/13372/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13372",
            "date": "2020-10-27T12:26:55",
            "name": "net/mlx5: support multiple-thread flow operations",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/13372/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/82298/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/82298/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1A3B0A04B5;\n\tTue, 27 Oct 2020 13:31:51 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F30CB5958;\n\tTue, 27 Oct 2020 13:29:04 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 2B4272DCC\n for <dev@dpdk.org>; Tue, 27 Oct 2020 13:27:58 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 27 Oct 2020 14:27:54 +0200",
            "from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09RCRZ78024637;\n Tue, 27 Oct 2020 14:27:53 +0200"
        ],
        "From": "Suanming Mou <suanmingm@nvidia.com>",
        "To": "Matan Azrad <matan@nvidia.com>, Shahaf Shuler <shahafs@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Cc": "dev@dpdk.org",
        "Date": "Tue, 27 Oct 2020 20:27:05 +0800",
        "Message-Id": "<1603801650-442376-11-git-send-email-suanmingm@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1603801650-442376-1-git-send-email-suanmingm@nvidia.com>",
        "References": "<1601984948-313027-1-git-send-email-suanmingm@nvidia.com>\n <1603801650-442376-1-git-send-email-suanmingm@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v3 10/34] net/mlx5: create global default miss\n\taction",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This commit creates the global default miss action instead of maintain\nit in flow insertion time. This makes the action to be thread safe.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c |  7 ++++\n drivers/net/mlx5/mlx5.h          |  9 +---\n drivers/net/mlx5/mlx5_flow_dv.c  | 88 +++-------------------------------------\n 3 files changed, 13 insertions(+), 91 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex a579dde..ae735a3 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -305,6 +305,10 @@\n \t}\n \tsh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();\n #endif /* HAVE_MLX5DV_DR */\n+\tsh->default_miss_action =\n+\t\t\tmlx5_glue->dr_create_flow_action_default_miss();\n+\tif (!sh->default_miss_action)\n+\t\tDRV_LOG(WARNING, \"Default miss action is not supported.\");\n \treturn 0;\n error:\n \t/* Rollback the created objects. */\n@@ -388,6 +392,9 @@\n \t}\n \tpthread_mutex_destroy(&sh->dv_mutex);\n #endif /* HAVE_MLX5DV_DR */\n+\tif (sh->default_miss_action)\n+\t\tmlx5_glue->destroy_flow_action\n+\t\t\t\t(sh->default_miss_action);\n \tif (sh->encaps_decaps) {\n \t\tmlx5_hlist_destroy(sh->encaps_decaps, NULL, NULL);\n \t\tsh->encaps_decaps = NULL;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4446be2..057a761 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -464,12 +464,6 @@ struct mlx5_flow_counter_mng {\n \tLIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;\n };\n \n-/* Default miss action resource structure. */\n-struct mlx5_flow_default_miss_resource {\n-\tvoid *action; /* Pointer to the rdma-core action. */\n-\trte_atomic32_t refcnt; /* Default miss action reference counter. */\n-};\n-\n #define MLX5_AGE_EVENT_NEW\t\t1\n #define MLX5_AGE_TRIGGER\t\t2\n #define MLX5_AGE_SET(age_info, BIT) \\\n@@ -664,8 +658,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t sample_action_list; /* List of sample actions. */\n \tuint32_t dest_array_list; /* List of destination array actions. */\n \tstruct mlx5_flow_counter_mng cmng; /* Counters management structure. */\n-\tstruct mlx5_flow_default_miss_resource default_miss;\n-\t/* Default miss action resource structure. */\n+\tvoid *default_miss_action; /* Default miss action. */\n \tstruct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];\n \t/* Memory Pool for mlx5 flow resources. */\n \tstruct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 767e580..b28cc6d 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -74,9 +74,6 @@\n \t\t\t     struct mlx5_flow_tbl_resource *tbl);\n \n static int\n-flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);\n-\n-static int\n flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,\n \t\t\t\t      uint32_t encap_decap_idx);\n \n@@ -2950,42 +2947,6 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n- * Find existing default miss resource or create and register a new one.\n- *\n- * @param[in, out] dev\n- *   Pointer to rte_eth_dev structure.\n- * @param[out] error\n- *   pointer to error structure.\n- *\n- * @return\n- *   0 on success otherwise -errno and errno is set.\n- */\n-static int\n-flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,\n-\t\tstruct rte_flow_error *error)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_flow_default_miss_resource *cache_resource =\n-\t\t\t&sh->default_miss;\n-\tint cnt = rte_atomic32_read(&cache_resource->refcnt);\n-\n-\tif (!cnt) {\n-\t\tMLX5_ASSERT(cache_resource->action);\n-\t\tcache_resource->action =\n-\t\tmlx5_glue->dr_create_flow_action_default_miss();\n-\t\tif (!cache_resource->action)\n-\t\t\treturn rte_flow_error_set(error, ENOMEM,\n-\t\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n-\t\t\t\t\t\"cannot create default miss action\");\n-\t\tDRV_LOG(DEBUG, \"new default miss resource %p: refcnt %d++\",\n-\t\t\t\t(void *)cache_resource->action, cnt);\n-\t}\n-\trte_atomic32_inc(&cache_resource->refcnt);\n-\treturn 0;\n-}\n-\n-/**\n  * Find existing table port ID resource or create and register a new one.\n  *\n  * @param[in, out] dev\n@@ -10384,16 +10345,14 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tdh->rix_hrxq = hrxq_idx;\n \t\t\tdv->actions[n++] = hrxq->action;\n \t\t} else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {\n-\t\t\tif (flow_dv_default_miss_resource_register\n-\t\t\t\t\t(dev, error)) {\n+\t\t\tif (!priv->sh->default_miss_action) {\n \t\t\t\trte_flow_error_set\n \t\t\t\t\t(error, rte_errno,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n-\t\t\t\t\t \"cannot create default miss resource\");\n-\t\t\t\tgoto error_default_miss;\n+\t\t\t\t\t \"default miss action not be created.\");\n+\t\t\t\tgoto error;\n \t\t\t}\n-\t\t\tdh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;\n-\t\t\tdv->actions[n++] = priv->sh->default_miss.action;\n+\t\t\tdv->actions[n++] = priv->sh->default_miss_action;\n \t\t}\n \t\terr = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,\n \t\t\t\t\t       (void *)&dv->value, n,\n@@ -10418,9 +10377,6 @@ struct field_modify_info modify_tcp[] = {\n \t}\n \treturn 0;\n error:\n-\tif (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)\n-\t\tflow_dv_default_miss_resource_release(dev);\n-error_default_miss:\n \terr = rte_errno; /* Save rte_errno before cleanup. */\n \tSILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,\n \t\t       handle_idx, dh, next) {\n@@ -10542,36 +10498,6 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n- * Release a default miss resource.\n- *\n- * @param dev\n- *   Pointer to Ethernet device.\n- * @return\n- *   1 while a reference on it exists, 0 when freed.\n- */\n-static int\n-flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_flow_default_miss_resource *cache_resource =\n-\t\t\t&sh->default_miss;\n-\n-\tMLX5_ASSERT(cache_resource->action);\n-\tDRV_LOG(DEBUG, \"default miss resource %p: refcnt %d--\",\n-\t\t\t(void *)cache_resource->action,\n-\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n-\t\tclaim_zero(mlx5_glue->destroy_flow_action\n-\t\t\t\t(cache_resource->action));\n-\t\tDRV_LOG(DEBUG, \"default miss resource %p: removed\",\n-\t\t\t\t(void *)cache_resource->action);\n-\t\treturn 0;\n-\t}\n-\treturn 1;\n-}\n-\n-/**\n  * Release a modify-header resource.\n  *\n  * @param dev\n@@ -10717,9 +10643,6 @@ struct field_modify_info modify_tcp[] = {\n \t\tflow_dv_port_id_action_resource_release(dev,\n \t\t\t\thandle->rix_port_id_action);\n \t\tbreak;\n-\tcase MLX5_FLOW_FATE_DEFAULT_MISS:\n-\t\tflow_dv_default_miss_resource_release(dev);\n-\t\tbreak;\n \tdefault:\n \t\tDRV_LOG(DEBUG, \"Incorrect fate action:%d\", handle->fate_action);\n \t\tbreak;\n@@ -10890,8 +10813,7 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tdh->drv_flow = NULL;\n \t\t}\n \t\tif (dh->fate_action == MLX5_FLOW_FATE_DROP ||\n-\t\t    dh->fate_action == MLX5_FLOW_FATE_QUEUE ||\n-\t\t    dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)\n+\t\t    dh->fate_action == MLX5_FLOW_FATE_QUEUE)\n \t\t\tflow_dv_fate_resource_release(dev, dh);\n \t\tif (dh->vf_vlan.tag && dh->vf_vlan.created)\n \t\t\tmlx5_vlan_vmwa_release(dev, &dh->vf_vlan);\n",
    "prefixes": [
        "v3",
        "10/34"
    ]
}