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GET /api/patches/82183/?format=api
{ "id": 82183, "url": "https://patches.dpdk.org/api/patches/82183/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603710656-32187-1-git-send-email-xuemingl@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603710656-32187-1-git-send-email-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603710656-32187-1-git-send-email-xuemingl@nvidia.com", "date": "2020-10-26T11:10:55", "name": "[1/2] common/mlx5: get number of ports that can be bonded", "commit_ref": null, "pull_url": null, "state": "new", "archived": true, "hash": "ad507c87cc1c514904c3d56fd0c6729454d3a5de", "submitter": { "id": 1904, "url": "https://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603710656-32187-1-git-send-email-xuemingl@nvidia.com/mbox/", "series": [ { "id": 13323, "url": "https://patches.dpdk.org/api/series/13323/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13323", "date": "2020-10-26T11:10:55", "name": "[1/2] common/mlx5: get number of ports that can be bonded", "version": 1, "mbox": "https://patches.dpdk.org/series/13323/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82183/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82183/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 08D51A04B5;\n\tMon, 26 Oct 2020 12:11:24 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B60CE2BD3;\n\tMon, 26 Oct 2020 12:11:20 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 254242BA2\n for <dev@dpdk.org>; Mon, 26 Oct 2020 12:11:19 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n xuemingl@nvidia.com) with SMTP; 26 Oct 2020 13:11:12 +0200", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09QBBC6T027455;\n Mon, 26 Oct 2020 13:11:12 +0200" ], "From": "Xueming Li <xuemingl@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Cc": "dev@dpdk.org, xuemingl@nvidia.com, Asaf Penso <asafp@nvidia.com>,\n stable@dpdk.org", "Date": "Mon, 26 Oct 2020 11:10:55 +0000", "Message-Id": "<1603710656-32187-1-git-send-email-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH 1/2] common/mlx5: get number of ports that can be\n\tbonded", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Get HCA capability: number of physical ports that can be bonded.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++--\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n 2 files changed, 4 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 8aee12d527..e748d034d0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -711,6 +711,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);\n \tattr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t log_max_static_sq_wq);\n+\tattr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);\n \tattr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t device_frequency_khz);\n \tattr->scatter_fcs_w_decap_disable =\n@@ -1429,8 +1430,8 @@ mlx5_devx_cmd_create_tis(void *ctx,\n \ttis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);\n \tMLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,\n \t\t tis_attr->strict_lag_tx_port_affinity);\n-\tMLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,\n-\t\t tis_attr->strict_lag_tx_port_affinity);\n+\tMLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,\n+\t\t tis_attr->lag_tx_port_affinity);\n \tMLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);\n \tMLX5_SET(tisc, tis_ctx, transport_domain,\n \t\t tis_attr->transport_domain);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex abbea67784..3781fedd9e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -99,6 +99,7 @@ struct mlx5_hca_attr {\n \tuint32_t cross_channel:1;\n \tuint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */\n \tuint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */\n+\tuint32_t num_lag_ports:4; /* Number of ports can be bonded. */\n \tuint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */\n \tuint32_t scatter_fcs_w_decap_disable:1;\n \tuint32_t regex:1;\n", "prefixes": [ "1/2" ] }