get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/82069/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 82069,
    "url": "https://patches.dpdk.org/api/patches/82069/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201025002953.1680999-3-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201025002953.1680999-3-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201025002953.1680999-3-qi.z.zhang@intel.com",
    "date": "2020-10-25T00:29:34",
    "name": "[v2,02/21] net/ice/base: add NVM Write Response flags",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8fb35aed659222aba0c2e203316198b1fd6a804d",
    "submitter": {
        "id": 504,
        "url": "https://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201025002953.1680999-3-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 13297,
            "url": "https://patches.dpdk.org/api/series/13297/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13297",
            "date": "2020-10-25T00:29:32",
            "name": "ice: update base code",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/13297/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/82069/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/82069/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7EC6BA04B5;\n\tSun, 25 Oct 2020 02:26:48 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 982461E35;\n\tSun, 25 Oct 2020 02:26:06 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 23F3E106B\n for <dev@dpdk.org>; Sun, 25 Oct 2020 02:26:02 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Oct 2020 17:26:01 -0700",
            "from dpdk51.sh.intel.com ([10.67.111.142])\n by FMSMGA003.fm.intel.com with ESMTP; 24 Oct 2020 17:26:00 -0700"
        ],
        "IronPort-SDR": [
            "\n Q87XHbX5F7mtc/MmRMWb1RVy3okmo99Q3fGi9bsvXA2VCBl1+xIWKfihqVlVVI0knp6+7nq9pU\n Lvsn5ftDiqTQ==",
            "\n jKVttwV+sq/dyiPLUdaS5uoCfevV9Bxt/8lmLGnhUtlq6NXF2GgMIgWIlzzxt2psVyjltKIzZt\n X1yCUrUMm+DQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9784\"; a=\"167927026\"",
            "E=Sophos;i=\"5.77,414,1596524400\"; d=\"scan'208\";a=\"167927026\"",
            "E=Sophos;i=\"5.77,414,1596524400\"; d=\"scan'208\";a=\"359984002\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Amir Shay <shay.amir@intel.com>",
        "Date": "Sun, 25 Oct 2020 08:29:34 +0800",
        "Message-Id": "<20201025002953.1680999-3-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.4",
        "In-Reply-To": "<20201025002953.1680999-1-qi.z.zhang@intel.com>",
        "References": "<20201025002953.1680999-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 02/21] net/ice/base: add NVM Write Response\n\tflags",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Added NVM Write Admin Command (0x703) ARQ response flags - as\nreturned in \"Response flags\" field.\nThree flags are supported: POR, PERST and EMPR. All indicate the\ntype of reset required to get the NVM bank update effective.\n\nSigned-off-by: Amir Shay <shay.amir@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 3 +++\n 1 file changed, 3 insertions(+)",
    "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex bc71ec5317..9db50de11c 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1654,6 +1654,9 @@ struct ice_aqc_nvm {\n #define ICE_AQC_NVM_REVERT_LAST_ACTIV\tBIT(6) /* Write Activate only */\n #define ICE_AQC_NVM_ACTIV_SEL_MASK\tMAKEMASK(0x7, 3)\n #define ICE_AQC_NVM_FLASH_ONLY\t\tBIT(7)\n+#define ICE_AQC_NVM_POR_FLAG\t0\t/* Used by NVM Write completion on ARQ */\n+#define ICE_AQC_NVM_PERST_FLAG\t1\n+#define ICE_AQC_NVM_EMPR_FLAG\t2\n \t__le16 module_typeid;\n \t__le16 length;\n #define ICE_AQC_NVM_ERASE_LEN\t0xFFFF\n",
    "prefixes": [
        "v2",
        "02/21"
    ]
}