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GET /api/patches/81964/?format=api
{ "id": 81964, "url": "https://patches.dpdk.org/api/patches/81964/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603477826-31374-4-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603477826-31374-4-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603477826-31374-4-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-10-23T18:30:06", "name": "[v3,03/23] event/dlb2: add private data structures and constants", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "277e7d6ff59995886a2ab50143fe33b239fa899b", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603477826-31374-4-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 13284, "url": "https://patches.dpdk.org/api/series/13284/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13284", "date": "2020-10-23T18:30:03", "name": "Add DLB2 PMD", "version": 3, "mbox": "https://patches.dpdk.org/series/13284/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/81964/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/81964/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4DAA6A04DD;\n\tFri, 23 Oct 2020 20:29:18 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E42DA5AA6;\n\tFri, 23 Oct 2020 20:28:42 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by dpdk.org (Postfix) with ESMTP id E0C285A8C\n for <dev@dpdk.org>; Fri, 23 Oct 2020 20:28:36 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Oct 2020 11:28:35 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 23 Oct 2020 11:28:35 -0700" ], "IronPort-SDR": [ "\n iRv56b4NcH/pHzYJAYFlk6LgsL5a9f1qye0tf5xZIoGJ1DDQkRGuX/k38anG+EITY6AokjQ3Gv\n R080WEbd0tIg==", "\n +pJBDrkvgby3aKCIVvn8mPvflo4iHwPGZnV2wfJEWTFhDR/j5FW7XWbjSM1ZPWH/uPzd8czJ39\n TwMBGU7cldUg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9783\"; a=\"167809538\"", "E=Sophos;i=\"5.77,409,1596524400\"; d=\"scan'208\";a=\"167809538\"", "E=Sophos;i=\"5.77,409,1596524400\"; d=\"scan'208\";a=\"524763978\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com", "Date": "Fri, 23 Oct 2020 13:30:06 -0500", "Message-Id": "<1603477826-31374-4-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1603477826-31374-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<1599855987-25976-2-git-send-email-timothy.mcdaniel@intel.com>\n <1603477826-31374-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 03/23] event/dlb2: add private data structures\n\tand constants", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The header file dlb2_priv.h is used internally by the PMD.\nIt include constants, macros for device resources,\nstructure definitions for hardware interfaces and\nsoftware state, and various forward-declarations.\nThe header file rte_pmd_dlb2.h will be exported in a\nsubsequent patch, but is included here due to a data\nstructure dependency.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\nReviewed-by: Gage Eads <gage.eads@intel.com>\n---\n drivers/event/dlb2/dlb2_priv.h | 575 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 575 insertions(+)\n create mode 100644 drivers/event/dlb2/dlb2_priv.h", "diff": "diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nnew file mode 100644\nindex 0000000..61567a6\n--- /dev/null\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -0,0 +1,575 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#ifndef _DLB2_PRIV_H_\n+#define _DLB2_PRIV_H_\n+\n+#include <emmintrin.h>\n+#include <stdbool.h>\n+\n+#include <rte_eventdev.h>\n+#include <rte_config.h>\n+#include \"dlb2_user.h\"\n+#include \"dlb2_log.h\"\n+\n+#ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS\n+#define DLB2_INC_STAT(_stat, _incr_val) ((_stat) += _incr_val)\n+#else\n+#define DLB2_INC_STAT(_stat, _incr_val)\n+#endif\n+\n+#define EVDEV_DLB2_NAME_PMD dlb2_event\n+\n+/* command line arg strings */\n+#define NUMA_NODE_ARG \"numa_node\"\n+#define DLB2_MAX_NUM_EVENTS \"max_num_events\"\n+#define DLB2_NUM_DIR_CREDITS \"num_dir_credits\"\n+#define DEV_ID_ARG \"dev_id\"\n+#define DLB2_DEFER_SCHED_ARG \"defer_sched\"\n+#define DLB2_QID_DEPTH_THRESH_ARG \"qid_depth_thresh\"\n+#define DLB2_COS_ARG \"cos\"\n+\n+/* Begin HW related defines and structs */\n+\n+#define DLB2_MAX_NUM_DOMAINS 32\n+#define DLB2_MAX_NUM_VFS 16\n+#define DLB2_MAX_NUM_LDB_QUEUES 32\n+#define DLB2_MAX_NUM_LDB_PORTS 64\n+#define DLB2_MAX_NUM_DIR_PORTS 64\n+#define DLB2_MAX_NUM_DIR_QUEUES 64\n+#define DLB2_MAX_NUM_FLOWS (64 * 1024)\n+#define DLB2_MAX_NUM_LDB_CREDITS (8 * 1024)\n+#define DLB2_MAX_NUM_DIR_CREDITS (2 * 1024)\n+#define DLB2_MAX_NUM_LDB_CREDIT_POOLS 64\n+#define DLB2_MAX_NUM_DIR_CREDIT_POOLS 64\n+#define DLB2_MAX_NUM_HIST_LIST_ENTRIES 2048\n+#define DLB2_MAX_NUM_AQOS_ENTRIES 2048\n+#define DLB2_MAX_NUM_QIDS_PER_LDB_CQ 8\n+#define DLB2_QID_PRIORITIES 8\n+#define DLB2_MAX_DEVICE_PATH 32\n+#define DLB2_MIN_DEQUEUE_TIMEOUT_NS 1\n+/* Note: \"- 1\" here to support the timeout range check in eventdev_autotest */\n+#define DLB2_MAX_DEQUEUE_TIMEOUT_NS (UINT32_MAX - 1)\n+#define DLB2_SW_CREDIT_BATCH_SZ 32\n+#define DLB2_NUM_SN_GROUPS 2\n+#define DLB2_MAX_LDB_SN_ALLOC 1024\n+#define DLB2_MAX_QUEUE_DEPTH_THRESHOLD 8191\n+\n+/* 2048 total hist list entries and 64 total ldb ports, which\n+ * makes for 2048/64 == 32 hist list entries per port. However, CQ\n+ * depth must be a power of 2 and must also be >= HIST LIST entries.\n+ * As a result we just limit the maximum dequeue depth to 32.\n+ */\n+#define DLB2_MIN_CQ_DEPTH 1\n+#define DLB2_MAX_CQ_DEPTH 32\n+#define DLB2_MIN_HARDWARE_CQ_DEPTH 8\n+#define DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT \\\n+\tDLB2_MAX_CQ_DEPTH\n+\n+/*\n+ * Static per queue/port provisioning values\n+ */\n+#define DLB2_NUM_ATOMIC_INFLIGHTS_PER_QUEUE 64\n+\n+#define CQ_BASE(is_dir) ((is_dir) ? DLB2_DIR_CQ_BASE : DLB2_LDB_CQ_BASE)\n+#define CQ_SIZE(is_dir) ((is_dir) ? DLB2_DIR_CQ_MAX_SIZE : \\\n+\t\t\t\t DLB2_LDB_CQ_MAX_SIZE)\n+#define PP_BASE(is_dir) ((is_dir) ? DLB2_DIR_PP_BASE : DLB2_LDB_PP_BASE)\n+\n+#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n+\n+#define DLB2_NUM_QES_PER_CACHE_LINE 4\n+\n+#define DLB2_MAX_ENQUEUE_DEPTH 64\n+#define DLB2_MIN_ENQUEUE_DEPTH 4\n+\n+#define DLB2_NAME_SIZE 64\n+\n+#define DLB2_1K 1024\n+#define DLB2_2K (2 * DLB2_1K)\n+#define DLB2_4K (4 * DLB2_1K)\n+#define DLB2_16K (16 * DLB2_1K)\n+#define DLB2_32K (32 * DLB2_1K)\n+#define DLB2_1MB (DLB2_1K * DLB2_1K)\n+#define DLB2_16MB (16 * DLB2_1MB)\n+\n+/* Use the upper 3 bits of the event priority to select the DLB2 priority */\n+#define EV_TO_DLB2_PRIO(x) ((x) >> 5)\n+#define DLB2_TO_EV_PRIO(x) ((x) << 5)\n+\n+enum dlb2_hw_port_types {\n+\tDLB2_LDB_PORT,\n+\tDLB2_DIR_PORT,\n+\tDLB2_NUM_PORT_TYPES /* Must be last */\n+};\n+\n+enum dlb2_hw_queue_types {\n+\tDLB2_LDB_QUEUE,\n+\tDLB2_DIR_QUEUE,\n+\tDLB2_NUM_QUEUE_TYPES /* Must be last */\n+};\n+\n+#define PORT_TYPE(p) ((p)->is_directed ? DLB2_DIR_PORT : DLB2_LDB_PORT)\n+\n+/* Do not change - must match hardware! */\n+enum dlb2_hw_sched_type {\n+\tDLB2_SCHED_ATOMIC = 0,\n+\tDLB2_SCHED_UNORDERED,\n+\tDLB2_SCHED_ORDERED,\n+\tDLB2_SCHED_DIRECTED,\n+\t/* DLB2_NUM_HW_SCHED_TYPES must be last */\n+\tDLB2_NUM_HW_SCHED_TYPES\n+};\n+\n+struct dlb2_hw_rsrcs {\n+\tint32_t nb_events_limit;\n+\tuint32_t num_queues;\t\t/* Total queues (lb + dir) */\n+\tuint32_t num_ldb_queues;\t/* Number of available ldb queues */\n+\tuint32_t num_ldb_ports; /* Number of load balanced ports */\n+\tuint32_t num_dir_ports; /* Number of directed ports */\n+\tuint32_t num_ldb_credits; /* Number of load balanced credits */\n+\tuint32_t num_dir_credits; /* Number of directed credits */\n+\tuint32_t reorder_window_size; /* Size of reorder window */\n+};\n+\n+struct dlb2_hw_resource_info {\n+\t/**> Max resources that can be provided */\n+\tstruct dlb2_hw_rsrcs hw_rsrc_max;\n+\tint num_sched_domains;\n+\tuint32_t socket_id;\n+};\n+\n+enum dlb2_enqueue_type {\n+\t/**>\n+\t * New : Used to inject a new packet into the QM.\n+\t */\n+\tDLB2_ENQ_NEW,\n+\t/**>\n+\t * Forward : Enqueues a packet, and\n+\t * - if atomic: release any lock it holds in the QM\n+\t * - if ordered: release the packet for egress re-ordering\n+\t */\n+\tDLB2_ENQ_FWD,\n+\t/**>\n+\t * Enqueue Drop : Release an inflight packet. Must be called with\n+\t * event == NULL. Used to drop a packet.\n+\t *\n+\t * Note that all packets dequeued from a load-balanced port must be\n+\t * released, either with DLB2_ENQ_DROP or DLB2_ENQ_FWD.\n+\t */\n+\tDLB2_ENQ_DROP,\n+\n+\t/* marker for array sizing etc. */\n+\t_DLB2_NB_ENQ_TYPES\n+};\n+\n+/* hw-specific format - do not change */\n+\n+struct dlb2_event_type {\n+\tuint8_t major:4;\n+\tuint8_t unused:4;\n+\tuint8_t sub;\n+};\n+\n+union dlb2_opaque_data {\n+\tuint16_t opaque_data;\n+\tstruct dlb2_event_type event_type;\n+};\n+\n+struct dlb2_msg_info {\n+\tuint8_t qid;\n+\tuint8_t sched_type:2;\n+\tuint8_t priority:3;\n+\tuint8_t msg_type:3;\n+};\n+\n+#define DLB2_NEW_CMD_BYTE 0x08\n+#define DLB2_FWD_CMD_BYTE 0x0A\n+#define DLB2_COMP_CMD_BYTE 0x02\n+#define DLB2_POP_CMD_BYTE 0x01\n+#define DLB2_NOOP_CMD_BYTE 0x00\n+\n+/* hw-specific format - do not change */\n+struct dlb2_enqueue_qe {\n+\tuint64_t data;\n+\t/* Word 3 */\n+\tunion dlb2_opaque_data u;\n+\tuint8_t qid;\n+\tuint8_t sched_type:2;\n+\tuint8_t priority:3;\n+\tuint8_t msg_type:3;\n+\t/* Word 4 */\n+\tuint16_t lock_id;\n+\tuint8_t meas_lat:1;\n+\tuint8_t rsvd1:2;\n+\tuint8_t no_dec:1;\n+\tuint8_t cmp_id:4;\n+\tunion {\n+\t\tuint8_t cmd_byte;\n+\t\tstruct {\n+\t\t\tuint8_t cq_token:1;\n+\t\t\tuint8_t qe_comp:1;\n+\t\t\tuint8_t qe_frag:1;\n+\t\t\tuint8_t qe_valid:1;\n+\t\t\tuint8_t rsvd3:1;\n+\t\t\tuint8_t error:1;\n+\t\t\tuint8_t rsvd:2;\n+\t\t};\n+\t};\n+};\n+\n+/* hw-specific format - do not change */\n+struct dlb2_cq_pop_qe {\n+\tuint64_t data;\n+\tunion dlb2_opaque_data u;\n+\tuint8_t qid;\n+\tuint8_t sched_type:2;\n+\tuint8_t priority:3;\n+\tuint8_t msg_type:3;\n+\tuint16_t tokens:10;\n+\tuint16_t rsvd2:6;\n+\tuint8_t meas_lat:1;\n+\tuint8_t rsvd1:2;\n+\tuint8_t no_dec:1;\n+\tuint8_t cmp_id:4;\n+\tunion {\n+\t\tuint8_t cmd_byte;\n+\t\tstruct {\n+\t\t\tuint8_t cq_token:1;\n+\t\t\tuint8_t qe_comp:1;\n+\t\t\tuint8_t qe_frag:1;\n+\t\t\tuint8_t qe_valid:1;\n+\t\t\tuint8_t rsvd3:1;\n+\t\t\tuint8_t error:1;\n+\t\t\tuint8_t rsvd:2;\n+\t\t};\n+\t};\n+};\n+\n+/* hw-specific format - do not change */\n+struct dlb2_dequeue_qe {\n+\tuint64_t data;\n+\tunion dlb2_opaque_data u;\n+\tuint8_t qid;\n+\tuint8_t sched_type:2;\n+\tuint8_t priority:3;\n+\tuint8_t msg_type:3;\n+\tuint16_t flow_id:16; /* was pp_id in v1 */\n+\tuint8_t debug;\n+\tuint8_t cq_gen:1;\n+\tuint8_t qid_depth:2; /* 2 bits in v2 */\n+\tuint8_t rsvd1:2;\n+\tuint8_t error:1;\n+\tuint8_t rsvd2:2;\n+};\n+\n+union dlb2_port_config {\n+\tstruct dlb2_create_ldb_port_args ldb;\n+\tstruct dlb2_create_dir_port_args dir;\n+};\n+\n+enum dlb2_port_state {\n+\tPORT_CLOSED,\n+\tPORT_STARTED,\n+\tPORT_STOPPED\n+};\n+\n+enum dlb2_configuration_state {\n+\t/* The resource has not been configured */\n+\tDLB2_NOT_CONFIGURED,\n+\t/* The resource was configured, but the device was stopped */\n+\tDLB2_PREV_CONFIGURED,\n+\t/* The resource is currently configured */\n+\tDLB2_CONFIGURED\n+};\n+\n+struct dlb2_port {\n+\tuint32_t id;\n+\tbool is_directed;\n+\tbool gen_bit;\n+\tuint16_t dir_credits;\n+\tuint32_t dequeue_depth;\n+\tunion dlb2_port_config cfg;\n+\tuint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */\n+\tuint16_t cached_ldb_credits;\n+\tuint16_t ldb_credits;\n+\tuint16_t cached_dir_credits;\n+\tbool int_armed;\n+\tuint16_t owed_tokens;\n+\tint16_t issued_releases;\n+\tint cq_depth;\n+\tuint16_t cq_idx;\n+\tuint16_t cq_idx_unmasked;\n+\tuint16_t cq_depth_mask;\n+\tuint16_t gen_bit_shift;\n+\tenum dlb2_port_state state;\n+\tenum dlb2_configuration_state config_state;\n+\tint num_mapped_qids;\n+\tuint8_t *qid_mappings;\n+\tstruct dlb2_enqueue_qe *qe4; /* Cache line's worth of QEs (4) */\n+\tstruct dlb2_enqueue_qe *int_arm_qe;\n+\tstruct dlb2_cq_pop_qe *consume_qe;\n+\tstruct dlb2_eventdev *dlb2; /* back ptr */\n+\tstruct dlb2_eventdev_port *ev_port; /* back ptr */\n+};\n+\n+/* Per-process per-port mmio and memory pointers */\n+struct process_local_port_data {\n+\tuint64_t *pp_addr;\n+\tstruct dlb2_dequeue_qe *cq_base;\n+\tconst struct rte_memzone *mz;\n+\tbool mmaped;\n+};\n+\n+struct dlb2_eventdev;\n+\n+struct dlb2_config {\n+\tint configured;\n+\tint reserved;\n+\tuint32_t num_ldb_credits;\n+\tuint32_t num_dir_credits;\n+\tstruct dlb2_create_sched_domain_args resources;\n+};\n+\n+enum dlb2_cos {\n+\tDLB2_COS_DEFAULT = -1,\n+\tDLB2_COS_0 = 0,\n+\tDLB2_COS_1,\n+\tDLB2_COS_2,\n+\tDLB2_COS_3\n+};\n+\n+struct dlb2_hw_dev {\n+\tstruct dlb2_config cfg;\n+\tstruct dlb2_hw_resource_info info;\n+\tvoid *pf_dev; /* opaque pointer to PF PMD dev (struct dlb2_dev) */\n+\tuint32_t domain_id;\n+\tenum dlb2_cos cos_id;\n+\trte_spinlock_t resource_lock; /* for MP support */\n+} __rte_cache_aligned;\n+\n+/* End HW related defines and structs */\n+\n+/* Begin DLB2 PMD Eventdev related defines and structs */\n+\n+#define DLB2_MAX_NUM_QUEUES \\\n+\t(DLB2_MAX_NUM_DIR_QUEUES + DLB2_MAX_NUM_LDB_QUEUES)\n+\n+#define DLB2_MAX_NUM_PORTS (DLB2_MAX_NUM_DIR_PORTS + DLB2_MAX_NUM_LDB_PORTS)\n+#define DLB2_MAX_INPUT_QUEUE_DEPTH 256\n+\n+/** Structure to hold the queue to port link establishment attributes */\n+\n+struct dlb2_event_queue_link {\n+\tuint8_t queue_id;\n+\tuint8_t priority;\n+\tbool mapped;\n+\tbool valid;\n+};\n+\n+struct dlb2_traffic_stats {\n+\tuint64_t rx_ok;\n+\tuint64_t rx_drop;\n+\tuint64_t rx_interrupt_wait;\n+\tuint64_t rx_umonitor_umwait;\n+\tuint64_t tx_ok;\n+\tuint64_t total_polls;\n+\tuint64_t zero_polls;\n+\tuint64_t tx_nospc_ldb_hw_credits;\n+\tuint64_t tx_nospc_dir_hw_credits;\n+\tuint64_t tx_nospc_inflight_max;\n+\tuint64_t tx_nospc_new_event_limit;\n+\tuint64_t tx_nospc_inflight_credits;\n+};\n+\n+/* DLB2 HW sets the 2bit qid_depth in rx QEs based on the programmable depth\n+ * threshold. The global default value in config/common_base (or rte_config.h)\n+ * can be overridden on a per-qid basis using a vdev command line parameter.\n+ * 3: depth > threshold\n+ * 2: threshold >= depth > 3/4 threshold\n+ * 1: 3/4 threshold >= depth > 1/2 threshold\n+ * 0: depth <= 1/2 threshold.\n+ */\n+#define DLB2_QID_DEPTH_LE50 0\n+#define DLB2_QID_DEPTH_GT50_LE75 1\n+#define DLB2_QID_DEPTH_GT75_LE100 2\n+#define DLB2_QID_DEPTH_GT100 3\n+#define DLB2_NUM_QID_DEPTH_STAT_VALS 4 /* 2 bits */\n+\n+struct dlb2_queue_stats {\n+\tuint64_t enq_ok;\n+\tuint64_t qid_depth[DLB2_NUM_QID_DEPTH_STAT_VALS];\n+};\n+\n+struct dlb2_port_stats {\n+\tstruct dlb2_traffic_stats traffic;\n+\tuint64_t tx_op_cnt[4]; /* indexed by rte_event.op */\n+\tuint64_t tx_implicit_rel;\n+\tuint64_t tx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];\n+\tuint64_t tx_invalid;\n+\tuint64_t rx_sched_cnt[DLB2_NUM_HW_SCHED_TYPES];\n+\tuint64_t rx_sched_invalid;\n+\tstruct dlb2_queue_stats queue[DLB2_MAX_NUM_QUEUES];\n+};\n+\n+struct dlb2_eventdev_port {\n+\tstruct dlb2_port qm_port; /* hw specific data structure */\n+\tstruct rte_event_port_conf conf; /* user-supplied configuration */\n+\tuint16_t inflight_credits; /* num credits this port has right now */\n+\tuint16_t credit_update_quanta;\n+\tstruct dlb2_eventdev *dlb2; /* backlink optimization */\n+\tstruct dlb2_port_stats stats __rte_cache_aligned;\n+\tstruct dlb2_event_queue_link link[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];\n+\tint num_links;\n+\tuint32_t id; /* port id */\n+\t/* num releases yet to be completed on this port.\n+\t * Only applies to load-balanced ports.\n+\t */\n+\tuint16_t outstanding_releases;\n+\tuint16_t inflight_max; /* app requested max inflights for this port */\n+\t/* setup_done is set when the event port is setup */\n+\tbool setup_done;\n+\t/* enq_configured is set when the qm port is created */\n+\tbool enq_configured;\n+\tuint8_t implicit_release; /* release events before dequeueing */\n+} __rte_cache_aligned;\n+\n+struct dlb2_queue {\n+\tuint32_t num_qid_inflights; /* User config */\n+\tuint32_t num_atm_inflights; /* User config */\n+\tenum dlb2_configuration_state config_state;\n+\tint sched_type; /* LB queue only */\n+\tuint32_t id;\n+\tbool is_directed;\n+};\n+\n+struct dlb2_eventdev_queue {\n+\tstruct dlb2_queue qm_queue;\n+\tstruct rte_event_queue_conf conf; /* User config */\n+\tint depth_threshold; /* use default if 0 */\n+\tuint32_t id;\n+\tbool setup_done;\n+\tuint8_t num_links;\n+};\n+\n+enum dlb2_run_state {\n+\tDLB2_RUN_STATE_STOPPED = 0,\n+\tDLB2_RUN_STATE_STOPPING,\n+\tDLB2_RUN_STATE_STARTING,\n+\tDLB2_RUN_STATE_STARTED\n+};\n+\n+struct dlb2_eventdev {\n+\tstruct dlb2_eventdev_port ev_ports[DLB2_MAX_NUM_PORTS];\n+\tstruct dlb2_eventdev_queue ev_queues[DLB2_MAX_NUM_QUEUES];\n+\tuint8_t qm_ldb_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];\n+\tuint8_t qm_dir_to_ev_queue_id[DLB2_MAX_NUM_QUEUES];\n+\t/* store num stats and offset of the stats for each queue */\n+\tuint16_t xstats_count_per_qid[DLB2_MAX_NUM_QUEUES];\n+\tuint16_t xstats_offset_for_qid[DLB2_MAX_NUM_QUEUES];\n+\t/* store num stats and offset of the stats for each port */\n+\tuint16_t xstats_count_per_port[DLB2_MAX_NUM_PORTS];\n+\tuint16_t xstats_offset_for_port[DLB2_MAX_NUM_PORTS];\n+\tstruct dlb2_get_num_resources_args hw_rsrc_query_results;\n+\tuint32_t xstats_count_mode_queue;\n+\tstruct dlb2_hw_dev qm_instance; /* strictly hw related */\n+\tuint64_t global_dequeue_wait_ticks;\n+\tstruct dlb2_xstats_entry *xstats;\n+\tstruct rte_eventdev *event_dev; /* backlink to dev */\n+\tuint32_t xstats_count_mode_dev;\n+\tuint32_t xstats_count_mode_port;\n+\tuint32_t xstats_count;\n+\tuint32_t inflights; /* use __atomic builtins */\n+\tuint32_t new_event_limit;\n+\tint max_num_events_override;\n+\tint num_dir_credits_override;\n+\tvolatile enum dlb2_run_state run_state;\n+\tuint16_t num_dir_queues; /* total num of evdev dir queues requested */\n+\tuint16_t num_dir_credits;\n+\tuint16_t num_ldb_credits;\n+\tuint16_t num_queues; /* total queues */\n+\tuint16_t num_ldb_queues; /* total num of evdev ldb queues requested */\n+\tuint16_t num_ports; /* total num of evdev ports requested */\n+\tuint16_t num_ldb_ports; /* total num of ldb ports requested */\n+\tuint16_t num_dir_ports; /* total num of dir ports requested */\n+\tbool umwait_allowed;\n+\tbool global_dequeue_wait; /* Not using per dequeue wait if true */\n+\tbool defer_sched;\n+\tenum dlb2_cq_poll_modes poll_mode;\n+\tuint8_t revision;\n+\tbool configured;\n+\tuint16_t max_ldb_credits;\n+\tuint16_t max_dir_credits;\n+\n+\t/* force hw credit pool counters into exclusive cache lines */\n+\n+\t/* use __atomic builtins */ /* shared hw cred */\n+\tuint32_t ldb_credit_pool __rte_cache_aligned;\n+\t/* use __atomic builtins */ /* shared hw cred */\n+\tuint32_t dir_credit_pool __rte_cache_aligned;\n+};\n+\n+/* used for collecting and passing around the dev args */\n+struct dlb2_qid_depth_thresholds {\n+\tint val[DLB2_MAX_NUM_QUEUES];\n+};\n+\n+struct dlb2_devargs {\n+\tint socket_id;\n+\tint max_num_events;\n+\tint num_dir_credits_override;\n+\tint dev_id;\n+\tint defer_sched;\n+\tstruct dlb2_qid_depth_thresholds qid_depth_thresholds;\n+\tenum dlb2_cos cos_id;\n+};\n+\n+/* End Eventdev related defines and structs */\n+\n+/* Forwards for non-inlined functions */\n+\n+void dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f);\n+\n+int dlb2_xstats_init(struct dlb2_eventdev *dlb2);\n+\n+void dlb2_xstats_uninit(struct dlb2_eventdev *dlb2);\n+\n+int dlb2_eventdev_xstats_get(const struct rte_eventdev *dev,\n+\t\tenum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\tconst unsigned int ids[], uint64_t values[], unsigned int n);\n+\n+int dlb2_eventdev_xstats_get_names(const struct rte_eventdev *dev,\n+\t\tenum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\tstruct rte_event_dev_xstats_name *xstat_names,\n+\t\tunsigned int *ids, unsigned int size);\n+\n+uint64_t dlb2_eventdev_xstats_get_by_name(const struct rte_eventdev *dev,\n+\t\t\t\t\t const char *name, unsigned int *id);\n+\n+int dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,\n+\t\tenum rte_event_dev_xstats_mode mode,\n+\t\tint16_t queue_port_id,\n+\t\tconst uint32_t ids[],\n+\t\tuint32_t nb_ids);\n+\n+int test_dlb2_eventdev(void);\n+\n+int dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t\tconst char *name,\n+\t\t\t\tstruct dlb2_devargs *dlb2_args);\n+\n+int dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,\n+\t\t\t\t const char *name);\n+\n+uint32_t dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,\n+\t\t\t struct dlb2_eventdev_queue *queue);\n+\n+int dlb2_parse_params(const char *params,\n+\t\t const char *name,\n+\t\t struct dlb2_devargs *dlb2_args);\n+\n+/* Extern globals */\n+extern struct process_local_port_data dlb2_port[][DLB2_NUM_PORT_TYPES];\n+\n+#endif\t/* _DLB2_PRIV_H_ */\n", "prefixes": [ "v3", "03/23" ] }