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GET /api/patches/81787/?format=api
{ "id": 81787, "url": "https://patches.dpdk.org/api/patches/81787/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603369447-28388-1-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603369447-28388-1-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603369447-28388-1-git-send-email-arybchenko@solarflare.com", "date": "2020-10-22T12:24:05", "name": "[1/3] common/sfc_efx: introduce 128-bit unsigned integer compat", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6ea7afb2148af20368bf5579fac71f6da9eb13a3", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603369447-28388-1-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 13214, "url": "https://patches.dpdk.org/api/series/13214/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13214", "date": "2020-10-22T12:24:06", "name": "[1/3] common/sfc_efx: introduce 128-bit unsigned integer compat", "version": 1, "mbox": "https://patches.dpdk.org/series/13214/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/81787/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/81787/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2015DA04DD;\n\tThu, 22 Oct 2020 14:24:53 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 940FDA9DE;\n\tThu, 22 Oct 2020 14:24:39 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 151C1A9D0\n for <dev@dpdk.org>; Thu, 22 Oct 2020 14:24:35 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.64])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 6D23860058 for <dev@dpdk.org>; Thu, 22 Oct 2020 12:24:33 +0000 (UTC)", "from us4-mdac16-57.ut7.mdlocal (unknown [10.7.66.28])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6BA902009B\n for <dev@dpdk.org>; Thu, 22 Oct 2020 12:24:33 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.174])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n E1EB622005A\n for <dev@dpdk.org>; Thu, 22 Oct 2020 12:24:32 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 97CB71C006C\n for <dev@dpdk.org>; Thu, 22 Oct 2020 12:24:32 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Thu, 22 Oct 2020 13:24:28 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 13:24:28 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09MCOS1r029638\n for <dev@dpdk.org>; Thu, 22 Oct 2020 13:24:28 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 85E4E1613A9\n for <dev@dpdk.org>; Thu, 22 Oct 2020 13:24:28 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Thu, 22 Oct 2020 13:24:05 +0100", "Message-ID": "<1603369447-28388-1-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25740.003", "X-TM-AS-Result": "No-2.693700-8.000000-10", "X-TMASE-MatchedRID": "1raMuI08qFAkliX1XDb78v3HILfxLV/92zgw5RT/BrZwkdIrVt8X1VDT\n Kayi2ZF67TB5f11dq/CS0G1KLf4rriHhSBQfglfsA9lly13c/gEs9Im7mOi/ZkdmDSBYfnJR1dW\n 4zIn6LEQRfYKA8Vd86IAy6p60ZV62fJ5/bZ6npdjGVuWouVipck7l+O/PfELscK2hp1tASaFjo5\n netu8UbU7a78OFV7U2jvYNl5oMTtSAtV8gOt8g9sYC1/CHK1Rp8sNzf98zgzs5niWVN5NzK0+9n\n KAUfbd9OiMMfiztpo/4XWZPvl2TZLAodBnVXNL5k0Q6cxt5OvU=", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--2.693700-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25740.003", "X-MDID": "1603369473-tfKesUTbPIGW", "X-PPE-DISP": "1603369473;tfKesUTbPIGW", "Subject": "[dpdk-dev] [PATCH 1/3] common/sfc_efx: introduce 128-bit unsigned\n\tinteger compat", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Intel SSE has __m128i, but ARMv8 has __uint128_t. So, add compat\nefsys_uint128_t to be used in driver source and have either __u128i\nor __uint128_t behind.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx_types.h | 8 ++++----\n drivers/common/sfc_efx/efsys.h | 19 ++++++++++---------\n 2 files changed, 14 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx_types.h b/drivers/common/sfc_efx/base/efx_types.h\nindex f7ec9a7..d67d07b 100644\n--- a/drivers/common/sfc_efx/base/efx_types.h\n+++ b/drivers/common/sfc_efx/base/efx_types.h\n@@ -221,8 +221,8 @@\n \tefx_word_t eo_word[8];\n \tefx_dword_t eo_dword[4];\n \tefx_qword_t eo_qword[2];\n-#if EFSYS_HAS_SSE2_M128\n-\t__m128i eo_u128[1];\n+#if EFSYS_HAS_UINT128\n+\tefsys_uint128_t eo_u128[1];\n #endif\n #if EFSYS_HAS_UINT64\n \tuint64_t eo_u64[2];\n@@ -243,8 +243,8 @@\n \tefx_dword_t ex_dword[8];\n \tefx_qword_t ex_qword[4];\n \tefx_oword_t ex_oword[2];\n-#if EFSYS_HAS_SSE2_M128\n-\t__m128i ex_u128[2];\n+#if EFSYS_HAS_UINT128\n+\tefsys_uint128_t ex_u128[2];\n #endif\n #if EFSYS_HAS_UINT64\n \tuint64_t ex_u64[4];\ndiff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h\nindex bbe9f2e..139f4d8 100644\n--- a/drivers/common/sfc_efx/efsys.h\n+++ b/drivers/common/sfc_efx/efsys.h\n@@ -39,7 +39,8 @@\n \n #define EFSYS_HAS_UINT64 1\n #define EFSYS_USE_UINT64 1\n-#define EFSYS_HAS_SSE2_M128 1\n+#define EFSYS_HAS_UINT128 1\n+typedef __m128i efsys_uint128_t;\n \n #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n #define EFSYS_IS_BIG_ENDIAN 1\n@@ -272,13 +273,13 @@\n #define EFSYS_MEM_READO(_esmp, _offset, _eop)\t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tvolatile uint8_t *_base = (_esmp)->esm_base;\t\t\\\n-\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\tvolatile efsys_uint128_t *_addr;\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n \t\tSFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,\t\\\n \t\t\t\t\t\tsizeof(efx_oword_t)));\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr = (volatile efsys_uint128_t *)(_base + (_offset));\\\n \t\t(_eop)->eo_u128[0] = _addr[0];\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\tEFSYS_PROBE5(mem_reado, unsigned int, (_offset),\t\\\n@@ -331,7 +332,7 @@\n #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop)\t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tvolatile uint8_t *_base = (_esmp)->esm_base;\t\t\\\n-\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\tvolatile efsys_uint128_t *_addr;\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n \t\tSFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,\t\\\n@@ -344,7 +345,7 @@\n \t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n \t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr = (volatile efsys_uint128_t *)(_base + (_offset));\\\n \t\t_addr[0] = (_eop)->eo_u128[0];\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n@@ -445,7 +446,7 @@\n #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock)\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tvolatile uint8_t *_base = (_esbp)->esb_base;\t\t\\\n-\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\tvolatile efsys_uint128_t *_addr;\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n \t\tSFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,\t\\\n@@ -455,7 +456,7 @@\n \t\tif (_lock)\t\t\t\t\t\t\\\n \t\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr = (volatile efsys_uint128_t *)(_base + (_offset));\\\n \t\trte_rmb();\t\t\t\t\t\t\\\n \t\t/* There is no rte_read128_relaxed() yet */\t\t\\\n \t\t(_eop)->eo_u128[0] = _addr[0];\t\t\t\t\\\n@@ -537,7 +538,7 @@\n #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock)\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tvolatile uint8_t *_base = (_esbp)->esb_base;\t\t\\\n-\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\tvolatile efsys_uint128_t *_addr;\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n \t\tSFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,\t\\\n@@ -553,7 +554,7 @@\n \t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n \t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr = (volatile efsys_uint128_t *)(_base + (_offset));\\\n \t\t/* There is no rte_write128_relaxed() yet */\t\t\\\n \t\t_addr[0] = (_eop)->eo_u128[0];\t\t\t\t\\\n \t\trte_wmb();\t\t\t\t\t\t\\\n", "prefixes": [ "1/3" ] }