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GET /api/patches/81535/?format=api
{ "id": 81535, "url": "https://patches.dpdk.org/api/patches/81535/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603185222-14831-17-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603185222-14831-17-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603185222-14831-17-git-send-email-arybchenko@solarflare.com", "date": "2020-10-20T09:12:56", "name": "[v2,16/62] common/sfc_efx/base: support setting a PPORT in a match spec", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b3efa1b14a85e4cc0f987ec7052887390464561e", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603185222-14831-17-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 13137, "url": "https://patches.dpdk.org/api/series/13137/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13137", "date": "2020-10-20T09:12:44", "name": "net/sfc: support flow API transfer rules", "version": 2, "mbox": "https://patches.dpdk.org/series/13137/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/81535/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/81535/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 776B7A04DD;\n\tTue, 20 Oct 2020 11:28:48 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2D101E25B;\n\tTue, 20 Oct 2020 11:14:57 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 2E2D8C806\n for <dev@dpdk.org>; Tue, 20 Oct 2020 11:14:11 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.60])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 7C66360075 for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:09 +0000 (UTC)", "from us4-mdac16-63.ut7.mdlocal (unknown [10.7.66.62])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 7B97B200A0\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:09 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.66.34])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n EEB351C004F\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:08 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n A4755600053\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:08 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 20 Oct 2020 10:13:59 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 10:13:59 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09K9Dx0f028377;\n Tue, 20 Oct 2020 10:13:59 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id AA2A31613A9;\n Tue, 20 Oct 2020 10:13:59 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Ivan Malov <ivan.malov@oktetlabs.ru>", "Date": "Tue, 20 Oct 2020 10:12:56 +0100", "Message-ID": "<1603185222-14831-17-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "References": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>\n <1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-TM-AS-Result": "No-0.594800-8.000000-10", "X-TMASE-MatchedRID": "BSJVbXLvFVBnbxlBLir0nMewkPVzkoGNYERxjzVaKh1wkdIrVt8X1VDT\n Kayi2ZF6pVG0HeSt+ryWGRCs++FM0t1RkEnBFAu+nFVnNmvv47vr3E41VlKsfXy/Hx1AgJrr3JM\n PHOsk+bidssHnNcMsHYQSjqSszbEGo1mG+FX/1/DMujzyu+W9gfngX/aL8PCNkY8eITaSJPhrcD\n qFw27ycG4nw1WMWtJw172j5rbqYvoVQ+fPl8Ti482CuVPkCNzua01mhnn7t6QELMPQNzyJSwHvY\n yr9Z+5lpX3VmKF8bKR2fWCrneqDG72Px8mW2XSIaFAKyqG5M2LiNs6hPZAKV5soi2XrUn/Jn6Kd\n MrRsL14qtq5d3cxkNQwWxr7XDKH8SaskcvCSHSCmtEij7nbzjaZ/NvLJaD4HNlbeyLzexm7hYGC\n dZ4ouMalHrHhe5Pl9NZnHadsmEs7HyLo5zqOExIDbjUmI9TWghdeYev6ImzWyrFieOBrhBjzcWr\n t/fwYrRcB2ZpPnVjJoZ1Aq3A7VZw==", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--0.594800-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-MDID": "1603185249-psZELMvgNxXK", "X-PPE-DISP": "1603185249;psZELMvgNxXK", "Subject": "[dpdk-dev] [PATCH v2 16/62] common/sfc_efx/base: support setting a\n\tPPORT in a match spec", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ivan Malov <ivan.malov@oktetlabs.ru>\n\nAdd an API for setting mask-value pairs in a match specification structure\nand add support for MAE field INGRESS_PORT of type PPORT.\n\nSigned-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx.h | 48 +++++\n drivers/common/sfc_efx/base/efx_mae.c | 170 ++++++++++++++++++\n .../sfc_efx/rte_common_sfc_efx_version.map | 3 +\n 3 files changed, 221 insertions(+)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h\nindex cd0b22d43a..4fb3b02aa8 100644\n--- a/drivers/common/sfc_efx/base/efx.h\n+++ b/drivers/common/sfc_efx/base/efx.h\n@@ -4081,9 +4081,57 @@ efx_mae_match_spec_fini(\n \t__in\t\t\t\tefx_mae_match_spec_t *spec);\n \n typedef enum efx_mae_field_id_e {\n+\tEFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,\n+\n \tEFX_MAE_FIELD_NIDS\n } efx_mae_field_id_t;\n \n+/* MPORT selector. Used to refer to MPORTs in match/action rules. */\n+typedef struct efx_mport_sel_s {\n+\tuint32_t sel;\n+} efx_mport_sel_t;\n+\n+/*\n+ * Get MPORT selector of a physical port.\n+ *\n+ * The resulting MPORT selector is opaque to the caller and can be\n+ * passed as an argument to efx_mae_match_spec_mport_set().\n+ */\n+LIBEFX_API\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_mport_by_phy_port(\n+\t__in\t\t\t\tuint32_t phy_port,\n+\t__out\t\t\t\tefx_mport_sel_t *mportp);\n+\n+/*\n+ * Fields which have BE postfix in their named constants are expected\n+ * to be passed by callers in big-endian byte order. They will appear\n+ * in the MCDI buffer, which is a part of the match specification, in\n+ * the very same byte order, that is, no conversion will be performed.\n+ *\n+ * Fields which don't have BE postfix in their named constants are in\n+ * host byte order. MCDI expects them to be little-endian, so the API\n+ * will take care to carry out conversion to little-endian byte order.\n+ * At the moment, the only field in host byte order is MPORT selector.\n+ */\n+LIBEFX_API\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_field_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tefx_mae_field_id_t field_id,\n+\t__in\t\t\t\tsize_t value_size,\n+\t__in_bcount(value_size)\t\tconst uint8_t *value,\n+\t__in\t\t\t\tsize_t mask_size,\n+\t__in_bcount(mask_size)\t\tconst uint8_t *mask);\n+\n+/* If the mask argument is NULL, the API will use full mask by default. */\n+LIBEFX_API\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_mport_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tconst efx_mport_sel_t *valuep,\n+\t__in_opt\t\t\tconst efx_mport_sel_t *maskp);\n+\n /*\n * Make sure that match fields known by EFX have proper masks set\n * in the match specification as per requirements of SF-122526-TC.\ndiff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c\nindex 81c586dfe8..4e6ae2227d 100644\n--- a/drivers/common/sfc_efx/base/efx_mae.c\n+++ b/drivers/common/sfc_efx/base/efx_mae.c\n@@ -282,6 +282,8 @@ efx_mae_match_spec_fini(\n \n /* Named identifiers which are valid indices to efx_mae_field_cap_t */\n typedef enum efx_mae_field_cap_id_e {\n+\tEFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,\n+\n \tEFX_MAE_FIELD_CAP_NIDS\n } efx_mae_field_cap_id_t;\n \n@@ -311,8 +313,176 @@ typedef struct efx_mae_mv_desc_s {\n \n /* Indices to this array are provided by efx_mae_field_id_t */\n static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {\n+#define\tEFX_MAE_MV_DESC(_name, _endianness)\t\t\t\t\\\n+\t[EFX_MAE_FIELD_##_name] =\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tEFX_MAE_FIELD_ID_##_name,\t\t\t\t\\\n+\t\tMAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,\t\t\\\n+\t\tMAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,\t\t\\\n+\t\tMAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,\t\t\\\n+\t\tMAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,\t\t\\\n+\t\t_endianness\t\t\t\t\t\t\\\n+\t}\n+\n+\tEFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),\n+\n+#undef EFX_MAE_MV_DESC\n };\n \n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_mport_by_phy_port(\n+\t__in\t\t\t\tuint32_t phy_port,\n+\t__out\t\t\t\tefx_mport_sel_t *mportp)\n+{\n+\tefx_dword_t dword;\n+\tefx_rc_t rc;\n+\n+\tif (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFX_POPULATE_DWORD_2(dword,\n+\t MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,\n+\t MAE_MPORT_SELECTOR_PPORT_ID, phy_port);\n+\n+\tmemset(mportp, 0, sizeof (*mportp));\n+\tmportp->sel = dword.ed_u32[0];\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_field_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tefx_mae_field_id_t field_id,\n+\t__in\t\t\t\tsize_t value_size,\n+\t__in_bcount(value_size)\t\tconst uint8_t *value,\n+\t__in\t\t\t\tsize_t mask_size,\n+\t__in_bcount(mask_size)\t\tconst uint8_t *mask)\n+{\n+\tconst efx_mae_mv_desc_t *descp;\n+\tuint8_t *mvp;\n+\tefx_rc_t rc;\n+\n+\tif (field_id >= EFX_MAE_FIELD_NIDS) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tswitch (spec->emms_type) {\n+\tcase EFX_MAE_RULE_ACTION:\n+\t\tdescp = &__efx_mae_action_rule_mv_desc_set[field_id];\n+\t\tmvp = spec->emms_mask_value_pairs.action;\n+\t\tbreak;\n+\tdefault:\n+\t\trc = ENOTSUP;\n+\t\tgoto fail2;\n+\t}\n+\n+\tif (value_size != descp->emmd_value_size) {\n+\t\trc = EINVAL;\n+\t\tgoto fail3;\n+\t}\n+\n+\tif (mask_size != descp->emmd_mask_size) {\n+\t\trc = EINVAL;\n+\t\tgoto fail4;\n+\t}\n+\n+\tif (descp->emmd_endianness == EFX_MAE_FIELD_BE) {\n+\t\t/*\n+\t\t * The mask/value are in network (big endian) order.\n+\t\t * The MCDI request field is also big endian.\n+\t\t */\n+\t\tmemcpy(mvp + descp->emmd_value_offset, value, value_size);\n+\t\tmemcpy(mvp + descp->emmd_mask_offset, mask, mask_size);\n+\t} else {\n+\t\tefx_dword_t dword;\n+\n+\t\t/*\n+\t\t * The mask/value are in host byte order.\n+\t\t * The MCDI request field is little endian.\n+\t\t */\n+\t\tswitch (value_size) {\n+\t\tcase 4:\n+\t\t\tEFX_POPULATE_DWORD_1(dword,\n+\t\t\t EFX_DWORD_0, *(const uint32_t *)value);\n+\n+\t\t\tmemcpy(mvp + descp->emmd_value_offset,\n+\t\t\t &dword, sizeof (dword));\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tEFSYS_ASSERT(B_FALSE);\n+\t\t}\n+\n+\t\tswitch (mask_size) {\n+\t\tcase 4:\n+\t\t\tEFX_POPULATE_DWORD_1(dword,\n+\t\t\t EFX_DWORD_0, *(const uint32_t *)mask);\n+\n+\t\t\tmemcpy(mvp + descp->emmd_mask_offset,\n+\t\t\t &dword, sizeof (dword));\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tEFSYS_ASSERT(B_FALSE);\n+\t\t}\n+\t}\n+\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_match_spec_mport_set(\n+\t__in\t\t\t\tefx_mae_match_spec_t *spec,\n+\t__in\t\t\t\tconst efx_mport_sel_t *valuep,\n+\t__in_opt\t\t\tconst efx_mport_sel_t *maskp)\n+{\n+\tuint32_t full_mask = UINT32_MAX;\n+\tconst uint8_t *vp;\n+\tconst uint8_t *mp;\n+\tefx_rc_t rc;\n+\n+\tif (valuep == NULL) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tvp = (const uint8_t *)&valuep->sel;\n+\tif (maskp != NULL)\n+\t\tmp = (const uint8_t *)&maskp->sel;\n+\telse\n+\t\tmp = (const uint8_t *)&full_mask;\n+\n+\trc = efx_mae_match_spec_field_set(spec,\n+\t EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,\n+\t sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);\n+\tif (rc != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n #define\tEFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)\t\t\\\n \t ((_mask)[(_bit) / (_mask_page_nbits)] &\t\t\t\\\n \t\t (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))\ndiff --git a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\nindex 8a4d2b2fff..86ed437e8d 100644\n--- a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n+++ b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n@@ -91,10 +91,13 @@ INTERNAL {\n \tefx_mae_fini;\n \tefx_mae_get_limits;\n \tefx_mae_init;\n+\tefx_mae_match_spec_field_set;\n \tefx_mae_match_spec_fini;\n \tefx_mae_match_spec_init;\n \tefx_mae_match_spec_is_valid;\n+\tefx_mae_match_spec_mport_set;\n \tefx_mae_match_specs_class_cmp;\n+\tefx_mae_mport_by_phy_port;\n \n \tefx_mcdi_fini;\n \tefx_mcdi_get_proxy_handle;\n", "prefixes": [ "v2", "16/62" ] }