Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/81517/?format=api
{ "id": 81517, "url": "https://patches.dpdk.org/api/patches/81517/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1603185222-14831-11-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603185222-14831-11-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603185222-14831-11-git-send-email-arybchenko@solarflare.com", "date": "2020-10-20T09:12:50", "name": "[v2,10/62] common/sfc_efx/base: add a match spec validate API", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "38dddf1666b07e8fd3c02b68fd9bb7818627b130", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1603185222-14831-11-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 13137, "url": "https://patches.dpdk.org/api/series/13137/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13137", "date": "2020-10-20T09:12:44", "name": "net/sfc: support flow API transfer rules", "version": 2, "mbox": "https://patches.dpdk.org/series/13137/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/81517/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/81517/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 01316A04DD;\n\tTue, 20 Oct 2020 11:22:22 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 06416BE39;\n\tTue, 20 Oct 2020 11:14:29 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id D3F51C7EC\n for <dev@dpdk.org>; Tue, 20 Oct 2020 11:14:07 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.61])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n A530560075 for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:07 +0000 (UTC)", "from us4-mdac16-49.ut7.mdlocal (unknown [10.7.66.16])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id A41DB8009E\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:07 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.66.41])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id C1DAC80056\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:06 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 62D624C0064\n for <dev@dpdk.org>; Tue, 20 Oct 2020 09:14:06 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Tue, 20 Oct 2020 10:13:59 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 10:13:59 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09K9DxZN028312;\n Tue, 20 Oct 2020 10:13:59 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 5B0E91613BE;\n Tue, 20 Oct 2020 10:13:59 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Ivan Malov <ivan.malov@oktetlabs.ru>", "Date": "Tue, 20 Oct 2020 10:12:50 +0100", "Message-ID": "<1603185222-14831-11-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "References": "<1603183709-23420-1-git-send-email-arybchenko@solarflare.com>\n <1603185222-14831-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-TM-AS-Result": "No-2.366400-8.000000-10", "X-TMASE-MatchedRID": "XrR3/qg0KnOB3AuymGAHRA9rVnOZ7Na2NV9S7O+u3KbEn6NODkzh6NAO\n OSAF0cTNJ4gUb5AkMXB1ssuldf62Xquhcc3IU+0WamOGWbsSIFcpWss5kPUFdHy/Hx1AgJrrwLd\n Z11vLmrV2u73/E7CHL0DTw9uN2GLZHVikQ9YmLLOInASnzB5VfFJAsn89ih94Bph69XjMbdn47X\n v617HbR53qDY7kD1WqNnxQQrlyFHBOJe7Iq9AgQv9XRIMLUOjQIPwiH5Xl/Q+o8aocg8ZmI124Y\n vC9/lw+C7dFQIvqCd+KGUoOUuWu8vmDLiOWM9q5CWlWR223da7YuVu0X/rOkHYJ8h0rMOWe9OlN\n 7uqXW49Pncvnf9/rJzvY+SL/TlWxsiLUMHgAKawmtTGirqG/D+BefETzWLKxOzrXChUtBARud6F\n XK/oTcEfivM8BUT0xvWvtbBh8hO2A1Eegw1mh2KchFrOB9kanIrMoP5XxqGeMLFaovouN0KPFjJ\n EFr+olwXCBO/GKkVqOhzOa6g8KrfkNIaNO51G9GH32/XuhRhcb0nM6g5itkCI2AAI3wPFC99qtH\n hwrlAsGv+LD0Oo6YOHYFq8ng2NUBDd0++DcHl795q0pW49U04XXmHr+iJs1sqxYnjga4QY83Fq7\n f38GK0XAdmaT51YybiPTBhvbLhaUTGVAhB5EbQ==", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--2.366400-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25736.003", "X-MDID": "1603185247-NR3kpysNMWut", "X-PPE-DISP": "1603185247;NR3kpysNMWut", "Subject": "[dpdk-dev] [PATCH v2 10/62] common/sfc_efx/base: add a match spec\n\tvalidate API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ivan Malov <ivan.malov@oktetlabs.ru>\n\nMAE has restrictions on what kind of mask a particular field can have in a\nmatch specification. Add an API for client drivers to check specifications.\n\nThe patch defines a field description list, whilst the list itself is\nleft empty. This is to provide a general idea of how field properties\nwill be used to validate a match specification. Particular fields\nwill be added to the list by follow-up patches.\n\nSigned-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx.h | 18 ++\n drivers/common/sfc_efx/base/efx_impl.h | 17 ++\n drivers/common/sfc_efx/base/efx_mae.c | 262 ++++++++++++++++++\n drivers/common/sfc_efx/base/efx_mcdi.h | 4 +\n .../sfc_efx/rte_common_sfc_efx_version.map | 1 +\n 5 files changed, 302 insertions(+)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h\nindex 40c5968ea9..094fad6367 100644\n--- a/drivers/common/sfc_efx/base/efx.h\n+++ b/drivers/common/sfc_efx/base/efx.h\n@@ -4080,6 +4080,24 @@ efx_mae_match_spec_fini(\n \t__in\t\t\t\tefx_nic_t *enp,\n \t__in\t\t\t\tefx_mae_match_spec_t *spec);\n \n+typedef enum efx_mae_field_id_e {\n+\tEFX_MAE_FIELD_NIDS\n+} efx_mae_field_id_t;\n+\n+/*\n+ * Make sure that match fields known by EFX have proper masks set\n+ * in the match specification as per requirements of SF-122526-TC.\n+ *\n+ * In the case efx_mae_field_id_t lacks named identifiers for any\n+ * fields which the FW maintains with support status MATCH_ALWAYS,\n+ * the validation result may not be accurate.\n+ */\n+LIBEFX_API\n+extern\t__checkReturn\t\t\tboolean_t\n+efx_mae_match_spec_is_valid(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tconst efx_mae_match_spec_t *spec);\n+\n #endif /* EFSYS_OPT_MAE */\n \n #ifdef\t__cplusplus\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex 931989f17a..2b872bb62e 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -782,8 +782,22 @@ typedef struct efx_proxy_ops_s {\n \n #if EFSYS_OPT_MAE\n \n+typedef struct efx_mae_field_cap_s {\n+\tuint32_t\t\t\temfc_support;\n+\tboolean_t\t\t\temfc_mask_affects_class;\n+\tboolean_t\t\t\temfc_match_affects_class;\n+} efx_mae_field_cap_t;\n+\n typedef struct efx_mae_s {\n \tuint32_t\t\t\tem_max_n_action_prios;\n+\t/*\n+\t * The number of MAE field IDs recognised by the FW implementation.\n+\t * Any field ID greater than or equal to this value is unsupported.\n+\t */\n+\tuint32_t\t\t\tem_max_nfields;\n+\t/** Action rule match field capabilities. */\n+\tefx_mae_field_cap_t\t\t*em_action_rule_field_caps;\n+\tsize_t\t\t\t\tem_action_rule_field_caps_size;\n } efx_mae_t;\n \n #endif /* EFSYS_OPT_MAE */\n@@ -1680,6 +1694,9 @@ efx_pci_xilinx_cap_tbl_find(\n struct efx_mae_match_spec_s {\n \tefx_mae_rule_type_t\t\temms_type;\n \tuint32_t\t\t\temms_prio;\n+\tunion emms_mask_value_pairs {\n+\t\tuint8_t\t\t\taction[MAE_FIELD_MASK_VALUE_PAIRS_LEN];\n+\t} emms_mask_value_pairs;\n };\n \n #endif /* EFSYS_OPT_MAE */\ndiff --git a/drivers/common/sfc_efx/base/efx_mae.c b/drivers/common/sfc_efx/base/efx_mae.c\nindex b1ebc93714..9e22c3d507 100644\n--- a/drivers/common/sfc_efx/base/efx_mae.c\n+++ b/drivers/common/sfc_efx/base/efx_mae.c\n@@ -42,8 +42,93 @@ efx_mae_get_capabilities(\n \tmaep->em_max_n_action_prios =\n \t MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);\n \n+\tmaep->em_max_nfields =\n+\t MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+static\t__checkReturn\t\t\tefx_rc_t\n+efx_mae_get_action_rule_caps(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tunsigned int field_ncaps,\n+\t__out_ecount(field_ncaps)\tefx_mae_field_cap_t *field_caps)\n+{\n+\tefx_mcdi_req_t req;\n+\tEFX_MCDI_DECLARE_BUF(payload,\n+\t MC_CMD_MAE_GET_AR_CAPS_IN_LEN,\n+\t MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);\n+\tunsigned int mcdi_field_ncaps;\n+\tunsigned int i;\n+\tefx_rc_t rc;\n+\n+\tif (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >\n+\t MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\treq.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);\n+\n+\tefx_mcdi_execute(enp, &req);\n+\n+\tif (req.emr_rc != 0) {\n+\t\trc = req.emr_rc;\n+\t\tgoto fail2;\n+\t}\n+\n+\tmcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);\n+\n+\tif (req.emr_out_length_used <\n+\t MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {\n+\t\trc = EMSGSIZE;\n+\t\tgoto fail3;\n+\t}\n+\n+\tif (mcdi_field_ncaps > field_ncaps) {\n+\t\trc = EMSGSIZE;\n+\t\tgoto fail4;\n+\t}\n+\n+\tfor (i = 0; i < mcdi_field_ncaps; ++i) {\n+\t\tuint32_t match_flag;\n+\t\tuint32_t mask_flag;\n+\n+\t\tfield_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,\n+\t\t MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,\n+\t\t MAE_FIELD_FLAGS_SUPPORT_STATUS);\n+\n+\t\tmatch_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,\n+\t\t MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,\n+\t\t MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);\n+\n+\t\tfield_caps[i].emfc_match_affects_class =\n+\t\t (match_flag != 0) ? B_TRUE : B_FALSE;\n+\n+\t\tmask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,\n+\t\t MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,\n+\t\t MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);\n+\n+\t\tfield_caps[i].emfc_mask_affects_class =\n+\t\t (mask_flag != 0) ? B_TRUE : B_FALSE;\n+\t}\n+\n \treturn (0);\n \n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n fail2:\n \tEFSYS_PROBE(fail2);\n fail1:\n@@ -56,6 +141,8 @@ efx_mae_init(\n \t__in\t\t\t\tefx_nic_t *enp)\n {\n \tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n+\tefx_mae_field_cap_t *ar_fcaps;\n+\tsize_t ar_fcaps_size;\n \tefx_mae_t *maep;\n \tefx_rc_t rc;\n \n@@ -76,8 +163,27 @@ efx_mae_init(\n \tif (rc != 0)\n \t\tgoto fail3;\n \n+\tar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);\n+\tEFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);\n+\tif (ar_fcaps == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail4;\n+\t}\n+\n+\tmaep->em_action_rule_field_caps_size = ar_fcaps_size;\n+\tmaep->em_action_rule_field_caps = ar_fcaps;\n+\n+\trc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);\n+\tif (rc != 0)\n+\t\tgoto fail5;\n+\n \treturn (0);\n \n+fail5:\n+\tEFSYS_PROBE(fail5);\n+\tEFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);\n+fail4:\n+\tEFSYS_PROBE(fail4);\n fail3:\n \tEFSYS_PROBE(fail3);\n \tEFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);\n@@ -99,6 +205,8 @@ efx_mae_fini(\n \tif (encp->enc_mae_supported == B_FALSE)\n \t\treturn;\n \n+\tEFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,\n+\t maep->em_action_rule_field_caps);\n \tEFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);\n \tenp->en_maep = NULL;\n }\n@@ -172,4 +280,158 @@ efx_mae_match_spec_fini(\n \tEFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);\n }\n \n+/* Named identifiers which are valid indices to efx_mae_field_cap_t */\n+typedef enum efx_mae_field_cap_id_e {\n+\tEFX_MAE_FIELD_CAP_NIDS\n+} efx_mae_field_cap_id_t;\n+\n+typedef enum efx_mae_field_endianness_e {\n+\tEFX_MAE_FIELD_LE = 0,\n+\tEFX_MAE_FIELD_BE,\n+\n+\tEFX_MAE_FIELD_ENDIANNESS_NTYPES\n+} efx_mae_field_endianness_t;\n+\n+/*\n+ * The following structure is a means to describe an MAE field.\n+ * The information in it is meant to be used internally by\n+ * APIs for addressing a given field in a mask-value pairs\n+ * structure and for validation purposes.\n+ */\n+typedef struct efx_mae_mv_desc_s {\n+\tefx_mae_field_cap_id_t\t\temmd_field_cap_id;\n+\n+\tsize_t\t\t\t\temmd_value_size;\n+\tsize_t\t\t\t\temmd_value_offset;\n+\tsize_t\t\t\t\temmd_mask_size;\n+\tsize_t\t\t\t\temmd_mask_offset;\n+\n+\tefx_mae_field_endianness_t\temmd_endianness;\n+} efx_mae_mv_desc_t;\n+\n+/* Indices to this array are provided by efx_mae_field_id_t */\n+static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {\n+};\n+\n+#define\tEFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)\t\t\\\n+\t ((_mask)[(_bit) / (_mask_page_nbits)] &\t\t\t\\\n+\t\t (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))\n+\n+static inline\t\t\t\tboolean_t\n+efx_mask_is_prefix(\n+\t__in\t\t\t\tsize_t mask_nbytes,\n+\t__in_bcount(mask_nbytes)\tconst uint8_t *maskp)\n+{\n+\tboolean_t prev_bit_is_set = B_TRUE;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < 8 * mask_nbytes; ++i) {\n+\t\tboolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);\n+\n+\t\tif (!prev_bit_is_set && bit_is_set)\n+\t\t\treturn B_FALSE;\n+\n+\t\tprev_bit_is_set = bit_is_set;\n+\t}\n+\n+\treturn B_TRUE;\n+}\n+\n+static inline\t\t\t\tboolean_t\n+efx_mask_is_all_ones(\n+\t__in\t\t\t\tsize_t mask_nbytes,\n+\t__in_bcount(mask_nbytes)\tconst uint8_t *maskp)\n+{\n+\tunsigned int i;\n+\tuint8_t t = ~0;\n+\n+\tfor (i = 0; i < mask_nbytes; ++i)\n+\t\tt &= maskp[i];\n+\n+\treturn (t == (uint8_t)(~0));\n+}\n+\n+static inline\t\t\t\tboolean_t\n+efx_mask_is_all_zeros(\n+\t__in\t\t\t\tsize_t mask_nbytes,\n+\t__in_bcount(mask_nbytes)\tconst uint8_t *maskp)\n+{\n+\tunsigned int i;\n+\tuint8_t t = 0;\n+\n+\tfor (i = 0; i < mask_nbytes; ++i)\n+\t\tt |= maskp[i];\n+\n+\treturn (t == 0);\n+}\n+\n+\t__checkReturn\t\t\tboolean_t\n+efx_mae_match_spec_is_valid(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tconst efx_mae_match_spec_t *spec)\n+{\n+\tefx_mae_t *maep = enp->en_maep;\n+\tunsigned int field_ncaps = maep->em_max_nfields;\n+\tconst efx_mae_field_cap_t *field_caps;\n+\tconst efx_mae_mv_desc_t *desc_setp;\n+\tunsigned int desc_set_nentries;\n+\tboolean_t is_valid = B_TRUE;\n+\tefx_mae_field_id_t field_id;\n+\tconst uint8_t *mvp;\n+\n+\tswitch (spec->emms_type) {\n+\tcase EFX_MAE_RULE_ACTION:\n+\t\tfield_caps = maep->em_action_rule_field_caps;\n+\t\tdesc_setp = __efx_mae_action_rule_mv_desc_set;\n+\t\tdesc_set_nentries =\n+\t\t EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);\n+\t\tmvp = spec->emms_mask_value_pairs.action;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn (B_FALSE);\n+\t}\n+\n+\tif (field_caps == NULL)\n+\t\treturn (B_FALSE);\n+\n+\tfor (field_id = 0; field_id < desc_set_nentries; ++field_id) {\n+\t\tconst efx_mae_mv_desc_t *descp = &desc_setp[field_id];\n+\t\tefx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;\n+\t\tconst uint8_t *m_buf = mvp + descp->emmd_mask_offset;\n+\t\tsize_t m_size = descp->emmd_mask_size;\n+\n+\t\tif (m_size == 0)\n+\t\t\tcontinue; /* Skip array gap */\n+\n+\t\tif (field_cap_id >= field_ncaps)\n+\t\t\tbreak;\n+\n+\t\tswitch (field_caps[field_cap_id].emfc_support) {\n+\t\tcase MAE_FIELD_SUPPORTED_MATCH_MASK:\n+\t\t\tis_valid = B_TRUE;\n+\t\t\tbreak;\n+\t\tcase MAE_FIELD_SUPPORTED_MATCH_PREFIX:\n+\t\t\tis_valid = efx_mask_is_prefix(m_size, m_buf);\n+\t\t\tbreak;\n+\t\tcase MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:\n+\t\t\tis_valid = (efx_mask_is_all_ones(m_size, m_buf) ||\n+\t\t\t efx_mask_is_all_zeros(m_size, m_buf));\n+\t\t\tbreak;\n+\t\tcase MAE_FIELD_SUPPORTED_MATCH_ALWAYS:\n+\t\t\tis_valid = efx_mask_is_all_ones(m_size, m_buf);\n+\t\t\tbreak;\n+\t\tcase MAE_FIELD_SUPPORTED_MATCH_NEVER:\n+\t\tcase MAE_FIELD_UNSUPPORTED:\n+\t\tdefault:\n+\t\t\tis_valid = efx_mask_is_all_zeros(m_size, m_buf);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (is_valid == B_FALSE)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn (is_valid);\n+}\n+\n #endif /* EFSYS_OPT_MAE */\ndiff --git a/drivers/common/sfc_efx/base/efx_mcdi.h b/drivers/common/sfc_efx/base/efx_mcdi.h\nindex 77a3d636e2..9dd0a23862 100644\n--- a/drivers/common/sfc_efx/base/efx_mcdi.h\n+++ b/drivers/common/sfc_efx/base/efx_mcdi.h\n@@ -421,6 +421,10 @@ efx_mcdi_phy_module_get_info(\n \tEFX_DWORD_FIELD(*MCDI_OUT2(_emr, efx_dword_t, _ofst),\t\t\\\n \t\t\tMC_CMD_ ## _field)\n \n+#define\tMCDI_OUT_INDEXED_DWORD_FIELD(_emr, _ofst, _idx, _field)\t\t\\\n+\tEFX_DWORD_FIELD(*(MCDI_OUT2(_emr, efx_dword_t, _ofst) +\t\t\\\n+\t\t\t(_idx)), _field)\n+\n #define\tMCDI_EV_FIELD(_eqp, _field)\t\t\t\t\t\\\n \tEFX_QWORD_FIELD(*_eqp, MCDI_EVENT_ ## _field)\n \ndiff --git a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\nindex 57a6c96b3e..0e6d44b6dc 100644\n--- a/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n+++ b/drivers/common/sfc_efx/rte_common_sfc_efx_version.map\n@@ -90,6 +90,7 @@ INTERNAL {\n \tefx_mae_init;\n \tefx_mae_match_spec_fini;\n \tefx_mae_match_spec_init;\n+\tefx_mae_match_spec_is_valid;\n \n \tefx_mcdi_fini;\n \tefx_mcdi_get_proxy_handle;\n", "prefixes": [ "v2", "10/62" ] }