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GET /api/patches/80874/?format=api
{ "id": 80874, "url": "https://patches.dpdk.org/api/patches/80874/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201015103814.253636-19-ciara.power@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201015103814.253636-19-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201015103814.253636-19-ciara.power@intel.com", "date": "2020-10-15T10:38:14", "name": "[v6,18/18] acl: add checks for max SIMD bitwidth", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "45834fee03373c108dd88b175b8d1638a62c96f6", "submitter": { "id": 978, "url": "https://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "https://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201015103814.253636-19-ciara.power@intel.com/mbox/", "series": [ { "id": 13000, "url": "https://patches.dpdk.org/api/series/13000/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13000", "date": "2020-10-15T10:37:56", "name": "add max SIMD bitwidth to EAL", "version": 6, "mbox": "https://patches.dpdk.org/series/13000/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/80874/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/80874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1BD9A04DB;\n\tThu, 15 Oct 2020 12:44:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CB17D1E4A5;\n\tThu, 15 Oct 2020 12:39:10 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id C00F91E497\n for <dev@dpdk.org>; Thu, 15 Oct 2020 12:39:05 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Oct 2020 03:39:05 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.239])\n by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:39:03 -0700" ], "IronPort-SDR": [ "\n 6SZHugyy7Hmo+kdAuwUVoXaKy6Yx5d91EcGKnlLU+G7AUgsF0eIWfnYsN1t2D6PqHQZKK/CWOM\n rhZj3bIlFwGQ==", "\n n+hO8bATkXrczSHu0PDX2EvUXEv1hTJ+X7xnBkUV8MX08aFuizu8WuW2sl3M1kIXhK4U4ukAVC\n w7d1y7ymGWAg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9774\"; a=\"227964303\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"227964303\"", "E=Sophos;i=\"5.77,378,1596524400\"; d=\"scan'208\";a=\"520728609\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com,\n drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, Ciara Power <ciara.power@intel.com>", "Date": "Thu, 15 Oct 2020 11:38:14 +0100", "Message-Id": "<20201015103814.253636-19-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20201015103814.253636-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20201015103814.253636-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v6 18/18] acl: add checks for max SIMD bitwidth", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath. These checks are added in the check alg helper functions.\n\nCc: Konstantin Ananyev <konstantin.ananyev@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\n lib/librte_acl/rte_acl.c | 27 +++++++++++++++++++++------\n 1 file changed, 21 insertions(+), 6 deletions(-)", "diff": "diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex 7c2f60b2d6..4ec6c982c9 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -16,6 +16,8 @@ static struct rte_tailq_elem rte_acl_tailq = {\n };\n EAL_REGISTER_TAILQ(rte_acl_tailq)\n \n+uint16_t max_simd_bitwidth;\n+\n #ifndef CC_AVX512_SUPPORT\n /*\n * If the compiler doesn't support AVX512 instructions,\n@@ -114,9 +116,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg)\n {\n \tif (alg == RTE_ACL_CLASSIFY_NEON) {\n #if defined(RTE_ARCH_ARM64)\n-\t\treturn 0;\n+\t\tif (max_simd_bitwidth >= RTE_SIMD_128)\n+\t\t\treturn 0;\n+\t\telse\n+\t\t\treturn -ENOTSUP;\n #elif defined(RTE_ARCH_ARM)\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) &&\n+\t\t\t\tmax_simd_bitwidth >= RTE_SIMD_128)\n \t\t\treturn 0;\n \t\treturn -ENOTSUP;\n #else\n@@ -136,7 +142,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n {\n \tif (alg == RTE_ACL_CLASSIFY_ALTIVEC) {\n #if defined(RTE_ARCH_PPC_64)\n-\t\treturn 0;\n+\t\tif (max_simd_bitwidth >= RTE_SIMD_128)\n+\t\t\treturn 0;\n+\t\telse\n+\t\t\treturn -ENOTSUP;\n #else\n \t\treturn -ENOTSUP;\n #endif\n@@ -158,7 +167,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&\n \t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&\n \t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&\n-\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW))\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) &&\n+\t\t\tmax_simd_bitwidth >= RTE_SIMD_512)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\n@@ -166,7 +176,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)\n \n \tif (alg == RTE_ACL_CLASSIFY_AVX2) {\n #ifdef CC_AVX2_SUPPORT\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&\n+\t\t\t\tmax_simd_bitwidth >= RTE_SIMD_256)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\n@@ -174,7 +185,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)\n \n \tif (alg == RTE_ACL_CLASSIFY_SSE) {\n #ifdef RTE_ARCH_X86\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) &&\n+\t\t\t\tmax_simd_bitwidth >= RTE_SIMD_128)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\n@@ -406,6 +418,9 @@ rte_acl_create(const struct rte_acl_param *param)\n \t\tTAILQ_INSERT_TAIL(acl_list, te, next);\n \t}\n \n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n+\n exit:\n \trte_mcfg_tailq_write_unlock();\n \treturn ctx;\n", "prefixes": [ "v6", "18/18" ] }