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GET /api/patches/79629/?format=api
{ "id": 79629, "url": "https://patches.dpdk.org/api/patches/79629/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-14-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005120910.189343-14-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-14-jiawenwu@trustnetic.com", "date": "2020-10-05T12:08:27", "name": "[v2,13/56] net/txgbe: add interrupt operation", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "97b1da507a9978890532c951bce39b98353b2682", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-14-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12690, "url": "https://patches.dpdk.org/api/series/12690/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12690", "date": "2020-10-05T12:08:14", "name": "net: txgbe PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/12690/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79629/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/79629/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE4EAA04B1;\n\tMon, 5 Oct 2020 14:13:32 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8BED41BB86;\n\tMon, 5 Oct 2020 14:09:08 +0200 (CEST)", "from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142])\n by dpdk.org (Postfix) with ESMTP id 7AA111BA83\n for <dev@dpdk.org>; Mon, 5 Oct 2020 14:09:00 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 05 Oct 2020 20:08:55 +0800 (CST)" ], "X-QQ-mid": "bizesmtp9t1601899736t339ep8u4", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "lMMvwf47cmgxHk/NFKOE7IhXEy10N/+1+XzNOBLTT+QJDMQY2//DRJFDMGKPy\n 68LtkIF3g5pb0gplNX+U6ye4hJVQyce0FWzeDYH2+4uDNZAGEIG8asJ97YJnPZkgpc75RrS\n x+32xynLFQV0cYv96rHjhBoqJ/PZ8hA7EfRUamj3nOW6e9XV3k1LpdYH3NjE3xcyKqIz5QQ\n zEbb8BCq+AGfO4nXywaguZPE0S3X6glondwWe0DRRpF1wjN7rgTb0NUXtuFxN5ZDJuzDxsu\n sj9fKo071R71dEjW/AOy/0xngLcS84kCOrTS31cJ5hoktWIk8pfuaNS2BXcV8X+fo/DTlCs\n OE+ACVlVsFMw/mYuV77ooiHtLOnXA==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "jiawenwu <jiawenwu@trustnetic.com>", "Date": "Mon, 5 Oct 2020 20:08:27 +0800", "Message-Id": "<20201005120910.189343-14-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 13/56] net/txgbe: add interrupt operation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd device interrupt handler and setup misx interrupt.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 2 +\n doc/guides/nics/txgbe.rst | 5 +\n drivers/net/txgbe/base/txgbe_type.h | 8 +\n drivers/net/txgbe/txgbe_ethdev.c | 466 ++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_ethdev.h | 30 ++\n 5 files changed, 511 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 2fc202c3a..d7c3bbfb6 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -5,6 +5,8 @@\n ;\n [Features]\n Speed capabilities = Y\n+Link status = Y\n+Link status event = Y\n Linux UIO = Y\n Linux VFIO = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst\nindex e3b9f1858..994ea0583 100644\n--- a/doc/guides/nics/txgbe.rst\n+++ b/doc/guides/nics/txgbe.rst\n@@ -7,6 +7,11 @@ TXGBE Poll Mode Driver\n The TXGBE PMD (librte_pmd_txgbe) provides poll mode driver support\n for Wangxun 10 Gigabit Ethernet NICs.\n \n+Features\n+--------\n+\n+- Link state information\n+\n Prerequisites\n -------------\n \ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex c0bf7cc23..499603c61 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -382,6 +382,14 @@ struct txgbe_mbx_info {\n \ts32 (*check_for_rst)(struct txgbe_hw *, u16);\n };\n \n+enum txgbe_isb_idx {\n+\tTXGBE_ISB_HEADER,\n+\tTXGBE_ISB_MISC,\n+\tTXGBE_ISB_VEC0,\n+\tTXGBE_ISB_VEC1,\n+\tTXGBE_ISB_MAX\n+};\n+\n struct txgbe_hw {\n \tvoid IOMEM *hw_addr;\n \tvoid *back;\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 7ad1eae2a..ea184316d 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -8,8 +8,12 @@\n #include <string.h>\n #include <rte_common.h>\n #include <rte_ethdev_pci.h>\n+\n+#include <rte_interrupts.h>\n #include <rte_pci.h>\n #include <rte_memory.h>\n+#include <rte_eal.h>\n+#include <rte_alarm.h>\n \n #include \"txgbe_logs.h\"\n #include \"base/txgbe.h\"\n@@ -18,6 +22,17 @@\n \n static void txgbe_dev_close(struct rte_eth_dev *dev);\n \n+static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);\n+static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);\n+static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);\n+static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);\n+static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);\n+static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_intr_handle *handle);\n+static void txgbe_dev_interrupt_handler(void *param);\n+static void txgbe_dev_interrupt_delayed_handler(void *param);\n+static void txgbe_configure_msix(struct rte_eth_dev *dev);\n+\n /*\n * The set of PCI devices this driver supports\n */\n@@ -59,6 +74,29 @@ txgbe_is_sfp(struct txgbe_hw *hw)\n \t}\n }\n \n+static inline void\n+txgbe_enable_intr(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\n+\twr32(hw, TXGBE_IENMISC, intr->mask_misc);\n+\twr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);\n+\twr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);\n+\ttxgbe_flush(hw);\n+}\n+\n+static void\n+txgbe_disable_intr(struct txgbe_hw *hw)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\twr32(hw, TXGBE_IENMISC, ~BIT_MASK32);\n+\twr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);\n+\twr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);\n+\ttxgbe_flush(hw);\n+}\n+\n static int\n eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n {\n@@ -144,6 +182,9 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \t\treturn -EIO;\n \t}\n \n+\t/* disable interrupt */\n+\ttxgbe_disable_intr(hw);\n+\n \t/* Allocate memory for storing MAC addresses */\n \teth_dev->data->mac_addrs = rte_zmalloc(\"txgbe\", RTE_ETHER_ADDR_LEN *\n \t\t\t\t\t hw->mac.num_rar_entries, 0);\n@@ -186,9 +227,15 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)\n \t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n \t\t pci_dev->id.device_id);\n \n+\trte_intr_callback_register(intr_handle,\n+\t\t\t\t txgbe_dev_interrupt_handler, eth_dev);\n+\n \t/* enable uio/vfio intr/eventfd mapping */\n \trte_intr_enable(intr_handle);\n \n+\t/* enable support intr */\n+\ttxgbe_enable_intr(eth_dev);\n+\n \treturn 0;\n }\n \n@@ -255,6 +302,20 @@ static struct rte_pci_driver rte_txgbe_pmd = {\n \t.remove = eth_txgbe_pci_remove,\n };\n \n+\n+static void\n+txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\tuint32_t gpie;\n+\n+\tgpie = rd32(hw, TXGBE_GPIOINTEN);\n+\tgpie |= TXGBE_GPIOBIT_6;\n+\twr32(hw, TXGBE_GPIOINTEN, gpie);\n+\tintr->mask_misc |= TXGBE_ICRMISC_GPIO;\n+}\n+\n /*\n * Reset and stop device.\n */\n@@ -263,6 +324,8 @@ txgbe_dev_close(struct rte_eth_dev *dev)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint retries = 0;\n+\tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -271,6 +334,22 @@ txgbe_dev_close(struct rte_eth_dev *dev)\n \t/* disable uio intr before callback unregister */\n \trte_intr_disable(intr_handle);\n \n+\tdo {\n+\t\tret = rte_intr_callback_unregister(intr_handle,\n+\t\t\t\ttxgbe_dev_interrupt_handler, dev);\n+\t\tif (ret >= 0 || ret == -ENOENT) {\n+\t\t\tbreak;\n+\t\t} else if (ret != -EAGAIN) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"intr callback unregister failed: %d\",\n+\t\t\t\tret);\n+\t\t}\n+\t\trte_delay_ms(100);\n+\t} while (retries++ < (10 + TXGBE_LINK_UP_TIME));\n+\n+\t/* cancel the delay handler before remove dev */\n+\trte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);\n+\n \trte_free(dev->data->mac_addrs);\n \tdev->data->mac_addrs = NULL;\n \n@@ -341,6 +420,393 @@ txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \treturn 0;\n }\n \n+static int\n+txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(wait_to_complete);\n+\treturn 0;\n+}\n+\n+/**\n+ * It clears the interrupt causes and enables the interrupt.\n+ * It will be called once only during nic initialized.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ * @param on\n+ * Enable or Disable.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)\n+{\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\n+\ttxgbe_dev_link_status_print(dev);\n+\tif (on)\n+\t\tintr->mask_misc |= TXGBE_ICRMISC_LSC;\n+\telse\n+\t\tintr->mask_misc &= ~TXGBE_ICRMISC_LSC;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * It clears the interrupt causes and enables the interrupt.\n+ * It will be called once only during nic initialized.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\n+\tintr->mask[0] |= TXGBE_ICR_MASK;\n+\tintr->mask[1] |= TXGBE_ICR_MASK;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * It clears the interrupt causes and enables the interrupt.\n+ * It will be called once only during nic initialized.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\n+\tintr->mask_misc |= TXGBE_ICRMISC_LNKSEC;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)\n+{\n+\tuint32_t eicr;\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\n+\t/* clear all cause mask */\n+\ttxgbe_disable_intr(hw);\n+\n+\t/* read-on-clear nic registers here */\n+\teicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];\n+\tPMD_DRV_LOG(DEBUG, \"eicr %x\", eicr);\n+\n+\tintr->flags = 0;\n+\n+\t/* set flag for async link update */\n+\tif (eicr & TXGBE_ICRMISC_LSC)\n+\t\tintr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;\n+\n+\tif (eicr & TXGBE_ICRMISC_VFMBX)\n+\t\tintr->flags |= TXGBE_FLAG_MAILBOX;\n+\n+\tif (eicr & TXGBE_ICRMISC_LNKSEC)\n+\t\tintr->flags |= TXGBE_FLAG_MACSEC;\n+\n+\tif (eicr & TXGBE_ICRMISC_GPIO)\n+\t\tintr->flags |= TXGBE_FLAG_PHY_INTERRUPT;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * It gets and then prints the link status.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static void\n+txgbe_dev_link_status_print(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_eth_link link;\n+\n+\trte_eth_linkstatus_get(dev, &link);\n+\n+\tif (link.link_status) {\n+\t\tPMD_INIT_LOG(INFO, \"Port %d: Link Up - speed %u Mbps - %s\",\n+\t\t\t\t\t(int)(dev->data->port_id),\n+\t\t\t\t\t(unsigned)link.link_speed,\n+\t\t\tlink.link_duplex == ETH_LINK_FULL_DUPLEX ?\n+\t\t\t\t\t\"full-duplex\" : \"half-duplex\");\n+\t} else {\n+\t\tPMD_INIT_LOG(INFO, \" Port %d: Link Down\",\n+\t\t\t\t(int)(dev->data->port_id));\n+\t}\n+\tPMD_INIT_LOG(DEBUG, \"PCI Address: \" PCI_PRI_FMT,\n+\t\t\t\tpci_dev->addr.domain,\n+\t\t\t\tpci_dev->addr.bus,\n+\t\t\t\tpci_dev->addr.devid,\n+\t\t\t\tpci_dev->addr.function);\n+}\n+\n+/*\n+ * It executes link_update after knowing an interrupt occurred.\n+ *\n+ * @param dev\n+ * Pointer to struct rte_eth_dev.\n+ *\n+ * @return\n+ * - On success, zero.\n+ * - On failure, a negative value.\n+ */\n+static int\n+txgbe_dev_interrupt_action(struct rte_eth_dev *dev,\n+\t\t\t struct rte_intr_handle *intr_handle)\n+{\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\tint64_t timeout;\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\n+\tPMD_DRV_LOG(DEBUG, \"intr action type %d\", intr->flags);\n+\n+\tif (intr->flags & TXGBE_FLAG_MAILBOX) {\n+\t\tintr->flags &= ~TXGBE_FLAG_MAILBOX;\n+\t}\n+\n+\tif (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {\n+\t\thw->phy.handle_lasi(hw);\n+\t\tintr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;\n+\t}\n+\n+\tif (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {\n+\t\tstruct rte_eth_link link;\n+\n+\t\t/* get the link status before link update, for predicting later */\n+\t\trte_eth_linkstatus_get(dev, &link);\n+\n+\t\ttxgbe_dev_link_update(dev, 0);\n+\n+\t\t/* likely to up */\n+\t\tif (!link.link_status)\n+\t\t\t/* handle it 1 sec later, wait it being stable */\n+\t\t\ttimeout = TXGBE_LINK_UP_CHECK_TIMEOUT;\n+\t\t/* likely to down */\n+\t\telse\n+\t\t\t/* handle it 4 sec later, wait it being stable */\n+\t\t\ttimeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;\n+\n+\t\ttxgbe_dev_link_status_print(dev);\n+\t\tif (rte_eal_alarm_set(timeout * 1000,\n+\t\t\t\t txgbe_dev_interrupt_delayed_handler,\n+\t\t\t\t (void *)dev) < 0)\n+\t\t\tPMD_DRV_LOG(ERR, \"Error setting alarm\");\n+\t\telse {\n+\t\t\t/* remember original mask */\n+\t\t\tintr->mask_misc_orig = intr->mask_misc;\n+\t\t\t/* only disable lsc interrupt */\n+\t\t\tintr->mask_misc &= ~TXGBE_ICRMISC_LSC;\n+\t\t}\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"enable intr immediately\");\n+\ttxgbe_enable_intr(dev);\n+\trte_intr_enable(intr_handle);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Interrupt handler which shall be registered for alarm callback for delayed\n+ * handling specific interrupt to wait for the stable nic state. As the\n+ * NIC interrupt state is not stable for txgbe after link is just down,\n+ * it needs to wait 4 seconds to get the stable status.\n+ *\n+ * @param handle\n+ * Pointer to interrupt handle.\n+ * @param param\n+ * The address of parameter (struct rte_eth_dev *) regsitered before.\n+ *\n+ * @return\n+ * void\n+ */\n+static void\n+txgbe_dev_interrupt_delayed_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tstruct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t eicr;\n+\n+\ttxgbe_disable_intr(hw);\n+\n+\teicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];\n+\n+\tif (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {\n+\t\thw->phy.handle_lasi(hw);\n+\t\tintr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;\n+\t}\n+\n+\tif (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {\n+\t\ttxgbe_dev_link_update(dev, 0);\n+\t\tintr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;\n+\t\ttxgbe_dev_link_status_print(dev);\n+\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,\n+\t\t\t\t\t NULL);\n+\t}\n+\n+\tif (intr->flags & TXGBE_FLAG_MACSEC) {\n+\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,\n+\t\t\t\t\t NULL);\n+\t\tintr->flags &= ~TXGBE_FLAG_MACSEC;\n+\t}\n+\n+\t/* restore original mask */\n+\tintr->mask_misc = intr->mask_misc_orig;\n+\tintr->mask_misc_orig = 0;\n+\n+\tPMD_DRV_LOG(DEBUG, \"enable intr in delayed handler S[%08x]\", eicr);\n+\ttxgbe_enable_intr(dev);\n+\trte_intr_enable(intr_handle);\n+}\n+\n+/**\n+ * Interrupt handler triggered by NIC for handling\n+ * specific interrupt.\n+ *\n+ * @param handle\n+ * Pointer to interrupt handle.\n+ * @param param\n+ * The address of parameter (struct rte_eth_dev *) regsitered before.\n+ *\n+ * @return\n+ * void\n+ */\n+static void\n+txgbe_dev_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\n+\ttxgbe_dev_interrupt_get_status(dev);\n+\ttxgbe_dev_interrupt_action(dev, dev->intr_handle);\n+}\n+\n+/**\n+ * set the IVAR registers, mapping interrupt causes to vectors\n+ * @param hw\n+ * pointer to txgbe_hw struct\n+ * @direction\n+ * 0 for Rx, 1 for Tx, -1 for other causes\n+ * @queue\n+ * queue to map the corresponding interrupt to\n+ * @msix_vector\n+ * the vector to map to the corresponding queue\n+ */\n+void\n+txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,\n+\t\t uint8_t queue, uint8_t msix_vector)\n+{\n+\tuint32_t tmp, idx;\n+\n+\tif (direction == -1) {\n+\t\t/* other causes */\n+\t\tmsix_vector |= TXGBE_IVARMISC_VLD;\n+\t\tidx = 0;\n+\t\ttmp = rd32(hw, TXGBE_IVARMISC);\n+\t\ttmp &= ~(0xFF << idx);\n+\t\ttmp |= (msix_vector << idx);\n+\t\twr32(hw, TXGBE_IVARMISC, tmp);\n+\t} else {\n+\t\t/* rx or tx causes */\n+\t\t/* Workround for ICR lost */\n+\t\tidx = ((16 * (queue & 1)) + (8 * direction));\n+\t\ttmp = rd32(hw, TXGBE_IVAR(queue >> 1));\n+\t\ttmp &= ~(0xFF << idx);\n+\t\ttmp |= (msix_vector << idx);\n+\t\twr32(hw, TXGBE_IVAR(queue >> 1), tmp);\n+\t}\n+}\n+\n+/**\n+ * Sets up the hardware to properly generate MSI-X interrupts\n+ * @hw\n+ * board private structure\n+ */\n+static void\n+txgbe_configure_msix(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t queue_id, base = TXGBE_MISC_VEC_ID;\n+\tuint32_t vec = TXGBE_MISC_VEC_ID;\n+\tuint32_t gpie;\n+\n+\t/* won't configure msix register if no mapping is done\n+\t * between intr vector and event fd\n+\t * but if misx has been enabled already, need to configure\n+\t * auto clean, auto mask and throttling.\n+\t */\n+\tgpie = rd32(hw, TXGBE_GPIE);\n+\tif (!rte_intr_dp_is_en(intr_handle) &&\n+\t !(gpie & TXGBE_GPIE_MSIX))\n+\t\treturn;\n+\n+\tif (rte_intr_allow_others(intr_handle))\n+\t\tvec = base = TXGBE_RX_VEC_START;\n+\n+\t/* setup GPIE for MSI-x mode */\n+\tgpie = rd32(hw, TXGBE_GPIE);\n+\tgpie |= TXGBE_GPIE_MSIX;\n+\twr32(hw, TXGBE_GPIE, gpie);\n+\n+\t/* Populate the IVAR table and set the ITR values to the\n+\t * corresponding register.\n+\t */\n+\tif (rte_intr_dp_is_en(intr_handle)) {\n+\t\tfor (queue_id = 0; queue_id < dev->data->nb_rx_queues;\n+\t\t\tqueue_id++) {\n+\t\t\t/* by default, 1:1 mapping */\n+\t\t\ttxgbe_set_ivar_map(hw, 0, queue_id, vec);\n+\t\t\tintr_handle->intr_vec[queue_id] = vec;\n+\t\t\tif (vec < base + intr_handle->nb_efd - 1)\n+\t\t\t\tvec++;\n+\t\t}\n+\n+\t\ttxgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);\n+\t}\n+\twr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),\n+\t\t\tTXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)\n+\t\t\t| TXGBE_ITR_WRDSA);\n+}\n+\n static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.dev_infos_get = txgbe_dev_info_get,\n };\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex c81528295..2c13da38f 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -7,12 +7,21 @@\n \n #include \"base/txgbe.h\"\n \n+/* need update link, bit flag */\n+#define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n+#define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)\n+#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)\n+#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)\n+#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)\n+\n /*\n * Defines that were not part of txgbe_type.h as they are not used by the\n * FreeBSD driver.\n */\n #define TXGBE_HKEY_MAX_INDEX 10\n \n+#define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT\t500 /* 500us */\n+\n #define TXGBE_RSS_OFFLOAD_ALL ( \\\n \tETH_RSS_IPV4 | \\\n \tETH_RSS_NONFRAG_IPV4_TCP | \\\n@@ -24,16 +33,37 @@\n \tETH_RSS_IPV6_TCP_EX | \\\n \tETH_RSS_IPV6_UDP_EX)\n \n+#define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET\n+#define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET\n+\n+/* structure for interrupt relative data */\n+struct txgbe_interrupt {\n+\tuint32_t flags;\n+\tuint32_t mask_misc;\n+\t/* to save original mask during delayed handler */\n+\tuint32_t mask_misc_orig;\n+\tuint32_t mask[2];\n+};\n+\n /*\n * Structure to store private data for each driver instance (for each port).\n */\n struct txgbe_adapter {\n \tstruct txgbe_hw hw;\n+\tstruct txgbe_interrupt intr;\n };\n \n #define TXGBE_DEV_HW(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)\n \n+#define TXGBE_DEV_INTR(dev) \\\n+\t(&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)\n+\n+void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,\n+\t\t\t uint8_t queue, uint8_t msix_vector);\n+\n+#define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */\n+#define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */\n #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */\n \n /*\n", "prefixes": [ "v2", "13/56" ] }