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GET /api/patches/79620/?format=api
{ "id": 79620, "url": "https://patches.dpdk.org/api/patches/79620/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-5-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005120910.189343-5-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-5-jiawenwu@trustnetic.com", "date": "2020-10-05T12:08:18", "name": "[v2,04/56] net/txgbe: add error types and registers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9b97073a134405a53e93d8236a55d43220d49d1b", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-5-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12690, "url": "https://patches.dpdk.org/api/series/12690/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12690", "date": "2020-10-05T12:08:14", "name": "net: txgbe PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/12690/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79620/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/79620/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A52ACA04B1;\n\tMon, 5 Oct 2020 14:09:46 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 859981B7FA;\n\tMon, 5 Oct 2020 14:08:51 +0200 (CEST)", "from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130])\n by dpdk.org (Postfix) with ESMTP id 7F6171B737\n for <dev@dpdk.org>; Mon, 5 Oct 2020 14:08:47 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 05 Oct 2020 20:08:41 +0800 (CST)" ], "X-QQ-mid": "bizesmtp9t1601899722tibrram5q", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "uPKj8ga2w7EQ5aGgx8cfflW7MDb807yRq6DxNMwTZ766j6l/eh1ZOtZOOlE+h\n KB+Z9spbj16zhS/b42iEXZbbyaMzpx5W8GLNF0//behCTdxeluiHaOVw2A9VEt12q3LNxnL\n 9FCZlkqVJP8M1mhmOakLE7tgrdEqOBRCiwTUQTP4Eso/jFfJfmvVavuz4LI34KI8VtEP47H\n BIWSq1aAk8eIla8CGyq3ejSomI1ynE0TuufdVsFbWW2HQsfuS25wImSukl7gJmHmvzPavI/\n 2jc463GrjLVID2LvLIOKJjbtNqOiF0p7etkxsAweYG4q26yW/TYxaJNCECCHlKMf1o88Nh3\n 1Xk8L4S", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "jiawenwu <jiawenwu@trustnetic.com>", "Date": "Mon, 5 Oct 2020 20:08:18 +0800", "Message-Id": "<20201005120910.189343-5-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 04/56] net/txgbe: add error types and registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd error types and registers.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_regs.h | 1890 +++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_status.h | 122 ++\n 2 files changed, 2012 insertions(+)\n create mode 100644 drivers/net/txgbe/base/txgbe_regs.h\n create mode 100644 drivers/net/txgbe/base/txgbe_status.h", "diff": "diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h\nnew file mode 100644\nindex 000000000..703d4f990\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_regs.h\n@@ -0,0 +1,1890 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#ifndef _TXGBE_REGS_H_\n+#define _TXGBE_REGS_H_\n+\n+#define TXGBE_PVMBX_QSIZE (16) /* 16*4B */\n+#define TXGBE_PVMBX_BSIZE (TXGBE_PVMBX_QSIZE * 4)\n+\n+#define TXGBE_REMOVED(a) (0)\n+\n+#define TXGBE_REG_DUMMY 0xFFFFFF\n+\n+#define MS8(shift, mask) (((u8)(mask)) << (shift))\n+#define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift))\n+#define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask))\n+\n+#define MS16(shift, mask) (((u16)(mask)) << (shift))\n+#define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift))\n+#define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask))\n+\n+#define MS32(shift, mask) (((u32)(mask)) << (shift))\n+#define LS32(val, shift, mask) (((u32)(val) & (u32)(mask)) << (shift))\n+#define RS32(reg, shift, mask) (((u32)(reg) >> (shift)) & (u32)(mask))\n+\n+#define MS64(shift, mask) (((u64)(mask)) << (shift))\n+#define LS64(val, shift, mask) (((u64)(val) & (u64)(mask)) << (shift))\n+#define RS64(reg, shift, mask) (((u64)(reg) >> (shift)) & (u64)(mask))\n+\n+#define MS(shift, mask) MS32(shift, mask)\n+#define LS(val, shift, mask) LS32(val, shift, mask)\n+#define RS(reg, shift, mask) RS32(reg, shift, mask)\n+\n+#define ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y))\n+#define ROUND_DOWN(x, y) ((x) / (y) * (y))\n+#define ROUND_OVER(x, maxbits, unitbits) \\\n+\t((x) >= 1 << (maxbits) ? 0 : (x) >> (unitbits))\n+\n+/* autoc bits definition */\n+#define TXGBE_AUTOC TXGBE_REG_DUMMY\n+#define TXGBE_AUTOC_FLU MS64(0, 0x1)\n+#define TXGBE_AUTOC_10G_PMA_PMD_MASK MS64(7, 0x3) /* parallel */\n+#define TXGBE_AUTOC_10G_XAUI LS64(0, 7, 0x3)\n+#define TXGBE_AUTOC_10G_KX4 LS64(1, 7, 0x3)\n+#define TXGBE_AUTOC_10G_CX4 LS64(2, 7, 0x3)\n+#define TXGBE_AUTOC_10G_KR LS64(3, 7, 0x3) /* fixme */\n+#define TXGBE_AUTOC_1G_PMA_PMD_MASK MS64(9, 0x7)\n+#define TXGBE_AUTOC_1G_BX LS64(0, 9, 0x7)\n+#define TXGBE_AUTOC_1G_KX LS64(1, 9, 0x7)\n+#define TXGBE_AUTOC_1G_SFI LS64(0, 9, 0x7)\n+#define TXGBE_AUTOC_1G_KX_BX LS64(1, 9, 0x7)\n+#define TXGBE_AUTOC_AN_RESTART MS64(12, 0x1)\n+#define TXGBE_AUTOC_LMS_MASK MS64(13, 0x7)\n+#define TXGBE_AUTOC_LMS_10Gs LS64(3, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_KX4_KX_KR LS64(4, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_SGMII_1G_100M LS64(5, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN LS64(6, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII LS64(7, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_1G_LINK_NO_AN LS64(0, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_10G_LINK_NO_AN LS64(1, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_1G_AN LS64(2, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_KX4_AN LS64(4, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_KX4_AN_1G_AN LS64(6, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_ATTACH_TYPE LS64(7, 13, 0x7)\n+#define TXGBE_AUTOC_LMS_AN MS64(15, 0x7)\n+\n+#define TXGBE_AUTOC_KR_SUPP MS64(16, 0x1)\n+#define TXGBE_AUTOC_FECR MS64(17, 0x1)\n+#define TXGBE_AUTOC_FECA MS64(18, 0x1)\n+#define TXGBE_AUTOC_AN_RX_ALIGN MS64(18, 0x1F) /* fixme */\n+#define TXGBE_AUTOC_AN_RX_DRIFT MS64(23, 0x3)\n+#define TXGBE_AUTOC_AN_RX_LOOSE MS64(24, 0x3)\n+#define TXGBE_AUTOC_PD_TMR MS64(25, 0x3)\n+#define TXGBE_AUTOC_RF MS64(27, 0x1)\n+#define TXGBE_AUTOC_ASM_PAUSE MS64(29, 0x1)\n+#define TXGBE_AUTOC_SYM_PAUSE MS64(28, 0x1)\n+#define TXGBE_AUTOC_PAUSE MS64(28, 0x3)\n+#define TXGBE_AUTOC_KX_SUPP MS64(30, 0x1)\n+#define TXGBE_AUTOC_KX4_SUPP MS64(31, 0x1)\n+\n+#define TXGBE_AUTOC_10Gs_PMA_PMD_MASK MS64(48, 0x3) /* serial */\n+#define TXGBE_AUTOC_10Gs_KR LS64(0, 48, 0x3)\n+#define TXGBE_AUTOC_10Gs_XFI LS64(1, 48, 0x3)\n+#define TXGBE_AUTOC_10Gs_SFI LS64(2, 48, 0x3)\n+#define TXGBE_AUTOC_LINK_DIA_MASK MS64(60, 0x7)\n+#define TXGBE_AUTOC_LINK_DIA_D3_MASK LS64(5, 60, 0x7)\n+\n+#define TXGBE_AUTOC_SPEED_MASK MS64(32, 0xFFFF)\n+#define TXGBD_AUTOC_SPEED(r) RS64(r, 32, 0xFFFF)\n+#define TXGBE_AUTOC_SPEED(v) LS64(v, 32, 0xFFFF)\n+#define TXGBE_LINK_SPEED_UNKNOWN 0\n+#define TXGBE_LINK_SPEED_10M_FULL 0x0002\n+#define TXGBE_LINK_SPEED_100M_FULL 0x0008\n+#define TXGBE_LINK_SPEED_1GB_FULL 0x0020\n+#define TXGBE_LINK_SPEED_2_5GB_FULL 0x0400\n+#define TXGBE_LINK_SPEED_5GB_FULL 0x0800\n+#define TXGBE_LINK_SPEED_10GB_FULL 0x0080\n+#define TXGBE_LINK_SPEED_40GB_FULL 0x0100\n+#define TXGBE_AUTOC_AUTONEG MS64(63, 0x1)\n+\n+\n+\n+/* Hardware Datapath:\n+ * RX: / Queue <- Filter \\\n+ * Host | TC <=> SEC <=> MAC <=> PHY\n+ * TX: \\ Queue -> Filter /\n+ *\n+ * Packet Filter:\n+ * RX: RSS < FDIR < Filter < Encrypt\n+ *\n+ * Macro Argument Naming:\n+ * rp = ring pair [0,127]\n+ * tc = traffic class [0,7]\n+ * up = user priority [0,7]\n+ * pi = pool index [0,63]\n+ * r = register\n+ * v = value\n+ * s = shift\n+ * m = mask\n+ * i,j,k = array index\n+ * H,L = high/low bits\n+ * HI,LO = high/low state\n+ */\n+\n+#define TXGBE_ETHPHYIF TXGBE_REG_DUMMY\n+#define TXGBE_ETHPHYIF_MDIO_ACT MS(1, 0x1)\n+#define TXGBE_ETHPHYIF_MDIO_MODE MS(2, 0x1)\n+#define TXGBE_ETHPHYIF_MDIO_BASE(r) RS(r, 3, 0x1F)\n+#define TXGBE_ETHPHYIF_MDIO_SHARED MS(13, 0x1)\n+#define TXGBE_ETHPHYIF_SPEED_10M MS(17, 0x1)\n+#define TXGBE_ETHPHYIF_SPEED_100M MS(18, 0x1)\n+#define TXGBE_ETHPHYIF_SPEED_1G MS(19, 0x1)\n+#define TXGBE_ETHPHYIF_SPEED_2_5G MS(20, 0x1)\n+#define TXGBE_ETHPHYIF_SPEED_10G MS(21, 0x1)\n+#define TXGBE_ETHPHYIF_SGMII_ENABLE MS(25, 0x1)\n+#define TXGBE_ETHPHYIF_INT_PHY_MODE MS(24, 0x1)\n+#define TXGBE_ETHPHYIF_IO_XPCS MS(30, 0x1)\n+#define TXGBE_ETHPHYIF_IO_EPHY MS(31, 0x1)\n+\n+/******************************************************************************\n+ * Chip Registers\n+ ******************************************************************************/\n+/**\n+ * Chip Status\n+ **/\n+#define TXGBE_PWR 0x010000\n+#define TXGBE_PWR_LAN(r) RS(r, 30, 0x3)\n+#define TXGBE_PWR_LAN_0 (1)\n+#define TXGBE_PWR_LAN_1 (2)\n+#define TXGBE_PWR_LAN_A (3)\n+#define TXGBE_CTL 0x010004\n+#define TXGBE_LOCKPF 0x010008\n+#define TXGBE_RST 0x01000C\n+#define TXGBE_RST_SW MS(0, 0x1)\n+#define TXGBE_RST_LAN(i) MS(((i)+1), 0x1)\n+#define TXGBE_RST_FW MS(3, 0x1)\n+#define TXGBE_RST_ETH(i) MS(((i)+29), 0x1)\n+#define TXGBE_RST_GLB MS(31, 0x1)\n+#define TXGBE_RST_DEFAULT (TXGBE_RST_SW | \\\n+\t\t\t\t TXGBE_RST_LAN(0) | \\\n+\t\t\t\t TXGBE_RST_LAN(1))\n+\n+#define TXGBE_STAT\t\t\t0x010028\n+#define TXGBE_STAT_MNGINIT\t\tMS(0, 0x1)\n+#define TXGBE_STAT_MNGVETO\t\tMS(8, 0x1)\n+#define TXGBE_STAT_ECCLAN0\t\tMS(16, 0x1)\n+#define TXGBE_STAT_ECCLAN1\t\tMS(17, 0x1)\n+#define TXGBE_STAT_ECCMNG\t\tMS(18, 0x1)\n+#define TXGBE_STAT_ECCPCIE\t\tMS(19, 0x1)\n+#define TXGBE_STAT_ECCPCIW\t\tMS(20, 0x1)\n+#define TXGBE_RSTSTAT 0x010030\n+#define TXGBE_RSTSTAT_PROG MS(20, 0x1)\n+#define TXGBE_RSTSTAT_PREP MS(19, 0x1)\n+#define TXGBE_RSTSTAT_TYPE_MASK MS(16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE(r) RS(r, 16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE_PE LS(0, 16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE_PWR LS(1, 16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE_HOT LS(2, 16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE_SW LS(3, 16, 0x7)\n+#define TXGBE_RSTSTAT_TYPE_FW LS(4, 16, 0x7)\n+#define TXGBE_RSTSTAT_TMRINIT_MASK MS(8, 0xFF)\n+#define TXGBE_RSTSTAT_TMRINIT(v) LS(v, 8, 0xFF)\n+#define TXGBE_RSTSTAT_TMRCNT_MASK MS(0, 0xFF)\n+#define TXGBE_RSTSTAT_TMRCNT(v) LS(v, 0, 0xFF)\n+#define TXGBE_PWRTMR\t\t\t0x010034\n+\n+/**\n+ * SPI(Flash)\n+ **/\n+#define TXGBE_SPICMD 0x010104\n+#define TXGBE_SPICMD_ADDR(v) LS(v, 0, 0xFFFFFF)\n+#define TXGBE_SPICMD_CLK(v) LS(v, 25, 0x7)\n+#define TXGBE_SPICMD_CMD(v) LS(v, 28, 0x7)\n+#define TXGBE_SPIDAT 0x010108\n+#define TXGBE_SPIDAT_BYPASS MS(31, 0x1)\n+#define TXGBE_SPIDAT_STATUS(v) LS(v, 16, 0xFF)\n+#define TXGBE_SPIDAT_OPDONE MS(0, 0x1)\n+#define TXGBE_SPISTATUS 0x01010C\n+#define TXGBE_SPISTATUS_OPDONE MS(0, 0x1)\n+#define TXGBE_SPISTATUS_BYPASS MS(31, 0x1)\n+#define TXGBE_SPIUSRCMD 0x010110\n+#define TXGBE_SPICFG0 0x010114\n+#define TXGBE_SPICFG1 0x010118\n+#define TXGBE_FLASH 0x010120\n+#define TXGBE_FLASH_PERSTD MS(0, 0x1)\n+#define TXGBE_FLASH_PWRRSTD MS(1, 0x1)\n+#define TXGBE_FLASH_SWRSTD MS(7, 0x1)\n+#define TXGBE_FLASH_LANRSTD(i) MS(((i)+9), 0x1)\n+#define TXGBE_SRAM 0x010124\n+#define TXGBE_SRAM_SZ(v) LS(v, 28, 0x7)\n+#define TXGBE_SRAMCTLECC 0x010130\n+#define TXGBE_SRAMINJECC 0x010134\n+#define TXGBE_SRAMECC 0x010138\n+\n+/**\n+ * Thermel Sensor\n+ **/\n+#define TXGBE_TSCTL 0x010300\n+#define TXGBE_TSCTL_MODE MS(31, 0x1)\n+#define TXGBE_TSREVAL 0x010304\n+#define TXGBE_TSREVAL_EA MS(0, 0x1)\n+#define TXGBE_TSDAT 0x010308\n+#define TXGBE_TSDAT_TMP(r) ((r) & 0x3FF)\n+#define TXGBE_TSDAT_VLD MS(16, 0x1)\n+#define TXGBE_TSALMWTRHI 0x01030C\n+#define TXGBE_TSALMWTRHI_VAL(v) (((v) & 0x3FF))\n+#define TXGBE_TSALMWTRLO 0x010310\n+#define TXGBE_TSALMWTRLO_VAL(v) (((v) & 0x3FF))\n+#define TXGBE_TSINTWTR 0x010314\n+#define TXGBE_TSINTWTR_HI MS(0, 0x1)\n+#define TXGBE_TSINTWTR_LO MS(1, 0x1)\n+#define TXGBE_TSALM 0x010318\n+#define TXGBE_TSALM_LO MS(0, 0x1)\n+#define TXGBE_TSALM_HI MS(1, 0x1)\n+\n+/**\n+ * Management\n+ **/\n+#define TXGBE_MNGTC 0x01CD10\n+#define TXGBE_MNGFWSYNC 0x01E000\n+#define TXGBE_MNGFWSYNC_REQ MS(0, 0x1)\n+#define TXGBE_MNGSWSYNC 0x01E004\n+#define TXGBE_MNGSWSYNC_REQ MS(0, 0x1)\n+#define TXGBE_SWSEM 0x01002C\n+#define TXGBE_SWSEM_PF MS(0, 0x1)\n+#define TXGBE_MNGSEM 0x01E008\n+#define TXGBE_MNGSEM_SW(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_MNGSEM_SWPHY MS(0, 0x1)\n+#define TXGBE_MNGSEM_SWMBX MS(2, 0x1)\n+#define TXGBE_MNGSEM_SWFLASH MS(3, 0x1)\n+#define TXGBE_MNGSEM_FW(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_MNGSEM_FWPHY MS(16, 0x1)\n+#define TXGBE_MNGSEM_FWMBX MS(18, 0x1)\n+#define TXGBE_MNGSEM_FWFLASH MS(19, 0x1)\n+#define TXGBE_MNGMBXCTL 0x01E044\n+#define TXGBE_MNGMBXCTL_SWRDY MS(0, 0x1)\n+#define TXGBE_MNGMBXCTL_SWACK MS(1, 0x1)\n+#define TXGBE_MNGMBXCTL_FWRDY MS(2, 0x1)\n+#define TXGBE_MNGMBXCTL_FWACK MS(3, 0x1)\n+#define TXGBE_MNGMBX 0x01E100\n+\n+/******************************************************************************\n+ * Port Registers\n+ ******************************************************************************/\n+/* Port Control */\n+#define TXGBE_PORTCTL 0x014400\n+#define TXGBE_PORTCTL_VLANEXT MS(0, 0x1)\n+#define TXGBE_PORTCTL_ETAG MS(1, 0x1)\n+#define TXGBE_PORTCTL_QINQ MS(2, 0x1)\n+#define TXGBE_PORTCTL_DRVLOAD MS(3, 0x1)\n+#define TXGBE_PORTCTL_UPLNK MS(4, 0x1)\n+#define TXGBE_PORTCTL_DCB MS(10, 0x1)\n+#define TXGBE_PORTCTL_NUMTC_MASK MS(11, 0x1)\n+#define TXGBE_PORTCTL_NUMTC_4 LS(0, 11, 0x1)\n+#define TXGBE_PORTCTL_NUMTC_8 LS(1, 11, 0x1)\n+#define TXGBE_PORTCTL_NUMVT_MASK MS(12, 0x3)\n+#define TXGBE_PORTCTL_NUMVT_16 LS(1, 12, 0x3)\n+#define TXGBE_PORTCTL_NUMVT_32 LS(2, 12, 0x3)\n+#define TXGBE_PORTCTL_NUMVT_64 LS(3, 12, 0x3)\n+#define TXGBE_PORTCTL_RSTDONE MS(14, 0x1)\n+#define TXGBE_PORTCTL_TEREDODIA MS(27, 0x1)\n+#define TXGBE_PORTCTL_GENEVEDIA MS(28, 0x1)\n+#define TXGBE_PORTCTL_VXLANGPEDIA MS(30, 0x1)\n+#define TXGBE_PORTCTL_VXLANDIA MS(31, 0x1)\n+\n+#define TXGBE_PORT 0x014404\n+#define TXGBE_PORT_LINKUP MS(0, 0x1)\n+#define TXGBE_PORT_LINK10G MS(1, 0x1)\n+#define TXGBE_PORT_LINK1000M MS(2, 0x1)\n+#define TXGBE_PORT_LINK100M MS(3, 0x1)\n+#define TXGBE_PORT_LANID(r) RS(r, 8, 0x1)\n+#define TXGBE_EXTAG 0x014408\n+#define TXGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF)\n+#define TXGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_EXTAG_VLAN_MASK MS(16, 0xFFFF)\n+#define TXGBE_EXTAG_VLAN(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_VXLANPORT 0x014410\n+#define TXGBE_VXLANPORTGPE 0x014414\n+#define TXGBE_GENEVEPORT 0x014418\n+#define TXGBE_TEREDOPORT 0x01441C\n+#define TXGBE_LEDCTL 0x014424\n+#define TXGBE_LEDCTL_SEL_MASK MS(0, 0xFFFF)\n+#define TXGBE_LEDCTL_SEL(s) MS((s), 0x1)\n+#define TXGBE_LEDCTL_OD_MASK MS(16, 0xFFFF)\n+#define TXGBE_LEDCTL_OD(s) MS(((s)+16), 0x1)\n+\t/* s=UP(0),10G(1),1G(2),100M(3),BSY(4) */\n+#define TXGBE_LEDCTL_ACTIVE (TXGBE_LEDCTL_SEL(4) | TXGBE_LEDCTL_OD(4))\n+#define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */\n+#define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF)\n+#define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF)\n+#define TXGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF)\n+\n+/**\n+ * GPIO Control\n+ * P0: link speed change\n+ * P1:\n+ * P2:\n+ * P3: optical laser disable\n+ * P4:\n+ * P5: link speed selection\n+ * P6:\n+ * P7: external phy event\n+ **/\n+#define TXGBE_SDP 0x014800\n+#define TXGBE_SDP_0 MS(0, 0x1)\n+#define TXGBE_SDP_1 MS(1, 0x1)\n+#define TXGBE_SDP_2 MS(2, 0x1)\n+#define TXGBE_SDP_3 MS(3, 0x1)\n+#define TXGBE_SDP_4 MS(4, 0x1)\n+#define TXGBE_SDP_5 MS(5, 0x1)\n+#define TXGBE_SDP_6 MS(6, 0x1)\n+#define TXGBE_SDP_7 MS(7, 0x1)\n+#define TXGBE_SDPDIR 0x014804\n+#define TXGBE_SDPCTL 0x014808\n+#define TXGBE_SDPINTEA 0x014830\n+#define TXGBE_SDPINTMSK 0x014834\n+#define TXGBE_SDPINTTYP 0x014838\n+#define TXGBE_SDPINTPOL 0x01483C\n+#define TXGBE_SDPINT 0x014840\n+#define TXGBE_SDPINTDB 0x014848\n+#define TXGBE_SDPINTEND 0x01484C\n+#define TXGBE_SDPDAT 0x014850\n+#define TXGBE_SDPLVLSYN 0x014854\n+\n+/**\n+ * MDIO(PHY)\n+ **/\n+#define TXGBE_MDIOSCA 0x011200\n+#define TXGBE_MDIOSCA_REG(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_MDIOSCA_PORT(v) LS(v, 16, 0x1F)\n+#define TXGBE_MDIOSCA_DEV(v) LS(v, 21, 0x1F)\n+#define TXGBE_MDIOSCD 0x011204\n+#define TXGBD_MDIOSCD_DAT(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_MDIOSCD_DAT(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_MDIOSCD_CMD_PREAD LS(1, 16, 0x3)\n+#define TXGBE_MDIOSCD_CMD_WRITE LS(2, 16, 0x3)\n+#define TXGBE_MDIOSCD_CMD_READ LS(3, 16, 0x3)\n+#define TXGBE_MDIOSCD_SADDR MS(18, 0x1)\n+#define TXGBE_MDIOSCD_CLOCK(v) LS(v, 19, 0x7)\n+#define TXGBE_MDIOSCD_BUSY MS(22, 0x1)\n+\n+/**\n+ * I2C (SFP)\n+ **/\n+#define TXGBE_I2CCTL 0x014900\n+#define TXGBE_I2CCTL_MAEA MS(0, 0x1)\n+#define TXGBE_I2CCTL_SPEED(v) LS(v, 1, 0x3)\n+#define TXGBE_I2CCTL_RESTART MS(5, 0x1)\n+#define TXGBE_I2CCTL_SLDA MS(6, 0x1)\n+#define TXGBE_I2CTGT 0x014904\n+#define TXGBE_I2CTGT_ADDR(v) LS(v, 0, 0x3FF)\n+#define TXGBE_I2CCMD 0x014910\n+#define TXGBE_I2CCMD_READ (MS(9, 0x1) | 0x100)\n+#define TXGBE_I2CCMD_WRITE (MS(9, 0x1))\n+#define TXGBE_I2CSCLHITM 0x014914\n+#define TXGBE_I2CSCLLOTM 0x014918\n+#define TXGBE_I2CINT 0x014934\n+#define TXGBE_I2CINT_RXFULL MS(2, 0x1)\n+#define TXGBE_I2CINT_TXEMPTY MS(4, 0x1)\n+#define TXGBE_I2CINTMSK 0x014930\n+#define TXGBE_I2CRXFIFO 0x014938\n+#define TXGBE_I2CTXFIFO 0x01493C\n+#define TXGBE_I2CEA 0x01496C\n+#define TXGBE_I2CST 0x014970\n+#define TXGBE_I2CST_ACT MS(5, 0x1)\n+#define TXGBE_I2CSCLTM 0x0149AC\n+#define TXGBE_I2CSDATM 0x0149B0\n+\n+/**\n+ * TPH\n+ **/\n+#define TXGBE_TPHCFG 0x014F00\n+\n+/******************************************************************************\n+ * Pool Registers\n+ ******************************************************************************/\n+#define TXGBE_POOLETHCTL(pl) (0x015600 + (pl) * 4)\n+#define TXGBE_POOLETHCTL_LBDIA MS(0, 0x1)\n+#define TXGBE_POOLETHCTL_LLBDIA MS(1, 0x1)\n+#define TXGBE_POOLETHCTL_LLB MS(2, 0x1)\n+#define TXGBE_POOLETHCTL_UCP MS(4, 0x1)\n+#define TXGBE_POOLETHCTL_ETP MS(5, 0x1)\n+#define TXGBE_POOLETHCTL_VLA MS(6, 0x1)\n+#define TXGBE_POOLETHCTL_VLP MS(7, 0x1)\n+#define TXGBE_POOLETHCTL_UTA MS(8, 0x1)\n+#define TXGBE_POOLETHCTL_MCHA MS(9, 0x1)\n+#define TXGBE_POOLETHCTL_UCHA MS(10, 0x1)\n+#define TXGBE_POOLETHCTL_BCA MS(11, 0x1)\n+#define TXGBE_POOLETHCTL_MCP MS(12, 0x1)\n+\n+/* DMA Control */\n+#define TXGBE_POOLRXENA(i) (0x012004 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLRXDNA(i) (0x012060 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXENA(i) (0x018004 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXDSA(i) (0x0180A0 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXLBET(i) (0x018050 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXASET(i) (0x018058 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXASMAC(i) (0x018060 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLTXASVLAN(i) (0x018070 + (i) * 4) /* 0-1 */\n+#define TXGBE_POOLDROPSWBK(i) (0x0151C8 + (i) * 4) /* 0-1 */\n+\n+#define TXGBE_POOLTAG(pl) (0x018100 + (pl) * 4)\n+#define TXGBE_POOLTAG_VTAG(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_POOLTAG_VTAG_MASK MS(0, 0xFFFF)\n+#define TXGBD_POOLTAG_VTAG_UP(r)\tRS(r, 13, 0x7)\n+#define TXGBE_POOLTAG_TPIDSEL(v) LS(v, 24, 0x7)\n+#define TXGBE_POOLTAG_ETAG_MASK MS(27, 0x3)\n+#define TXGBE_POOLTAG_ETAG LS(2, 27, 0x3)\n+#define TXGBE_POOLTAG_ACT_MASK MS(30, 0x3)\n+#define TXGBE_POOLTAG_ACT_ALWAYS LS(1, 30, 0x3)\n+#define TXGBE_POOLTAG_ACT_NEVER LS(2, 30, 0x3)\n+#define TXGBE_POOLTXARB 0x018204\n+#define TXGBE_POOLTXARB_WRR MS(1, 0x1)\n+#define TXGBE_POOLETAG(pl) (0x018700 + (pl) * 4)\n+\n+/* RSS Hash */\n+#define TXGBE_POOLRSS(pl) (0x019300 + (pl) * 4)\n+#define TXGBE_POOLRSS_L4HDR MS(1, 0x1)\n+#define TXGBE_POOLRSS_L3HDR MS(2, 0x1)\n+#define TXGBE_POOLRSS_L2HDR MS(3, 0x1)\n+#define TXGBE_POOLRSS_L2TUN MS(4, 0x1)\n+#define TXGBE_POOLRSS_TUNHDR MS(5, 0x1)\n+#define TXGBE_POOLRSSKEY(pl, i) (0x01A000 + (pl) * 0x40 + (i) * 4)\n+#define TXGBE_POOLRSSMAP(pl, i) (0x01B000 + (pl) * 0x40 + (i) * 4)\n+\n+/******************************************************************************\n+ * Packet Buffer\n+ ******************************************************************************/\n+/* Flow Control */\n+#define TXGBE_FCXOFFTM(i) (0x019200 + (i) * 4) /* 0-3 */\n+#define TXGBE_FCWTRLO(tc) (0x019220 + (tc) * 4)\n+#define TXGBE_FCWTRLO_TH(v) LS(v, 10, 0x1FF) /* KB */\n+#define TXGBE_FCWTRLO_XON MS(31, 0x1)\n+#define TXGBE_FCWTRHI(tc) (0x019260 + (tc) * 4)\n+#define TXGBE_FCWTRHI_TH(v) LS(v, 10, 0x1FF) /* KB */\n+#define TXGBE_FCWTRHI_XOFF MS(31, 0x1)\n+#define TXGBE_RXFCRFSH 0x0192A0\n+#define TXGBE_RXFCFSH_TIME(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FCSTAT 0x01CE00\n+#define TXGBE_FCSTAT_DLNK(tc) MS((tc), 0x1)\n+#define TXGBE_FCSTAT_ULNK(tc) MS((tc) + 8, 0x1)\n+\n+#define TXGBE_RXFCCFG 0x011090\n+#define TXGBE_RXFCCFG_FC MS(0, 0x1)\n+#define TXGBE_RXFCCFG_PFC MS(8, 0x1)\n+#define TXGBE_TXFCCFG 0x0192A4\n+#define TXGBE_TXFCCFG_FC MS(3, 0x1)\n+#define TXGBE_TXFCCFG_PFC MS(4, 0x1)\n+\n+/* Data Buffer */\n+#define TXGBE_PBRXCTL 0x019000\n+#define TXGBE_PBRXCTL_ST MS(0, 0x1)\n+#define TXGBE_PBRXCTL_ENA MS(31, 0x1)\n+#define TXGBE_PBRXUP2TC 0x019008\n+#define TXGBE_PBTXUP2TC 0x01C800\n+#define TXGBE_DCBUP2TC_MAP(tc, v) LS(v, 3 * (tc), 0x7)\n+#define TXGBE_DCBUP2TC_DEC(tc, r) RS(r, 3 * (tc), 0x7)\n+#define TXGBE_PBRXSIZE(tc) (0x019020 + (tc) * 4)\n+#define TXGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3FF)\n+\n+#define TXGBE_PBRXOFTMR 0x019094\n+#define TXGBE_PBRXDBGCMD 0x019090\n+#define TXGBE_PBRXDBGDAT(tc) (0x0190A0 + (tc) * 4)\n+#define TXGBE_PBTXDMATH(tc) (0x018020 + (tc) * 4)\n+#define TXGBE_PBTXSIZE(tc) (0x01CC00 + (tc) * 4)\n+\n+/* LLI */\n+#define TXGBE_PBRXLLI 0x19080\n+#define TXGBE_PBRXLLI_SZLT(v) LS(v, 0, 0xFFF)\n+#define TXGBE_PBRXLLI_UPLT(v) LS(v, 16, 0x7)\n+#define TXGBE_PBRXLLI_UPEA MS(19, 0x1)\n+#define TXGBE_PBRXLLI_CNM MS(20, 0x1)\n+\n+/* Port Arbiter(QoS) */\n+#define TXGBE_PARBTXCTL 0x01CD00\n+#define TXGBE_PARBTXCTL_SP MS(5, 0x1)\n+#define TXGBE_PARBTXCTL_DA MS(6, 0x1)\n+#define TXGBE_PARBTXCTL_RECYC MS(8, 0x1)\n+#define TXGBE_PARBTXCFG(tc) (0x01CD20 + (tc) * 4)\n+#define TXGBE_PARBTXCFG_CRQ(v) LS(v, 0, 0x1FF)\n+#define TXGBE_PARBTXCFG_BWG(v) LS(v, 9, 0x7)\n+#define TXGBE_PARBTXCFG_MCL(v) LS(v, 12, 0xFFF)\n+#define TXGBE_PARBTXCFG_GSP MS(30, 0x1)\n+#define TXGBE_PARBTXCFG_LSP MS(31, 0x1)\n+\n+/******************************************************************************\n+ * Queue Registers\n+ ******************************************************************************/\n+/* Queue Control */\n+#define TXGBE_QPRXDROP(i) (0x012080 + (i) * 4) /* 0-3 */\n+#define TXGBE_QPRXSTRPVLAN(i) (0x012090 + (i) * 4) /* 0-3 */\n+#define TXGBE_QPTXLLI(i) (0x018040 + (i) * 4) /* 0-3 */\n+\n+/* Queue Arbiter(QoS) */\n+#define TXGBE_QARBRXCTL 0x012000\n+#define TXGBE_QARBRXCTL_RC MS(1, 0x1)\n+#define TXGBE_QARBRXCTL_WSP MS(2, 0x1)\n+#define TXGBE_QARBRXCTL_DA MS(6, 0x1)\n+#define TXGBE_QARBRXCFG(tc) (0x012040 + (tc) * 4)\n+#define TXGBE_QARBRXCFG_CRQ(v) LS(v, 0, 0x1FF)\n+#define TXGBE_QARBRXCFG_BWG(v) LS(v, 9, 0x7)\n+#define TXGBE_QARBRXCFG_MCL(v) LS(v, 12, 0xFFF)\n+#define TXGBE_QARBRXCFG_GSP MS(30, 0x1)\n+#define TXGBE_QARBRXCFG_LSP MS(31, 0x1)\n+#define TXGBE_QARBRXTC 0x0194F8\n+#define TXGBE_QARBRXTC_RR MS(0, 0x1)\n+\n+#define TXGBE_QARBTXCTL 0x018200\n+#define TXGBE_QARBTXCTL_WSP MS(1, 0x1)\n+#define TXGBE_QARBTXCTL_RECYC MS(4, 0x1)\n+#define TXGBE_QARBTXCTL_DA MS(6, 0x1)\n+#define TXGBE_QARBTXCFG(tc) (0x018220 + (tc) * 4)\n+#define TXGBE_QARBTXCFG_CRQ(v) LS(v, 0, 0x1FF)\n+#define TXGBE_QARBTXCFG_BWG(v) LS(v, 9, 0x7)\n+#define TXGBE_QARBTXCFG_MCL(v) LS(v, 12, 0xFFF)\n+#define TXGBE_QARBTXCFG_GSP MS(30, 0x1)\n+#define TXGBE_QARBTXCFG_LSP MS(31, 0x1)\n+#define TXGBE_QARBTXMMW 0x018208\n+#define TXGBE_QARBTXMMW_DEF (4)\n+#define TXGBE_QARBTXMMW_JF (20)\n+#define TXGBE_QARBTXRATEI 0x01820C\n+#define TXGBE_QARBTXRATE 0x018404\n+#define TXGBE_QARBTXRATE_MIN(v) LS(v, 0, 0x3FFF)\n+#define TXGBE_QARBTXRATE_MAX(v) LS(v, 16, 0x3FFF)\n+#define TXGBE_QARBTXCRED(rp) (0x018500 + (rp) * 4)\n+\n+/* QCN */\n+#define TXGBE_QCNADJ 0x018210\n+#define TXGBE_QCNRP 0x018400\n+#define TXGBE_QCNRPRATE 0x018404\n+#define TXGBE_QCNRPADJ 0x018408\n+#define TXGBE_QCNRPRLD 0x01840C\n+\n+/* Misc Control */\n+#define TXGBE_RSECCTL 0x01200C\n+#define TXGBE_RSECCTL_TSRSC MS(0, 0x1)\n+#define TXGBE_DMATXCTRL 0x018000\n+#define TXGBE_DMATXCTRL_ENA MS(0, 0x1)\n+#define TXGBE_DMATXCTRL_TPID_MASK MS(16, 0xFFFF)\n+#define TXGBE_DMATXCTRL_TPID(v) LS(v, 16, 0xFFFF)\n+\n+/******************************************************************************\n+ * Packet Filter (L2-7)\n+ ******************************************************************************/\n+/**\n+ * Receive Scaling\n+ **/\n+#define TXGBE_RSSTBL(i) (0x019400 + (i) * 4) /* 32 */\n+#define TXGBE_RSSKEY(i) (0x019480 + (i) * 4) /* 10 */\n+#define TXGBE_RSSPBHASH 0x0194F0\n+#define TXGBE_RSSPBHASH_BITS(tc, v) LS(v, 3 * (tc), 0x7)\n+#define TXGBE_RACTL 0x0194F4\n+#define TXGBE_RACTL_RSSMKEY MS(0, 0x1)\n+#define TXGBE_RACTL_RSSENA MS(2, 0x1)\n+#define TXGBE_RACTL_RSSMASK MS(16, 0xFFFF)\n+#define TXGBE_RACTL_RSSIPV4TCP MS(16, 0x1)\n+#define TXGBE_RACTL_RSSIPV4 MS(17, 0x1)\n+#define TXGBE_RACTL_RSSIPV6 MS(20, 0x1)\n+#define TXGBE_RACTL_RSSIPV6TCP MS(21, 0x1)\n+#define TXGBE_RACTL_RSSIPV4UDP MS(22, 0x1)\n+#define TXGBE_RACTL_RSSIPV6UDP MS(23, 0x1)\n+\n+/**\n+ * Flow Director\n+ **/\n+#define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */\n+#define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */\n+#define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */\n+#define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */\n+#define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */\n+#define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */\n+\n+#define TXGBE_FDIRCTL 0x019500\n+#define TXGBE_FDIRCTL_BUF_MASK MS(0, 0x3)\n+#define TXGBE_FDIRCTL_BUF_64K LS(1, 0, 0x3)\n+#define TXGBE_FDIRCTL_BUF_128K LS(2, 0, 0x3)\n+#define TXGBE_FDIRCTL_BUF_256K LS(3, 0, 0x3)\n+#define TXGBD_FDIRCTL_BUF_BYTE(r) (1 << (15 + RS(r, 0, 0x3)))\n+#define TXGBE_FDIRCTL_INITDONE MS(3, 0x1)\n+#define TXGBE_FDIRCTL_PERFECT MS(4, 0x1)\n+#define TXGBE_FDIRCTL_REPORT_MASK MS(5, 0x7)\n+#define TXGBE_FDIRCTL_REPORT_MATCH LS(1, 5, 0x7)\n+#define TXGBE_FDIRCTL_REPORT_ALWAYS LS(5, 5, 0x7)\n+#define TXGBE_FDIRCTL_DROPQP_MASK MS(8, 0x7F)\n+#define TXGBE_FDIRCTL_DROPQP(v) LS(v, 8, 0x7F)\n+#define TXGBE_FDIRCTL_HASHBITS_MASK LS(20, 0xF)\n+#define TXGBE_FDIRCTL_HASHBITS(v) LS(v, 20, 0xF)\n+#define TXGBE_FDIRCTL_MAXLEN(v) LS(v, 24, 0xF)\n+#define TXGBE_FDIRCTL_FULLTHR(v) LS(v, 28, 0xF)\n+#define TXGBE_FDIRFLEXCFG(i) (0x019580 + (i) * 4) /* 0-15 */\n+#define TXGBD_FDIRFLEXCFG_ALL(r, i) RS(0, (i) << 3, 0xFF)\n+#define TXGBE_FDIRFLEXCFG_ALL(v, i) LS(v, (i) << 3, 0xFF)\n+#define TXGBE_FDIRFLEXCFG_BASE_MAC LS(0, 0, 0x3)\n+#define TXGBE_FDIRFLEXCFG_BASE_L2 LS(1, 0, 0x3)\n+#define TXGBE_FDIRFLEXCFG_BASE_L3 LS(2, 0, 0x3)\n+#define TXGBE_FDIRFLEXCFG_BASE_PAY LS(3, 0, 0x3)\n+#define TXGBE_FDIRFLEXCFG_DIA MS(2, 0x1)\n+#define TXGBE_FDIRFLEXCFG_OFST_MASK MS(3, 0x1F)\n+#define TXGBD_FDIRFLEXCFG_OFST(r) RS(r, 3, 0x1F)\n+#define TXGBE_FDIRFLEXCFG_OFST(v) LS(v, 3, 0x1F)\n+#define TXGBE_FDIRBKTHKEY 0x019568\n+#define TXGBE_FDIRSIGHKEY 0x01956C\n+\n+/* Common Mask */\n+#define TXGBE_FDIRDIP4MSK 0x01953C\n+#define TXGBE_FDIRSIP4MSK 0x019540\n+#define TXGBE_FDIRIP6MSK 0x019574\n+#define TXGBE_FDIRIP6MSK_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FDIRIP6MSK_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRTCPMSK 0x019544\n+#define TXGBE_FDIRTCPMSK_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FDIRTCPMSK_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRUDPMSK 0x019548\n+#define TXGBE_FDIRUDPMSK_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FDIRUDPMSK_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRSCTPMSK 0x019560\n+#define TXGBE_FDIRSCTPMSK_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FDIRSCTPMSK_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRMSK 0x019570\n+#define TXGBE_FDIRMSK_POOL MS(2, 0x1)\n+#define TXGBE_FDIRMSK_L4P MS(3, 0x1)\n+#define TXGBE_FDIRMSK_L3P MS(4, 0x1)\n+#define TXGBE_FDIRMSK_TUNTYPE MS(5, 0x1)\n+#define TXGBE_FDIRMSK_TUNIP MS(6, 0x1)\n+#define TXGBE_FDIRMSK_TUNPKT MS(7, 0x1)\n+\n+/* Programming Interface */\n+#define TXGBE_FDIRPIPORT 0x019520\n+#define TXGBE_FDIRPIPORT_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_FDIRPIPORT_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRPISIP6(i) (0x01950C + (i) * 4) /* [0,2] */\n+#define TXGBE_FDIRPISIP4 0x019518\n+#define TXGBE_FDIRPIDIP4 0x01951C\n+#define TXGBE_FDIRPIFLEX 0x019524\n+#define TXGBE_FDIRPIFLEX_PTYPE(v) LS(v, 0, 0xFF)\n+#define TXGBE_FDIRPIFLEX_FLEX(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRPIHASH 0x019528\n+#define TXGBE_FDIRPIHASH_BKT(v) LS(v, 0, 0x7FFF)\n+#define TXGBE_FDIRPIHASH_VLD MS(15, 0x1)\n+#define TXGBE_FDIRPIHASH_SIG(v) LS(v, 16, 0x7FFF)\n+#define TXGBE_FDIRPIHASH_IDX(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FDIRPICMD 0x01952C\n+#define TXGBE_FDIRPICMD_OP_MASK MS(0, 0x3)\n+#define TXGBE_FDIRPICMD_OP_ADD LS(1, 0, 0x3)\n+#define TXGBE_FDIRPICMD_OP_REM LS(2, 0, 0x3)\n+#define TXGBE_FDIRPICMD_OP_QRY LS(3, 0, 0x3)\n+#define TXGBE_FDIRPICMD_VLD MS(2, 0x1)\n+#define TXGBE_FDIRPICMD_UPD MS(3, 0x1)\n+#define TXGBE_FDIRPICMD_DIP6 MS(4, 0x1)\n+#define TXGBE_FDIRPICMD_FT(v) LS(v, 5, 0x3)\n+#define TXGBE_FDIRPICMD_FT_MASK MS(5, 0x3)\n+#define TXGBE_FDIRPICMD_FT_UDP LS(1, 5, 0x3)\n+#define TXGBE_FDIRPICMD_FT_TCP LS(2, 5, 0x3)\n+#define TXGBE_FDIRPICMD_FT_SCTP LS(3, 5, 0x3)\n+#define TXGBE_FDIRPICMD_IP6 MS(7, 0x1)\n+#define TXGBE_FDIRPICMD_CLR MS(8, 0x1)\n+#define TXGBE_FDIRPICMD_DROP MS(9, 0x1)\n+#define TXGBE_FDIRPICMD_LLI MS(10, 0x1)\n+#define TXGBE_FDIRPICMD_LAST MS(11, 0x1)\n+#define TXGBE_FDIRPICMD_COLLI MS(12, 0x1)\n+#define TXGBE_FDIRPICMD_QPENA MS(15, 0x1)\n+#define TXGBE_FDIRPICMD_QP(v) LS(v, 16, 0x7F)\n+#define TXGBE_FDIRPICMD_POOL(v) LS(v, 24, 0x3F)\n+\n+/**\n+ * 5-tuple Filter\n+ **/\n+#define TXGBE_5TFSADDR(i) (0x019600 + (i) * 4) /* 0-127 */\n+#define TXGBE_5TFDADDR(i) (0x019800 + (i) * 4) /* 0-127 */\n+#define TXGBE_5TFPORT(i) (0x019A00 + (i) * 4) /* 0-127 */\n+#define TXGBE_5TFPORT_SRC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_5TFPORT_DST(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_5TFCTL0(i) (0x019C00 + (i) * 4) /* 0-127 */\n+#define TXGBE_5TFCTL0_PROTO(v) LS(v, 0, 0x3)\n+enum txgbe_5tuple_protocol {\n+\tTXGBE_5TF_PROT_TCP = 0,\n+\tTXGBE_5TF_PROT_UDP,\n+\tTXGBE_5TF_PROT_SCTP,\n+\tTXGBE_5TF_PROT_NONE,\n+};\n+#define TXGBE_5TFCTL0_PRI(v) LS(v, 2, 0x7)\n+#define TXGBE_5TFCTL0_POOL(v) LS(v, 8, 0x3F)\n+#define TXGBE_5TFCTL0_MASK MS(25, 0x3F)\n+#define TXGBE_5TFCTL0_MSADDR MS(25, 0x1)\n+#define TXGBE_5TFCTL0_MDADDR MS(26, 0x1)\n+#define TXGBE_5TFCTL0_MSPORT MS(27, 0x1)\n+#define TXGBE_5TFCTL0_MDPORT MS(28, 0x1)\n+#define TXGBE_5TFCTL0_MPROTO MS(29, 0x1)\n+#define TXGBE_5TFCTL0_MPOOL MS(30, 0x1)\n+#define TXGBE_5TFCTL0_ENA MS(31, 0x1)\n+#define TXGBE_5TFCTL1(i) (0x019E00 + (i) * 4) /* 0-127 */\n+#define TXGBE_5TFCTL1_CHKSZ MS(12, 0x1)\n+#define TXGBE_5TFCTL1_LLI MS(20, 0x1)\n+#define TXGBE_5TFCTL1_QP(v) LS(v, 21, 0x7F)\n+\n+/**\n+ * Storm Control\n+ **/\n+#define TXGBE_STRMCTL 0x015004\n+#define TXGBE_STRMCTL_MCPNSH MS(0, 0x1)\n+#define TXGBE_STRMCTL_MCDROP MS(1, 0x1)\n+#define TXGBE_STRMCTL_BCPNSH MS(2, 0x1)\n+#define TXGBE_STRMCTL_BCDROP MS(3, 0x1)\n+#define TXGBE_STRMCTL_DFTPOOL MS(4, 0x1)\n+#define TXGBE_STRMCTL_ITVL(v) LS(v, 8, 0x3FF)\n+#define TXGBE_STRMTH 0x015008\n+#define TXGBE_STRMTH_MC(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_STRMTH_BC(v) LS(v, 16, 0xFFFF)\n+\n+/******************************************************************************\n+ * Ether Flow\n+ ******************************************************************************/\n+#define TXGBE_PSRCTL 0x015000\n+#define TXGBE_PSRCTL_TPE MS(4, 0x1)\n+#define TXGBE_PSRCTL_ADHF12_MASK MS(5, 0x3)\n+#define TXGBE_PSRCTL_ADHF12(v) LS(v, 5, 0x3)\n+#define TXGBE_PSRCTL_UCHFENA MS(7, 0x1)\n+#define TXGBE_PSRCTL_MCHFENA MS(7, 0x1)\n+#define TXGBE_PSRCTL_MCP MS(8, 0x1)\n+#define TXGBE_PSRCTL_UCP MS(9, 0x1)\n+#define TXGBE_PSRCTL_BCA MS(10, 0x1)\n+#define TXGBE_PSRCTL_L4CSUM MS(12, 0x1)\n+#define TXGBE_PSRCTL_PCSD MS(13, 0x1)\n+#define TXGBE_PSRCTL_RSCPUSH MS(15, 0x1)\n+#define TXGBE_PSRCTL_RSCDIA MS(16, 0x1)\n+#define TXGBE_PSRCTL_RSCACK MS(17, 0x1)\n+#define TXGBE_PSRCTL_LBENA MS(18, 0x1)\n+#define TXGBE_FRMSZ 0x015020\n+#define TXGBE_FRMSZ_MAX_MASK MS(0, 0xFFFF)\n+#define TXGBE_FRMSZ_MAX(v) LS((v) + 4, 0, 0xFFFF)\n+#define TXGBE_VLANCTL 0x015088\n+#define TXGBE_VLANCTL_TPID_MASK MS(0, 0xFFFF)\n+#define TXGBE_VLANCTL_TPID(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_VLANCTL_CFI MS(28, 0x1)\n+#define TXGBE_VLANCTL_CFIENA MS(29, 0x1)\n+#define TXGBE_VLANCTL_VFE MS(30, 0x1)\n+#define TXGBE_POOLCTL 0x0151B0\n+#define TXGBE_POOLCTL_DEFDSA MS(29, 0x1)\n+#define TXGBE_POOLCTL_RPLEN MS(30, 0x1)\n+#define TXGBE_POOLCTL_MODE_MASK MS(16, 0x3)\n+#define TXGBE_PSRPOOL_MODE_MAC LS(0, 16, 0x3)\n+#define TXGBE_PSRPOOL_MODE_ETAG LS(1, 16, 0x3)\n+#define TXGBE_POOLCTL_DEFPL(v) LS(v, 7, 0x3F)\n+#define TXGBE_POOLCTL_DEFPL_MASK MS(7, 0x3F)\n+\n+#define TXGBE_ETFLT(i) (0x015128 + (i) * 4) /* 0-7 */\n+#define TXGBE_ETFLT_ETID(v) LS(v, 0, 0xFFFF)\n+#define TXGBE_ETFLT_ETID_MASK MS(0, 0xFFFF)\n+#define TXGBE_ETFLT_POOL(v) LS(v, 20, 0x3FF)\n+#define TXGBE_ETFLT_POOLENA MS(26, 0x1)\n+#define TXGBE_ETFLT_FCOE MS(27, 0x1)\n+#define TXGBE_ETFLT_TXAS MS(29, 0x1)\n+#define TXGBE_ETFLT_1588 MS(30, 0x1)\n+#define TXGBE_ETFLT_ENA MS(31, 0x1)\n+#define TXGBE_ETCLS(i) (0x019100 + (i) * 4) /* 0-7 */\n+#define TXGBE_ETCLS_QPID(v) LS(v, 16, 0x7F)\n+#define TXGBD_ETCLS_QPID(r) RS(r, 16, 0x7F)\n+#define TXGBE_ETCLS_LLI MS(29, 0x1)\n+#define TXGBE_ETCLS_QENA MS(31, 0x1)\n+#define TXGBE_SYNCLS 0x019130\n+#define TXGBE_SYNCLS_ENA MS(0, 0x1)\n+#define TXGBE_SYNCLS_QPID(v) LS(v, 1, 0x7F)\n+#define TXGBD_SYNCLS_QPID(r) RS(r, 1, 0x7F)\n+#define TXGBE_SYNCLS_QPID_MASK MS(1, 0x7F)\n+#define TXGBE_SYNCLS_HIPRIO MS(31, 0x1)\n+\n+/* MAC & VLAN & NVE */\n+#define TXGBE_PSRVLANIDX 0x016230 /* 0-63 */\n+#define TXGBE_PSRVLAN 0x016220\n+#define TXGBE_PSRVLAN_VID(v) LS(v, 0, 0xFFF)\n+#define TXGBE_PSRVLAN_EA MS(31, 0x1)\n+#define TXGBE_PSRVLANPLM(i) (0x016224 + (i) * 4) /* 0-1 */\n+\n+#define TXGBE_PSRNVEI 0x016260 /* 256 */\n+#define TXGBE_PSRNVEADDR(i) (0x016240 + (i) * 4) /* 0-3 */\n+#define TXGBE_PSRNVE 0x016250\n+#define TXGBE_PSRNVE_KEY(v) LS(v, 0, 0xFFFFFF)\n+#define TXGBE_PSRNVE_TYPE(v) LS(v, 24, 0x3)\n+#define TXGBE_PSRNVECTL 0x016254\n+#define TXGBE_PSRNVECTL_MKEY MS(0, 0x1)\n+#define TXGBE_PSRNVECTL_MADDR MS(1, 0x1)\n+#define TXGBE_PSRNVECTL_SEL(v) LS(v, 8, 0x3)\n+#define TXGBE_PSRNVECTL_SEL_ODIP (0)\n+#define TXGBE_PSRNVECTL_SEL_IDMAC (1)\n+#define TXGBE_PSRNVECTL_SEL_IDIP (2)\n+#define TXGBE_PSRNVECTL_EA MS(31, 0x1)\n+#define TXGBE_PSRNVEPM(i) (0x016258 + (i) * 4) /* 0-1 */\n+\n+/**\n+ * FCoE\n+ **/\n+#define TXGBE_FCCTL 0x015100\n+#define TXGBE_FCCTL_LLI MS(0, 0x1)\n+#define TXGBE_FCCTL_SAVBAD MS(1, 0x1)\n+#define TXGBE_FCCTL_FRSTRDH MS(2, 0x1)\n+#define TXGBE_FCCTL_LSEQH MS(3, 0x1)\n+#define TXGBE_FCCTL_ALLH MS(4, 0x1)\n+#define TXGBE_FCCTL_FSEQH MS(5, 0x1)\n+#define TXGBE_FCCTL_ICRC MS(6, 0x1)\n+#define TXGBE_FCCTL_CRCBO MS(7, 0x1)\n+#define TXGBE_FCCTL_VER(v) LS(v, 8, 0xF)\n+#define TXGBE_FCRSSCTL 0x019140\n+#define TXGBE_FCRSSCTL_EA MS(0, 0x1)\n+#define TXGBE_FCRSSTBL(i) (0x019160 + (i) * 4) /* 0-7 */\n+#define TXGBE_FCRSSTBL_QUE(v) LS(v, 0, 0x7F)\n+\n+#define TXGBE_FCRXEOF 0x015158\n+#define TXGBE_FCRXSOF 0x0151F8\n+#define TXGBE_FCTXEOF 0x018384\n+#define TXGBE_FCTXSOF 0x018380\n+#define TXGBE_FCRXFCDESC(i) (0x012410 + (i) * 4) /* 0-1 */\n+#define TXGBE_FCRXFCBUF 0x012418\n+#define TXGBE_FCRXFCDDP 0x012420\n+#define TXGBE_FCRXCTXINVL(i) (0x0190C0 + (i) * 4) /* 0-15 */\n+\n+/* Programming Interface */\n+#define TXGBE_FCCTXT 0x015110\n+#define TXGBE_FCCTXT_ID(v) (((v) & 0x1FF)) /* 512 */\n+#define TXGBE_FCCTXT_REVA LS(0x1, 13, 0x1)\n+#define TXGBE_FCCTXT_WREA LS(0x1, 14, 0x1)\n+#define TXGBE_FCCTXT_RDEA LS(0x1, 15, 0x1)\n+#define TXGBE_FCCTXTCTL 0x015108\n+#define TXGBE_FCCTXTCTL_EA MS(0, 0x1)\n+#define TXGBE_FCCTXTCTL_FIRST MS(1, 0x1)\n+#define TXGBE_FCCTXTCTL_WR MS(2, 0x1)\n+#define TXGBE_FCCTXTCTL_SEQID(v) LS(v, 8, 0xFF)\n+#define TXGBE_FCCTXTCTL_SEQNR(v) LS(v, 16, 0xFFFF)\n+#define TXGBE_FCCTXTPARM 0x0151D8\n+\n+/**\n+ * Mirror Rules\n+ **/\n+#define TXGBE_MIRRCTL(i) (0x015B00 + (i) * 4)\n+#define TXGBE_MIRRCTL_POOL MS(0, 0x1)\n+#define TXGBE_MIRRCTL_UPLINK MS(1, 0x1)\n+#define TXGBE_MIRRCTL_DNLINK MS(2, 0x1)\n+#define TXGBE_MIRRCTL_VLAN MS(3, 0x1)\n+#define TXGBE_MIRRCTL_DESTP(v) LS(v, 8, 0x3F)\n+#define TXGBE_MIRRVLANL(i) (0x015B10 + (i) * 8)\n+#define TXGBE_MIRRVLANH(i) (0x015B14 + (i) * 8)\n+#define TXGBE_MIRRPOOLL(i) (0x015B30 + (i) * 8)\n+#define TXGBE_MIRRPOOLH(i) (0x015B34 + (i) * 8)\n+\n+/**\n+ * Time Stamp\n+ **/\n+#define TXGBE_TSRXCTL 0x015188\n+#define TXGBE_TSRXCTL_VLD MS(0, 0x1)\n+#define TXGBE_TSRXCTL_TYPE(v) LS(v, 1, 0x7)\n+#define TXGBE_TSRXCTL_TYPE_V2L2 (0)\n+#define TXGBE_TSRXCTL_TYPE_V1L4 (1)\n+#define TXGBE_TSRXCTL_TYPE_V2L24 (2)\n+#define TXGBE_TSRXCTL_TYPE_V2EVENT (5)\n+#define TXGBE_TSRXCTL_ENA MS(4, 0x1)\n+#define TXGBE_TSRXSTMPL 0x0151E8\n+#define TXGBE_TSRXSTMPH 0x0151A4\n+#define TXGBE_TSTXCTL 0x01D400\n+#define TXGBE_TSTXCTL_VLD MS(0, 0x1)\n+#define TXGBE_TSTXCTL_ENA MS(4, 0x1)\n+#define TXGBE_TSTXSTMPL 0x01D404\n+#define TXGBE_TSTXSTMPH 0x01D408\n+#define TXGBE_TSTIMEL 0x01D40C\n+#define TXGBE_TSTIMEH 0x01D410\n+#define TXGBE_TSTIMEINC 0x01D414\n+#define TXGBE_TSTIMEINC_IV(v) LS(v, 0, 0xFFFFFF)\n+#define TXGBE_TSTIMEINC_IP(v) LS(v, 24, 0xFF)\n+#define TXGBE_TSTIMEINC_VP(v, p) \\\n+\t\t\t(((v) & MS(0, 0xFFFFFF)) | TXGBE_TSTIMEINC_IP(p))\n+\n+/**\n+ * Wake on Lan\n+ **/\n+#define TXGBE_WOLCTL 0x015B80\n+#define TXGBE_WOLIPCTL 0x015B84\n+#define TXGBE_WOLIP4(i) (0x015BC0 + (i) * 4) /* 0-3 */\n+#define TXGBE_WOLIP6(i) (0x015BE0 + (i) * 4) /* 0-3 */\n+\n+#define TXGBE_WOLFLEXCTL 0x015CFC\n+#define TXGBE_WOLFLEXI 0x015B8C\n+#define TXGBE_WOLFLEXDAT(i) (0x015C00 + (i) * 16) /* 0-15 */\n+#define TXGBE_WOLFLEXMSK(i) (0x015C08 + (i) * 16) /* 0-15 */\n+\n+/******************************************************************************\n+ * Security Registers\n+ ******************************************************************************/\n+#define TXGBE_SECRXCTL 0x017000\n+#define TXGBE_SECRXCTL_ODSA MS(0, 0x1)\n+#define TXGBE_SECRXCTL_XDSA MS(1, 0x1)\n+#define TXGBE_SECRXCTL_CRCSTRIP MS(2, 0x1)\n+#define TXGBE_SECRXCTL_SAVEBAD MS(6, 0x1)\n+#define TXGBE_SECRXSTAT 0x017004\n+#define TXGBE_SECRXSTAT_RDY MS(0, 0x1)\n+#define TXGBE_SECRXSTAT_ECC MS(1, 0x1)\n+\n+#define TXGBE_SECTXCTL 0x01D000\n+#define TXGBE_SECTXCTL_ODSA MS(0, 0x1)\n+#define TXGBE_SECTXCTL_XDSA MS(1, 0x1)\n+#define TXGBE_SECTXCTL_STFWD MS(2, 0x1)\n+#define TXGBE_SECTXCTL_MSKIV MS(3, 0x1)\n+#define TXGBE_SECTXSTAT 0x01D004\n+#define TXGBE_SECTXSTAT_RDY MS(0, 0x1)\n+#define TXGBE_SECTXSTAT_ECC MS(1, 0x1)\n+#define TXGBE_SECTXBUFAF 0x01D008\n+#define TXGBE_SECTXBUFAE 0x01D00C\n+#define TXGBE_SECTXIFG 0x01D020\n+#define TXGBE_SECTXIFG_MIN(v) LS(v, 0, 0xF)\n+#define TXGBE_SECTXIFG_MIN_MASK MS(0, 0xF)\n+\n+\n+/**\n+ * LinkSec\n+ **/\n+#define TXGBE_LSECRXCAP\t 0x017200\n+#define TXGBE_LSECRXCTL 0x017204\n+\t/* disabled(0),check(1),strict(2),drop(3) */\n+#define TXGBE_LSECRXCTL_MODE_MASK MS(2, 0x3)\n+#define TXGBE_LSECRXCTL_MODE_STRICT LS(2, 2, 0x3)\n+#define TXGBE_LSECRXCTL_POSTHDR MS(6, 0x1)\n+#define TXGBE_LSECRXCTL_REPLAY MS(7, 0x1)\n+#define TXGBE_LSECRXSCIL 0x017208\n+#define TXGBE_LSECRXSCIH 0x01720C\n+#define TXGBE_LSECRXSA(i) (0x017210 + (i) * 4) /* 0-1 */\n+#define TXGBE_LSECRXPN(i) (0x017218 + (i) * 4) /* 0-1 */\n+#define TXGBE_LSECRXKEY(n, i)\t (0x017220 + 0x10 * (n) + 4 * (i)) /* 0-3 */\n+#define TXGBE_LSECTXCAP 0x01D200\n+#define TXGBE_LSECTXCTL 0x01D204\n+\t/* disabled(0), auth(1), auth+encrypt(2) */\n+#define TXGBE_LSECTXCTL_MODE_MASK MS(0, 0x3)\n+#define TXGBE_LSECTXCTL_MODE_AUTH LS(1, 0, 0x3)\n+#define TXGBE_LSECTXCTL_MODE_AENC LS(2, 0, 0x3)\n+#define TXGBE_LSECTXCTL_PNTRH_MASK MS(8, 0xFFFFFF)\n+#define TXGBE_LSECTXCTL_PNTRH(v) LS(v, 8, 0xFFFFFF)\n+#define TXGBE_LSECTXSCIL 0x01D208\n+#define TXGBE_LSECTXSCIH 0x01D20C\n+#define TXGBE_LSECTXSA 0x01D210\n+#define TXGBE_LSECTXPN0 0x01D214\n+#define TXGBE_LSECTXPN1 0x01D218\n+#define TXGBE_LSECTXKEY0(i) (0x01D21C + (i) * 4) /* 0-3 */\n+#define TXGBE_LSECTXKEY1(i) (0x01D22C + (i) * 4) /* 0-3 */\n+\n+#define TXGBE_LSECRX_UTPKT 0x017240\n+#define TXGBE_LSECRX_DECOCT 0x017244\n+#define TXGBE_LSECRX_VLDOCT 0x017248\n+#define TXGBE_LSECRX_BTPKT 0x01724C\n+#define TXGBE_LSECRX_NOSCIPKT 0x017250\n+#define TXGBE_LSECRX_UNSCIPKT 0x017254\n+#define TXGBE_LSECRX_UNCHKPKT 0x017258\n+#define TXGBE_LSECRX_DLYPKT 0x01725C\n+#define TXGBE_LSECRX_LATEPKT 0x017260\n+#define TXGBE_LSECRX_OKPKT(i) (0x017264 + (i) * 4) /* 0-1 */\n+#define TXGBE_LSECRX_BADPKT(i) (0x01726C + (i) * 4) /* 0-1 */\n+#define TXGBE_LSECRX_INVPKT(i) (0x017274 + (i) * 4) /* 0-1 */\n+#define TXGBE_LSECRX_BADSAPKT 0x01727C\n+#define TXGBE_LSECRX_INVSAPKT 0x017280\n+#define TXGBE_LSECTX_UTPKT 0x01D23C\n+#define TXGBE_LSECTX_ENCPKT 0x01D240\n+#define TXGBE_LSECTX_PROTPKT 0x01D244\n+#define TXGBE_LSECTX_ENCOCT 0x01D248\n+#define TXGBE_LSECTX_PROTOCT 0x01D24C\n+\n+/**\n+ * IpSec\n+ **/\n+#define TXGBE_ISECRXIDX 0x017100\n+#define TXGBE_ISECRXADDR(i) (0x017104 + (i) * 4) /*0-3*/\n+#define TXGBE_ISECRXSPI 0x017114\n+#define TXGBE_ISECRXIPIDX 0x017118\n+#define TXGBE_ISECRXKEY(i) (0x01711C + (i) * 4) /*0-3*/\n+#define TXGBE_ISECRXSALT 0x01712C\n+#define TXGBE_ISECRXMODE 0x017130\n+\n+#define TXGBE_ISECTXIDX 0x01D100\n+#define TXGBE_ISECTXIDX_WT 0x80000000U\n+#define TXGBE_ISECTXIDX_RD 0x40000000U\n+#define TXGBE_ISECTXIDX_SDIDX 0x0U\n+#define TXGBE_ISECTXIDX_ENA 0x00000001U\n+\n+#define TXGBE_ISECTXSALT 0x01D104\n+#define TXGBE_ISECTXKEY(i) (0x01D108 + (i) * 4) /* 0-3 */\n+\n+/******************************************************************************\n+ * MAC Registers\n+ ******************************************************************************/\n+#define TXGBE_MACRXCFG 0x011004\n+#define TXGBE_MACRXCFG_ENA MS(0, 0x1)\n+#define TXGBE_MACRXCFG_JUMBO MS(8, 0x1)\n+#define TXGBE_MACRXCFG_LB MS(10, 0x1)\n+#define TXGBE_MACCNTCTL 0x011800\n+#define TXGBE_MACCNTCTL_RC MS(2, 0x1)\n+\n+#define TXGBE_MACRXFLT 0x011008\n+#define TXGBE_MACRXFLT_PROMISC MS(0, 0x1)\n+#define TXGBE_MACRXFLT_CTL_MASK MS(6, 0x3)\n+#define TXGBE_MACRXFLT_CTL_DROP LS(0, 6, 0x3)\n+#define TXGBE_MACRXFLT_CTL_NOPS LS(1, 6, 0x3)\n+#define TXGBE_MACRXFLT_CTL_NOFT LS(2, 6, 0x3)\n+#define TXGBE_MACRXFLT_CTL_PASS LS(3, 6, 0x3)\n+#define TXGBE_MACRXFLT_RXALL MS(31, 0x1)\n+\n+/******************************************************************************\n+ * Statistic Registers\n+ ******************************************************************************/\n+/* Ring Counter */\n+#define TXGBE_QPRXPKT(rp) (0x001014 + 0x40 * (rp))\n+#define TXGBE_QPRXOCTL(rp) (0x001018 + 0x40 * (rp))\n+#define TXGBE_QPRXOCTH(rp) (0x00101C + 0x40 * (rp))\n+#define TXGBE_QPTXPKT(rp) (0x003014 + 0x40 * (rp))\n+#define TXGBE_QPTXOCTL(rp) (0x003018 + 0x40 * (rp))\n+#define TXGBE_QPTXOCTH(rp) (0x00301C + 0x40 * (rp))\n+#define TXGBE_QPRXMPKT(rp) (0x001020 + 0x40 * (rp))\n+\n+/* Host DMA Counter */\n+#define TXGBE_DMATXDROP 0x018300\n+#define TXGBE_DMATXSECDROP 0x018304\n+#define TXGBE_DMATXPKT 0x018308\n+#define TXGBE_DMATXOCTL 0x01830C\n+#define TXGBE_DMATXOCTH 0x018310\n+#define TXGBE_DMATXMNG 0x018314\n+#define TXGBE_DMARXDROP 0x012500\n+#define TXGBE_DMARXPKT 0x012504\n+#define TXGBE_DMARXOCTL 0x012508\n+#define TXGBE_DMARXOCTH 0x01250C\n+#define TXGBE_DMARXMNG 0x012510\n+\n+/* Packet Buffer Counter */\n+#define TXGBE_PBRXMISS(tc) (0x019040 + (tc) * 4)\n+#define TXGBE_PBRXPKT 0x019060\n+#define TXGBE_PBRXREP 0x019064\n+#define TXGBE_PBRXDROP 0x019068\n+#define TXGBE_PBRXLNKXOFF 0x011988\n+#define TXGBE_PBRXLNKXON 0x011E0C\n+#define TXGBE_PBRXUPXON(up) (0x011E30 + (up) * 4)\n+#define TXGBE_PBRXUPXOFF(up) (0x011E10 + (up) * 4)\n+\n+#define TXGBE_PBTXLNKXOFF 0x019218\n+#define TXGBE_PBTXLNKXON 0x01921C\n+#define TXGBE_PBTXUPXON(up) (0x0192E0 + (up) * 4)\n+#define TXGBE_PBTXUPXOFF(up) (0x0192C0 + (up) * 4)\n+#define TXGBE_PBTXUPOFF(up) (0x019280 + (up) * 4)\n+\n+#define TXGBE_PBLPBK 0x01CF08\n+\n+/* Ether Flow Counter */\n+#define TXGBE_LANPKTDROP 0x0151C0\n+#define TXGBE_MNGPKTDROP 0x0151C4\n+\n+/* MAC Counter */\n+#define TXGBE_MACRXERRCRCL 0x011928\n+#define TXGBE_MACRXERRCRCH 0x01192C\n+#define TXGBE_MACRXERRLENL 0x011978\n+#define TXGBE_MACRXERRLENH 0x01197C\n+#define TXGBE_MACRX1to64L 0x001940\n+#define TXGBE_MACRX1to64H 0x001944\n+#define TXGBE_MACRX65to127L 0x001948\n+#define TXGBE_MACRX65to127H 0x00194C\n+#define TXGBE_MACRX128to255L 0x001950\n+#define TXGBE_MACRX128to255H 0x001954\n+#define TXGBE_MACRX256to511L 0x001958\n+#define TXGBE_MACRX256to511H 0x00195C\n+#define TXGBE_MACRX512to1023L 0x001960\n+#define TXGBE_MACRX512to1023H 0x001964\n+#define TXGBE_MACRX1024toMAXL 0x001968\n+#define TXGBE_MACRX1024toMAXH 0x00196C\n+#define TXGBE_MACTX1to64L 0x001834\n+#define TXGBE_MACTX1to64H 0x001838\n+#define TXGBE_MACTX65to127L 0x00183C\n+#define TXGBE_MACTX65to127H 0x001840\n+#define TXGBE_MACTX128to255L 0x001844\n+#define TXGBE_MACTX128to255H 0x001848\n+#define TXGBE_MACTX256to511L 0x00184C\n+#define TXGBE_MACTX256to511H 0x001850\n+#define TXGBE_MACTX512to1023L 0x001854\n+#define TXGBE_MACTX512to1023H 0x001858\n+#define TXGBE_MACTX1024toMAXL 0x00185C\n+#define TXGBE_MACTX1024toMAXH 0x001860\n+\n+#define TXGBE_MACRXUNDERSIZE 0x011938\n+#define TXGBE_MACRXOVERSIZE 0x01193C\n+#define TXGBE_MACRXJABBER 0x011934\n+\n+#define TXGBE_MACRXPKTL 0x011900\n+#define TXGBE_MACRXPKTH 0x011904\n+#define TXGBE_MACTXPKTL 0x01181C\n+#define TXGBE_MACTXPKTH 0x011820\n+#define TXGBE_MACRXGBOCTL 0x011908\n+#define TXGBE_MACRXGBOCTH 0x01190C\n+#define TXGBE_MACTXGBOCTL 0x011814\n+#define TXGBE_MACTXGBOCTH 0x011818\n+\n+#define TXGBE_MACRXOCTL 0x011918\n+#define TXGBE_MACRXOCTH 0x01191C\n+#define TXGBE_MACRXMPKTL 0x011920\n+#define TXGBE_MACRXMPKTH 0x011924\n+#define TXGBE_MACTXOCTL 0x011824\n+#define TXGBE_MACTXOCTH 0x011828\n+#define TXGBE_MACTXMPKTL 0x01182C\n+#define TXGBE_MACTXMPKTH 0x011830\n+\n+/* Management Counter */\n+#define TXGBE_MNGOUT 0x01CF00\n+#define TXGBE_MNGIN 0x01CF04\n+\n+/* MAC SEC Counter */\n+#define TXGBE_LSECRXUNTAG 0x017240\n+#define TXGBE_LSECRXDECOCT 0x017244\n+#define TXGBE_LSECRXVLDOCT 0x017248\n+#define TXGBE_LSECRXBADTAG 0x01724C\n+#define TXGBE_LSECRXNOSCI 0x017250\n+#define TXGBE_LSECRXUKSCI 0x017254\n+#define TXGBE_LSECRXUNCHK 0x017258\n+#define TXGBE_LSECRXDLY 0x01725C\n+#define TXGBE_LSECRXLATE 0x017260\n+#define TXGBE_LSECRXGOOD 0x017264\n+#define TXGBE_LSECRXBAD 0x01726C\n+#define TXGBE_LSECRXUK 0x017274\n+#define TXGBE_LSECRXBADSA 0x01727C\n+#define TXGBE_LSECRXUKSA 0x017280\n+#define TXGBE_LSECTXUNTAG 0x01D23C\n+#define TXGBE_LSECTXENC 0x01D240\n+#define TXGBE_LSECTXPTT 0x01D244\n+#define TXGBE_LSECTXENCOCT 0x01D248\n+#define TXGBE_LSECTXPTTOCT 0x01D24C\n+\n+/* IP SEC Counter */\n+\n+/* FDIR Counter */\n+#define TXGBE_FDIRFREE 0x019538\n+#define TXGBE_FDIRFREE_FLT(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_FDIRLEN 0x01954C\n+#define TXGBE_FDIRLEN_BKTLEN(r) RS(r, 0, 0x3F)\n+#define TXGBE_FDIRLEN_MAXLEN(r) RS(r, 8, 0x3F)\n+#define TXGBE_FDIRUSED 0x019550\n+#define TXGBE_FDIRUSED_ADD(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_FDIRUSED_REM(r) RS(r, 16, 0xFFFF)\n+#define TXGBE_FDIRFAIL 0x019554\n+#define TXGBE_FDIRFAIL_ADD(r) RS(r, 0, 0xFF)\n+#define TXGBE_FDIRFAIL_REM(r) RS(r, 8, 0xFF)\n+#define TXGBE_FDIRMATCH 0x019558\n+#define TXGBE_FDIRMISS 0x01955C\n+\n+/* FCOE Counter */\n+#define TXGBE_FCOECRC 0x015160\n+#define TXGBE_FCOERPDC 0x012514\n+#define TXGBE_FCOELAST 0x012518\n+#define TXGBE_FCOEPRC 0x015164\n+#define TXGBE_FCOEDWRC 0x015168\n+#define TXGBE_FCOEPTC 0x018318\n+#define TXGBE_FCOEDWTC 0x01831C\n+\n+/* Management Counter */\n+#define TXGBE_MNGOS2BMC 0x01E094\n+#define TXGBE_MNGBMC2OS 0x01E090\n+\n+/******************************************************************************\n+ * PF(Physical Function) Registers\n+ ******************************************************************************/\n+/* Interrupt */\n+#define TXGBE_ICRMISC 0x000100\n+#define TXGBE_ICRMISC_MASK MS(8, 0xFFFFFF)\n+#define TXGBE_ICRMISC_LNKDN MS(8, 0x1) /* eth link down */\n+#define TXGBE_ICRMISC_RST MS(10, 0x1) /* device reset event */\n+#define TXGBE_ICRMISC_TS MS(11, 0x1) /* time sync */\n+#define TXGBE_ICRMISC_STALL MS(12, 0x1) /* trans or recv path is stalled */\n+#define TXGBE_ICRMISC_LNKSEC MS(13, 0x1) /* Tx LinkSec require key exchange */\n+#define TXGBE_ICRMISC_ERRBUF MS(14, 0x1) /* Packet Buffer Overrun */\n+#define TXGBE_ICRMISC_FDIR MS(15, 0x1) /* FDir Exception */\n+#define TXGBE_ICRMISC_I2C MS(16, 0x1) /* I2C interrupt */\n+#define TXGBE_ICRMISC_ERRMAC MS(17, 0x1) /* err reported by MAC */\n+#define TXGBE_ICRMISC_LNKUP MS(18, 0x1) /* link up */\n+#define TXGBE_ICRMISC_ANDONE MS(19, 0x1) /* link auto-nego done */\n+#define TXGBE_ICRMISC_ERRIG MS(20, 0x1) /* integrity error */\n+#define TXGBE_ICRMISC_SPI MS(21, 0x1) /* SPI interface */\n+#define TXGBE_ICRMISC_VFMBX MS(22, 0x1) /* VF-PF message box */\n+#define TXGBE_ICRMISC_GPIO MS(26, 0x1) /* GPIO interrupt */\n+#define TXGBE_ICRMISC_ERRPCI MS(27, 0x1) /* pcie request error */\n+#define TXGBE_ICRMISC_HEAT MS(28, 0x1) /* overheat detection */\n+#define TXGBE_ICRMISC_PROBE MS(29, 0x1) /* probe match */\n+#define TXGBE_ICRMISC_MNGMBX MS(30, 0x1) /* mng mailbox */\n+#define TXGBE_ICRMISC_TIMER MS(31, 0x1) /* tcp timer */\n+#define TXGBE_ICRMISC_DEFAULT ( \\\n+\t\t\tTXGBE_ICRMISC_LNKDN | \\\n+\t\t\tTXGBE_ICRMISC_RST | \\\n+\t\t\tTXGBE_ICRMISC_ERRMAC | \\\n+\t\t\tTXGBE_ICRMISC_LNKUP | \\\n+\t\t\tTXGBE_ICRMISC_ANDONE | \\\n+\t\t\tTXGBE_ICRMISC_ERRIG | \\\n+\t\t\tTXGBE_ICRMISC_VFMBX | \\\n+\t\t\tTXGBE_ICRMISC_MNGMBX | \\\n+\t\t\tTXGBE_ICRMISC_STALL | \\\n+\t\t\tTXGBE_ICRMISC_TIMER)\n+#define TXGBE_ICRMISC_LSC ( \\\n+\t\t\tTXGBE_ICRMISC_LNKDN | \\\n+\t\t\tTXGBE_ICRMISC_LNKUP)\n+#define TXGBE_ICSMISC 0x000104\n+#define TXGBE_IENMISC 0x000108\n+#define TXGBE_IVARMISC 0x0004FC\n+#define TXGBE_IVARMISC_VEC(v) LS(v, 0, 0x7)\n+#define TXGBE_IVARMISC_VLD MS(7, 0x1)\n+#define TXGBE_ICR(i) (0x000120 + (i) * 4) /* 0-1 */\n+#define TXGBE_ICR_MASK MS(0, 0xFFFFFFFF)\n+#define TXGBE_ICS(i) (0x000130 + (i) * 4) /* 0-1 */\n+#define TXGBE_ICS_MASK TXGBE_ICR_MASK\n+#define TXGBE_IMS(i) (0x000140 + (i) * 4) /* 0-1 */\n+#define TXGBE_IMS_MASK TXGBE_ICR_MASK\n+#define TXGBE_IMC(i) (0x000150 + (i) * 4) /* 0-1 */\n+#define TXGBE_IMC_MASK TXGBE_ICR_MASK\n+#define TXGBE_IVAR(i) (0x000500 + (i) * 4) /* 0-3 */\n+#define TXGBE_IVAR_VEC(v) LS(v, 0, 0x7)\n+#define TXGBE_IVAR_VLD MS(7, 0x1)\n+#define TXGBE_TCPTMR 0x000170\n+#define TXGBE_ITRSEL 0x000180\n+\n+/* P2V Mailbox */\n+#define TXGBE_MBMEM(i) (0x005000 + 0x40 * (i)) /* 0-63 */\n+#define TXGBE_MBCTL(i) (0x000600 + 4 * (i)) /* 0-63 */\n+#define TXGBE_MBCTL_STS MS(0, 0x1) /* Initiate message send to VF */\n+#define TXGBE_MBCTL_ACK MS(1, 0x1) /* Ack message recv'd from VF */\n+#define TXGBE_MBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */\n+#define TXGBE_MBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */\n+#define TXGBE_MBCTL_RVFU MS(4, 0x1) /* Reset VFU - used when VF stuck */\n+#define TXGBE_MBVFICR(i) (0x000480 + 4 * (i)) /* 0-3 */\n+#define TXGBE_MBVFICR_INDEX(vf) ((vf) >> 4)\n+#define TXGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */\n+#define TXGBE_MBVFICR_VFREQ_VF1 (0x00000001) /* bit for VF 1 message */\n+#define TXGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */\n+#define TXGBE_MBVFICR_VFACK_VF1 (0x00010000) /* bit for VF 1 ack */\n+#define TXGBE_FLRVFP(i) (0x000490 + 4 * (i)) /* 0-1 */\n+#define TXGBE_FLRVFE(i) (0x0004A0 + 4 * (i)) /* 0-1 */\n+#define TXGBE_FLRVFEC(i) (0x0004A8 + 4 * (i)) /* 0-1 */\n+\n+/******************************************************************************\n+ * VF(Virtual Function) Registers\n+ ******************************************************************************/\n+#define TXGBE_VFPBWRAP 0x000000\n+#define TXGBE_VFPBWRAP_WRAP(r, tc) ((0x7 << 4 * (tc) & (r)) >> 4 * (tc))\n+#define TXGBE_VFPBWRAP_EMPT(r, tc) ((0x8 << 4 * (tc) & (r)) >> 4 * (tc))\n+#define TXGBE_VFSTATUS 0x000004\n+#define TXGBE_VFSTATUS_UP MS(0, 0x1)\n+#define TXGBE_VFSTATUS_BW_MASK MS(1, 0x7)\n+#define TXGBE_VFSTATUS_BW_10G LS(0x1, 1, 0x7)\n+#define TXGBE_VFSTATUS_BW_1G LS(0x2, 1, 0x7)\n+#define TXGBE_VFSTATUS_BW_100M LS(0x4, 1, 0x7)\n+#define TXGBE_VFSTATUS_BUSY MS(4, 0x1)\n+#define TXGBE_VFSTATUS_LANID MS(8, 0x1)\n+#define TXGBE_VFRST 0x000008\n+#define TXGBE_VFRST_SET MS(0, 0x1)\n+#define TXGBE_VFPLCFG 0x000078\n+#define TXGBE_VFPLCFG_RSV MS(0, 0x1)\n+#define TXGBE_VFPLCFG_PSR(v) LS(v, 1, 0x1F)\n+#define TXGBE_VFPLCFG_PSRL4HDR (0x1)\n+#define TXGBE_VFPLCFG_PSRL3HDR (0x2)\n+#define TXGBE_VFPLCFG_PSRL2HDR (0x4)\n+#define TXGBE_VFPLCFG_PSRTUNHDR (0x8)\n+#define TXGBE_VFPLCFG_PSRTUNMAC (0x10)\n+#define TXGBE_VFPLCFG_RSSMASK MS(16, 0xFF)\n+#define TXGBE_VFPLCFG_RSSIPV4TCP MS(16, 0x1)\n+#define TXGBE_VFPLCFG_RSSIPV4 MS(17, 0x1)\n+#define TXGBE_VFPLCFG_RSSIPV6 MS(20, 0x1)\n+#define TXGBE_VFPLCFG_RSSIPV6TCP MS(21, 0x1)\n+#define TXGBE_VFPLCFG_RSSIPV4UDP MS(22, 0x1)\n+#define TXGBE_VFPLCFG_RSSIPV6UDP MS(23, 0x1)\n+#define TXGBE_VFPLCFG_RSSENA MS(24, 0x1)\n+#define TXGBE_VFPLCFG_RSSHASH(v) LS(v, 29, 0x7)\n+#define TXGBE_VFRSSKEY(i) (0x000080 + (i) * 4) /* 0-9 */\n+#define TXGBE_VFRSSTBL(i) (0x0000C0 + (i) * 4) /* 0-15 */\n+#define TXGBE_VFICR 0x000100\n+#define TXGBE_VFICR_MASK LS(7, 0, 0x7)\n+#define TXGBE_VFICR_MBX MS(0, 0x1)\n+#define TXGBE_VFICR_DONE1 MS(1, 0x1)\n+#define TXGBE_VFICR_DONE2 MS(2, 0x1)\n+#define TXGBE_VFICS 0x000104\n+#define TXGBE_VFICS_MASK TXGBE_VFICR_MASK\n+#define TXGBE_VFIMS 0x000108\n+#define TXGBE_VFIMS_MASK TXGBE_VFICR_MASK\n+#define TXGBE_VFIMC 0x00010C\n+#define TXGBE_VFIMC_MASK TXGBE_VFICR_MASK\n+#define TXGBE_VFGPIE 0x000118\n+#define TXGBE_VFIVAR(i) (0x000240 + 4 * (i)) /* 0-3 */\n+#define TXGBE_VFIVARMISC 0x000260\n+#define TXGBE_VFIVAR_ALLOC(v) LS(v, 0, 0x3)\n+#define TXGBE_VFIVAR_VLD MS(7, 0x1)\n+\n+#define TXGBE_VFMBCTL 0x000600\n+#define TXGBE_VFMBCTL_REQ MS(0, 0x1) /* Request for PF Ready bit */\n+#define TXGBE_VFMBCTL_ACK MS(1, 0x1) /* Ack PF message received */\n+#define TXGBE_VFMBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */\n+#define TXGBE_VFMBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */\n+#define TXGBE_VFMBCTL_PFSTS MS(4, 0x1) /* PF wrote a message in the MB */\n+#define TXGBE_VFMBCTL_PFACK MS(5, 0x1) /* PF ack the previous VF msg */\n+#define TXGBE_VFMBCTL_RSTI MS(6, 0x1) /* PF has reset indication */\n+#define TXGBE_VFMBCTL_RSTD MS(7, 0x1) /* PF has indicated reset done */\n+#define TXGBE_VFMBCTL_R2C_BITS (TXGBE_VFMBCTL_RSTD | \\\n+\t\t\t\t\t TXGBE_VFMBCTL_PFSTS | \\\n+\t\t\t\t\t TXGBE_VFMBCTL_PFACK)\n+#define TXGBE_VFMBX 0x000C00 /* 0-15 */\n+#define TXGBE_VFTPHCTL(i) (0x000D00 + 4 * (i)) /* 0-7 */\n+\n+/******************************************************************************\n+ * PF&VF TxRx Interface\n+ ******************************************************************************/\n+#define RNGLEN(v) ROUND_OVER(v, 13, 7)\n+#define HDRLEN(v) ROUND_OVER(v, 10, 6)\n+#define PKTLEN(v) ROUND_OVER(v, 14, 10)\n+#define INTTHR(v) ROUND_OVER(v, 4, 0)\n+\n+#define\tTXGBE_RING_DESC_ALIGN\t128\n+#define\tTXGBE_RING_DESC_MIN\t128\n+#define\tTXGBE_RING_DESC_MAX\t8192\n+#define TXGBE_RXD_ALIGN\t\tTXGBE_RING_DESC_ALIGN\n+#define TXGBE_TXD_ALIGN\t\tTXGBE_RING_DESC_ALIGN\n+\n+/* receive ring */\n+#define TXGBE_RXBAL(rp) (0x001000 + 0x40 * (rp))\n+#define TXGBE_RXBAH(rp) (0x001004 + 0x40 * (rp))\n+#define TXGBE_RXRP(rp) (0x00100C + 0x40 * (rp))\n+#define TXGBE_RXWP(rp) (0x001008 + 0x40 * (rp))\n+#define TXGBE_RXCFG(rp) (0x001010 + 0x40 * (rp))\n+#define TXGBE_RXCFG_ENA MS(0, 0x1)\n+#define TXGBE_RXCFG_RNGLEN(v) LS(RNGLEN(v), 1, 0x3F)\n+#define TXGBE_RXCFG_PKTLEN(v) LS(PKTLEN(v), 8, 0xF)\n+#define TXGBE_RXCFG_PKTLEN_MASK MS(8, 0xF)\n+#define TXGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF)\n+#define TXGBE_RXCFG_HDRLEN_MASK MS(12, 0xF)\n+#define TXGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7)\n+#define TXGBE_RXCFG_ETAG MS(22, 0x1)\n+#define TXGBE_RXCFG_RSCMAX_MASK MS(23, 0x3)\n+#define TXGBE_RXCFG_RSCMAX_1 LS(0, 23, 0x3)\n+#define TXGBE_RXCFG_RSCMAX_4 LS(1, 23, 0x3)\n+#define TXGBE_RXCFG_RSCMAX_8 LS(2, 23, 0x3)\n+#define TXGBE_RXCFG_RSCMAX_16 LS(3, 23, 0x3)\n+#define TXGBE_RXCFG_STALL MS(25, 0x1)\n+#define TXGBE_RXCFG_SPLIT MS(26, 0x1)\n+#define TXGBE_RXCFG_RSCMODE MS(27, 0x1)\n+#define TXGBE_RXCFG_CNTAG MS(28, 0x1)\n+#define TXGBE_RXCFG_RSCENA MS(29, 0x1)\n+#define TXGBE_RXCFG_DROP MS(30, 0x1)\n+#define TXGBE_RXCFG_VLAN MS(31, 0x1)\n+\n+/* transmit ring */\n+#define TXGBE_TXBAL(rp) (0x003000 + 0x40 * (rp))\n+#define TXGBE_TXBAH(rp) (0x003004 + 0x40 * (rp))\n+#define TXGBE_TXWP(rp) (0x003008 + 0x40 * (rp))\n+#define TXGBE_TXRP(rp) (0x00300C + 0x40 * (rp))\n+#define TXGBE_TXCFG(rp) (0x003010 + 0x40 * (rp))\n+#define TXGBE_TXCFG_ENA MS(0, 0x1)\n+#define TXGBE_TXCFG_BUFLEN_MASK MS(1, 0x3F)\n+#define TXGBE_TXCFG_BUFLEN(v) LS(RNGLEN(v), 1, 0x3F)\n+#define TXGBE_TXCFG_HTHRESH_MASK MS(8, 0xF)\n+#define TXGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF)\n+#define TXGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F)\n+#define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F)\n+#define TXGBE_TXCFG_FLUSH MS(26, 0x1)\n+\n+/* interrupt registers */\n+#define TXGBE_ITRI 0x000180\n+#define TXGBE_ITR(i) (0x000200 + 4 * (i))\n+#define TXGBE_ITR_IVAL_MASK MS(2, 0x3FE)\n+#define TXGBE_ITR_IVAL(v) LS(v, 2, 0x3FE)\n+#define TXGBE_ITR_IVAL_1G(us) TXGBE_ITR_IVAL((us) / 2)\n+#define TXGBE_ITR_IVAL_10G(us) TXGBE_ITR_IVAL((us) / 20)\n+#define TXGBE_ITR_LLIEA MS(15, 0x1)\n+#define TXGBE_ITR_LLICREDIT(v) LS(v, 16, 0x1F)\n+#define TXGBE_ITR_CNT(v) LS(v, 21, 0x7F)\n+#define TXGBE_ITR_WRDSA MS(31, 0x1)\n+#define TXGBE_GPIE 0x000118\n+#define TXGBE_GPIE_MSIX MS(0, 0x1)\n+#define TXGBE_GPIE_LLIEA MS(1, 0x1)\n+#define TXGBE_GPIE_LLIVAL(v) LS(v, 4, 0xF)\n+#define TXGBE_GPIE_RSCDLY(v) LS(v, 8, 0x7)\n+\n+/******************************************************************************\n+ * Debug Registers\n+ ******************************************************************************/\n+/**\n+ * Probe\n+ **/\n+#define TXGBE_PROB 0x010010\n+#define TXGBE_IODRV 0x010024\n+\n+#define TXGBE_PRBCTL 0x010200\n+#define TXGBE_PRBSTA 0x010204\n+#define TXGBE_PRBDAT 0x010220\n+#define TXGBE_PRBPTN 0x010224\n+#define TXGBE_PRBCNT 0x010228\n+#define TXGBE_PRBMSK 0x01022C\n+\n+#define TXGBE_PRBPCI 0x01F010\n+#define TXGBE_PRBRDMA 0x012010\n+#define TXGBE_PRBTDMA 0x018010\n+#define TXGBE_PRBPSR 0x015010\n+#define TXGBE_PRBRDB 0x019010\n+#define TXGBE_PRBTDB 0x01C010\n+#define TXGBE_PRBRSEC 0x017010\n+#define TXGBE_PRBTSEC 0x01D010\n+#define TXGBE_PRBMNG 0x01E010\n+#define TXGBE_PRBRMAC 0x011014\n+#define TXGBE_PRBTMAC 0x011010\n+#define TXGBE_PRBREMAC 0x011E04\n+#define TXGBE_PRBTEMAC 0x011E00\n+\n+/**\n+ * ECC\n+ **/\n+#define TXGBE_ECCRXDMACTL 0x012014\n+#define TXGBE_ECCRXDMAINJ 0x012018\n+#define TXGBE_ECCRXDMA 0x01201C\n+#define TXGBE_ECCTXDMACTL 0x018014\n+#define TXGBE_ECCTXDMAINJ 0x018018\n+#define TXGBE_ECCTXDMA 0x01801C\n+\n+#define TXGBE_ECCRXPBCTL 0x019014\n+#define TXGBE_ECCRXPBINJ 0x019018\n+#define TXGBE_ECCRXPB 0x01901C\n+#define TXGBE_ECCTXPBCTL 0x01C014\n+#define TXGBE_ECCTXPBINJ 0x01C018\n+#define TXGBE_ECCTXPB 0x01C01C\n+\n+#define TXGBE_ECCRXETHCTL 0x015014\n+#define TXGBE_ECCRXETHINJ 0x015018\n+#define TXGBE_ECCRXETH 0x01401C\n+\n+#define TXGBE_ECCRXSECCTL 0x017014\n+#define TXGBE_ECCRXSECINJ 0x017018\n+#define TXGBE_ECCRXSEC 0x01701C\n+#define TXGBE_ECCTXSECCTL 0x01D014\n+#define TXGBE_ECCTXSECINJ 0x01D018\n+#define TXGBE_ECCTXSEC 0x01D01C\n+\n+/**\n+ * Inspection\n+ **/\n+#define TXGBE_PBLBSTAT 0x01906C\n+#define TXGBE_PBLBSTAT_FREE(r) RS(r, 0, 0x3FF)\n+#define TXGBE_PBLBSTAT_FULL MS(11, 0x1)\n+#define TXGBE_PBRXSTAT 0x019004\n+#define TXGBE_PBRXSTAT_WRAP(tc, r) ((7u << 4 * (tc) & (r)) >> 4 * (tc))\n+#define TXGBE_PBRXSTAT_EMPT(tc, r) ((8u << 4 * (tc) & (r)) >> 4 * (tc))\n+#define TXGBE_PBRXSTAT2(tc) (0x019180 + (tc) * 4)\n+#define TXGBE_PBRXSTAT2_USED(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_PBRXWRPTR(tc) (0x019180 + (tc) * 4)\n+#define TXGBE_PBRXWRPTR_HEAD(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_PBRXWRPTR_TAIL(r) RS(r, 16, 0xFFFF)\n+#define TXGBE_PBRXRDPTR(tc) (0x0191A0 + (tc) * 4)\n+#define TXGBE_PBRXRDPTR_HEAD(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_PBRXRDPTR_TAIL(r) RS(r, 16, 0xFFFF)\n+#define TXGBE_PBRXDATA(tc) (0x0191C0 + (tc) * 4)\n+#define TXGBE_PBRXDATA_RDPTR(r) RS(r, 0, 0xFFFF)\n+#define TXGBE_PBRXDATA_WRPTR(r) RS(r, 16, 0xFFFF)\n+#define TXGBE_PBTXSTAT 0x01C004\n+#define TXGBE_PBTXSTAT_EMPT(tc, r) ((1 << (tc) & (r)) >> (tc))\n+\n+#define TXGBE_RXPBPFCDMACL 0x019210\n+#define TXGBE_RXPBPFCDMACH 0x019214\n+\n+#define TXGBE_PSRLANPKTCNT 0x0151B8\n+#define TXGBE_PSRMNGPKTCNT 0x0151BC\n+\n+#define TXGBE_P2VMBX_SIZE (16) /* 16*4B */\n+#define TXGBE_P2MMBX_SIZE (64) /* 64*4B */\n+\n+/**************** Global Registers ****************************/\n+/* chip control Registers */\n+#define TXGBE_PWR 0x010000\n+#define TXGBE_PWR_LANID(r) RS(r, 30, 0x3)\n+#define TXGBE_PWR_LANID_SWAP LS(2, 30, 0x3)\n+\n+/* Sensors for PVT(Process Voltage Temperature) */\n+#define TXGBE_TSCTRL 0x010300\n+#define TXGBE_TSCTRL_EVALMD MS(31, 0x1)\n+#define TXGBE_TSEN 0x010304\n+#define TXGBE_TSEN_ENA MS(0, 0x1)\n+#define TXGBE_TSSTAT 0x010308\n+#define TXGBE_TSSTAT_VLD MS(16, 0x1)\n+#define TXGBE_TSSTAT_DATA(r) RS(r, 0, 0x3FF)\n+\n+#define TXGBE_TSATHRE 0x01030C\n+#define TXGBE_TSDTHRE 0x010310\n+#define TXGBE_TSINTR 0x010314\n+#define TXGBE_TSINTR_AEN MS(0, 0x1)\n+#define TXGBE_TSINTR_DEN MS(1, 0x1)\n+#define TXGBE_TS_ALARM_ST 0x10318\n+#define TXGBE_TS_ALARM_ST_DALARM 0x00000002U\n+#define TXGBE_TS_ALARM_ST_ALARM 0x00000001U\n+\n+/* FMGR Registers */\n+#define TXGBE_ILDRSTAT 0x010120\n+#define TXGBE_ILDRSTAT_PCIRST MS(0, 0x1)\n+#define TXGBE_ILDRSTAT_PWRRST MS(1, 0x1)\n+#define TXGBE_ILDRSTAT_SWRST MS(7, 0x1)\n+#define TXGBE_ILDRSTAT_SWRST_LAN0 MS(9, 0x1)\n+#define TXGBE_ILDRSTAT_SWRST_LAN1 MS(10, 0x1)\n+\n+#define TXGBE_SPISTAT 0x01010C\n+#define TXGBE_SPISTAT_OPDONE MS(0, 0x1)\n+#define TXGBE_SPISTAT_BPFLASH MS(31, 0x1)\n+\n+/************************* Port Registers ************************************/\n+/* I2C registers */\n+#define TXGBE_I2CCON 0x014900 /* I2C Control */\n+#define TXGBE_I2CCON_SDIA ((1 << 6))\n+#define TXGBE_I2CCON_RESTART ((1 << 5))\n+#define TXGBE_I2CCON_M10BITADDR ((1 << 4))\n+#define TXGBE_I2CCON_S10BITADDR ((1 << 3))\n+#define TXGBE_I2CCON_SPEED(v) (((v) & 0x3) << 1)\n+#define TXGBE_I2CCON_MENA ((1 << 0))\n+#define TXGBE_I2CTAR 0x014904 /* I2C Target Address */\n+#define TXGBE_I2CDATA 0x014910 /* I2C Rx/Tx Data Buf and Cmd */\n+#define TXGBE_I2CDATA_STOP ((1 << 9))\n+#define TXGBE_I2CDATA_READ ((1 << 8) | TXGBE_I2CDATA_STOP)\n+#define TXGBE_I2CDATA_WRITE ((0 << 8) | TXGBE_I2CDATA_STOP)\n+#define TXGBE_I2CSSSCLHCNT 0x014914 /* Standard speed I2C Clock SCL High Count */\n+#define TXGBE_I2CSSSCLLCNT 0x014918 /* Standard speed I2C Clock SCL Low Count */\n+#define TXGBE_I2CICR 0x014934 /* I2C Raw Interrupt Status */\n+#define TXGBE_I2CICR_RXFULL ((0x1) << 2)\n+#define TXGBE_I2CICR_TXEMPTY ((0x1) << 4)\n+#define TXGBE_I2CICM 0x014930 /* I2C Interrupt Mask */\n+#define TXGBE_I2CRXTL 0x014938 /* I2C Receive FIFO Threshold */\n+#define TXGBE_I2CTXTL 0x01493C /* I2C TX FIFO Threshold */\n+#define TXGBE_I2CENA 0x01496C /* I2C Enable */\n+#define TXGBE_I2CSTAT 0x014970 /* I2C Status register */\n+#define TXGBE_I2CSTAT_MST ((1U << 5))\n+#define TXGBE_I2CSCLTMOUT 0x0149AC /* I2C SCL stuck at low timeout register */\n+#define TXGBE_I2CSDATMOUT 0x0149B0 /*I2C SDA Stuck at Low Timeout*/\n+\n+/* port cfg Registers */\n+#define TXGBE_PORTSTAT 0x014404\n+#define TXGBE_PORTSTAT_UP MS(0, 0x1)\n+#define TXGBE_PORTSTAT_BW_MASK MS(1, 0x7)\n+#define TXGBE_PORTSTAT_BW_10G MS(1, 0x1)\n+#define TXGBE_PORTSTAT_BW_1G MS(2, 0x1)\n+#define TXGBE_PORTSTAT_BW_100M MS(3, 0x1)\n+#define TXGBE_PORTSTAT_ID(r) RS(r, 8, 0x1)\n+\n+#define TXGBE_VXLAN 0x014410\n+#define TXGBE_VXLAN_GPE 0x014414\n+#define TXGBE_GENEVE 0x014418\n+#define TXGBE_TEREDO 0x01441C\n+#define TXGBE_TCPTIME 0x014420\n+\n+/* GPIO Registers */\n+#define TXGBE_GPIODATA 0x014800\n+#define TXGBE_GPIOBIT_0 MS(0, 0x1) /* O:tx fault */\n+#define TXGBE_GPIOBIT_1 MS(1, 0x1) /* O:tx disabled */\n+#define TXGBE_GPIOBIT_2 MS(2, 0x1) /* I:sfp module absent */\n+#define TXGBE_GPIOBIT_3 MS(3, 0x1) /* I:rx signal lost */\n+#define TXGBE_GPIOBIT_4 MS(4, 0x1) /* O:rate select, 1G(0) 10G(1) */\n+#define TXGBE_GPIOBIT_5 MS(5, 0x1) /* O:rate select, 1G(0) 10G(1) */\n+#define TXGBE_GPIOBIT_6 MS(6, 0x1) /* I:ext phy interrupt */\n+#define TXGBE_GPIOBIT_7 MS(7, 0x1) /* I:fan speed alarm */\n+#define TXGBE_GPIODIR 0x014804\n+#define TXGBE_GPIOCTL 0x014808\n+#define TXGBE_GPIOINTEN 0x014830\n+#define TXGBE_GPIOINTMASK 0x014834\n+#define TXGBE_GPIOINTTYPE 0x014838\n+#define TXGBE_GPIOINTSTAT 0x014840\n+#define TXGBE_GPIOEOI 0x01484C\n+\n+\n+#define TXGBE_ARBPOOLIDX 0x01820C\n+#define TXGBE_ARBTXRATE 0x018404\n+#define TXGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF)\n+#define TXGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF)\n+\n+/* qos */\n+#define TXGBE_ARBTXCTL 0x018200\n+#define TXGBE_ARBTXCTL_RRM MS(1, 0x1)\n+#define TXGBE_ARBTXCTL_WSP MS(2, 0x1)\n+#define TXGBE_ARBTXCTL_DIA MS(6, 0x1)\n+#define TXGBE_ARBTXMMW 0x018208\n+\n+/**************************** Receive DMA registers **************************/\n+/* receive control */\n+#define TXGBE_ARBRXCTL 0x012000\n+#define TXGBE_ARBRXCTL_RRM MS(1, 0x1)\n+#define TXGBE_ARBRXCTL_WSP MS(2, 0x1)\n+#define TXGBE_ARBRXCTL_DIA MS(6, 0x1)\n+\n+#define TXGBE_RPUP2TC 0x019008\n+#define TXGBE_RPUP2TC_UP_SHIFT 3\n+#define TXGBE_RPUP2TC_UP_MASK 0x7\n+\n+/* mac switcher */\n+#define TXGBE_ETHADDRL 0x016200\n+#define TXGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF)\n+#define TXGBE_ETHADDRL_AD1(v) LS(v, 8, 0xFF)\n+#define TXGBE_ETHADDRL_AD2(v) LS(v, 16, 0xFF)\n+#define TXGBE_ETHADDRL_AD3(v) LS(v, 24, 0xFF)\n+#define TXGBE_ETHADDRL_ETAG(r) RS(r, 0, 0x3FFF)\n+#define TXGBE_ETHADDRH 0x016204\n+#define TXGBE_ETHADDRH_AD4(v) LS(v, 0, 0xFF)\n+#define TXGBE_ETHADDRH_AD5(v) LS(v, 8, 0xFF)\n+#define TXGBE_ETHADDRH_AD_MASK MS(0, 0xFFFF)\n+#define TXGBE_ETHADDRH_ETAG MS(30, 0x1)\n+#define TXGBE_ETHADDRH_VLD MS(31, 0x1)\n+#define TXGBE_ETHADDRASSL 0x016208\n+#define TXGBE_ETHADDRASSH 0x01620C\n+#define TXGBE_ETHADDRIDX 0x016210\n+\n+/* Outmost Barrier Filters */\n+#define TXGBE_MCADDRTBL(i) (0x015200 + (i) * 4) /* 0-127 */\n+#define TXGBE_UCADDRTBL(i) (0x015400 + (i) * 4) /* 0-127 */\n+#define TXGBE_VLANTBL(i) (0x016000 + (i) * 4) /* 0-127 */\n+\n+#define TXGBE_MNGFLEXSEL 0x1582C\n+#define TXGBE_MNGFLEXDWL(i) (0x15A00 + ((i) * 16))\n+#define TXGBE_MNGFLEXDWH(i) (0x15A04 + ((i) * 16))\n+#define TXGBE_MNGFLEXMSK(i) (0x15A08 + ((i) * 16))\n+\n+#define TXGBE_LANFLEXSEL 0x15B8C\n+#define TXGBE_LANFLEXDWL(i) (0x15C00 + ((i) * 16))\n+#define TXGBE_LANFLEXDWH(i) (0x15C04 + ((i) * 16))\n+#define TXGBE_LANFLEXMSK(i) (0x15C08 + ((i) * 16))\n+#define TXGBE_LANFLEXCTL 0x15CFC\n+\n+/* ipsec */\n+#define TXGBE_IPSRXIDX 0x017100\n+#define TXGBE_IPSRXIDX_ENA MS(0, 0x1)\n+#define TXGBE_IPSRXIDX_TB_MASK MS(1, 0x3)\n+#define TXGBE_IPSRXIDX_TB_IP LS(1, 1, 0x3)\n+#define TXGBE_IPSRXIDX_TB_SPI LS(2, 1, 0x3)\n+#define TXGBE_IPSRXIDX_TB_KEY LS(3, 1, 0x3)\n+#define TXGBE_IPSRXIDX_TBIDX(v) LS(v, 3, 0x3FF)\n+#define TXGBE_IPSRXIDX_READ MS(30, 0x1)\n+#define TXGBE_IPSRXIDX_WRITE MS(31, 0x1)\n+#define TXGBE_IPSRXADDR(i) (0x017104 + (i) * 4)\n+\n+#define TXGBE_IPSRXSPI 0x017114\n+#define TXGBE_IPSRXADDRIDX 0x017118\n+#define TXGBE_IPSRXKEY(i) (0x01711C + (i) * 4)\n+#define TXGBE_IPSRXSALT 0x01712C\n+#define TXGBE_IPSRXMODE 0x017130\n+#define TXGBE_IPSRXMODE_IPV6 0x00000010\n+#define TXGBE_IPSRXMODE_DEC 0x00000008\n+#define TXGBE_IPSRXMODE_ESP 0x00000004\n+#define TXGBE_IPSRXMODE_AH 0x00000002\n+#define TXGBE_IPSRXMODE_VLD 0x00000001\n+#define TXGBE_IPSTXIDX 0x01D100\n+#define TXGBE_IPSTXIDX_ENA MS(0, 0x1)\n+#define TXGBE_IPSTXIDX_SAIDX(v) LS(v, 3, 0x3FF)\n+#define TXGBE_IPSTXIDX_READ MS(30, 0x1)\n+#define TXGBE_IPSTXIDX_WRITE MS(31, 0x1)\n+#define TXGBE_IPSTXSALT 0x01D104\n+#define TXGBE_IPSTXKEY(i) (0x01D108 + (i) * 4)\n+\n+#define TXGBE_MACTXCFG 0x011000\n+#define TXGBE_MACTXCFG_TE MS(0, 0x1)\n+#define TXGBE_MACTXCFG_SPEED_MASK MS(29, 0x3)\n+#define TXGBE_MACTXCFG_SPEED(v) LS(v, 29, 0x3)\n+#define TXGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3)\n+#define TXGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3)\n+\n+#define TXGBE_ISBADDRL 0x000160\n+#define TXGBE_ISBADDRH 0x000164\n+\n+#define NVM_OROM_OFFSET\t\t0x17\n+#define NVM_OROM_BLK_LOW\t0x83\n+#define NVM_OROM_BLK_HI\t\t0x84\n+#define NVM_OROM_PATCH_MASK\t0xFF\n+#define NVM_OROM_SHIFT\t\t8\n+#define NVM_VER_MASK\t\t0x00FF /* version mask */\n+#define NVM_VER_SHIFT\t\t8 /* version bit shift */\n+#define NVM_OEM_PROD_VER_PTR\t0x1B /* OEM Product version block pointer */\n+#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */\n+#define NVM_OEM_PROD_VER_OFF_L\t0x2 /* OEM Product version offset low */\n+#define NVM_OEM_PROD_VER_OFF_H\t0x3 /* OEM Product version offset high */\n+#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */\n+#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */\n+#define NVM_ETK_OFF_LOW\t\t0x2D /* version low order word */\n+#define NVM_ETK_OFF_HI\t\t0x2E /* version high order word */\n+#define NVM_ETK_SHIFT\t\t16 /* high version word shift */\n+#define NVM_VER_INVALID\t\t0xFFFF\n+#define NVM_ETK_VALID\t\t0x8000\n+#define NVM_INVALID_PTR\t\t0xFFFF\n+#define NVM_VER_SIZE\t\t32 /* version sting size */\n+\n+#define TXGBE_REG_RSSTBL TXGBE_RSSTBL(0)\n+#define TXGBE_REG_RSSKEY TXGBE_RSSKEY(0)\n+\n+/**\n+ * register operations\n+ **/\n+#define TXGBE_REG_READ32(addr) rte_read32(addr)\n+#define TXGBE_REG_READ32_RELAXED(addr) rte_read32_relaxed(addr)\n+#define TXGBE_REG_WRITE32(addr, val) rte_write32(val, addr)\n+#define TXGBE_REG_WRITE32_RELAXED(addr, val) rte_write32_relaxed(val, addr)\n+\n+#define TXGBE_DEAD_READ_REG 0xdeadbeefU\n+#define TXGBE_FAILED_READ_REG 0xffffffffU\n+#define TXGBE_REG_ADDR(hw, reg) \\\n+\t((volatile u32 *)((char *)(hw)->hw_addr + (reg)))\n+\n+static inline u32\n+txgbe_get32(volatile u32 *addr)\n+{\n+\tu32 val = TXGBE_REG_READ32(addr);\n+\treturn rte_le_to_cpu_32(val);\n+}\n+\n+static inline void\n+txgbe_set32(volatile u32 *addr, u32 val)\n+{\n+\tval = rte_cpu_to_le_32(val);\n+\tTXGBE_REG_WRITE32(addr, val);\n+}\n+\n+static inline u32\n+txgbe_get32_masked(volatile u32 *addr, u32 mask)\n+{\n+\tu32 val = txgbe_get32(addr);\n+\tval &= mask;\n+\treturn val;\n+}\n+\n+static inline void\n+txgbe_set32_masked(volatile u32 *addr, u32 mask, u32 field)\n+{\n+\tu32 val = txgbe_get32(addr);\n+\tval = ((val & ~mask) | (field & mask));\n+\ttxgbe_set32(addr, val);\n+}\n+\n+static inline u32\n+txgbe_get32_relaxed(volatile u32 *addr)\n+{\n+\tu32 val = TXGBE_REG_READ32_RELAXED(addr);\n+\treturn rte_le_to_cpu_32(val);\n+}\n+\n+static inline void\n+txgbe_set32_relaxed(volatile u32 *addr, u32 val)\n+{\n+\tval = rte_cpu_to_le_32(val);\n+\tTXGBE_REG_WRITE32_RELAXED(addr, val);\n+\treturn;\n+}\n+\n+static inline u32\n+rd32(struct txgbe_hw *hw, u32 reg)\n+{\n+\tif (reg == TXGBE_REG_DUMMY)\n+\t\treturn 0;\n+\treturn txgbe_get32(TXGBE_REG_ADDR(hw, reg));\n+}\n+\n+static inline void\n+wr32(struct txgbe_hw *hw, u32 reg, u32 val)\n+{\n+\tif (reg == TXGBE_REG_DUMMY)\n+\t\treturn;\n+\ttxgbe_set32(TXGBE_REG_ADDR(hw, reg), val);\n+}\n+\n+static inline u32\n+rd32m(struct txgbe_hw *hw, u32 reg, u32 mask)\n+{\n+\tu32 val = rd32(hw, reg);\n+\tval &= mask;\n+\treturn val;\n+}\n+\n+static inline void\n+wr32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 field)\n+{\n+\tu32 val = rd32(hw, reg);\n+\tval = ((val & ~mask) | (field & mask));\n+\twr32(hw, reg, val);\n+}\n+\n+static inline u64\n+rd64(struct txgbe_hw *hw, u32 reg)\n+{\n+\tu64 lsb = rd32(hw, reg);\n+\tu64 msb = rd32(hw, reg + 4);\n+\treturn (lsb | msb << 32);\n+}\n+\n+static inline void\n+wr64(struct txgbe_hw *hw, u32 reg, u64 val)\n+{\n+\twr32(hw, reg, (u32)val);\n+\twr32(hw, reg + 4, (u32)(val >> 32));\n+}\n+\n+/* poll register */\n+static inline u32\n+po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,\n+\tu32 loop, u32 slice)\n+{\n+\tbool usec = true;\n+\tu32 value = 0, all = 0;\n+\n+\tif (slice > 1000 * MAX_UDELAY_MS) {\n+\t\tusec = false;\n+\t\tslice = (slice + 500) / 1000;\n+\t}\n+\n+\tdo {\n+\t\tall |= rd32(hw, reg);\n+\t\tvalue |= mask & all;\n+\t\tif (value == expect) {\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tusec ? usec_delay(slice) : msec_delay(slice);\n+\t} while (--loop > 0);\n+\n+\tif (actual) {\n+\t\t*actual = all;\n+\t}\n+\n+\treturn loop;\n+}\n+\n+/* flush all write operations */\n+#define txgbe_flush(hw) rd32(hw, 0x00100C)\n+\n+#define rd32a(hw, reg, idx) ( \\\n+\trd32((hw), (reg) + ((idx) << 2)))\n+#define wr32a(hw, reg, idx, val) \\\n+\twr32((hw), (reg) + ((idx) << 2), (val))\n+\n+#define rd32w(hw, reg, mask, slice) do { \\\n+\trd32((hw), reg); \\\n+\tpo32m((hw), reg, mask, mask, NULL, 5, slice); \\\n+} while (0)\n+\n+#define wr32w(hw, reg, val, mask, slice) do { \\\n+\twr32((hw), reg, val); \\\n+\tpo32m((hw), reg, mask, mask, NULL, 5, slice); \\\n+} while (0)\n+\n+#define TXGBE_XPCS_IDAADDR 0x13000\n+#define TXGBE_XPCS_IDADATA 0x13004\n+#define TXGBE_EPHY_IDAADDR 0x13008\n+#define TXGBE_EPHY_IDADATA 0x1300C\n+static inline u32\n+rd32_epcs(struct txgbe_hw *hw, u32 addr)\n+{\n+\tu32 data;\n+\twr32(hw, TXGBE_XPCS_IDAADDR, addr);\n+\tdata = rd32(hw, TXGBE_XPCS_IDADATA);\n+\treturn data;\n+}\n+\n+static inline void\n+wr32_epcs(struct txgbe_hw *hw, u32 addr, u32 data)\n+{\n+\twr32(hw, TXGBE_XPCS_IDAADDR, addr);\n+\twr32(hw, TXGBE_XPCS_IDADATA, data);\n+}\n+\n+static inline u32\n+rd32_ephy(struct txgbe_hw *hw, u32 addr)\n+{\n+\tu32 data;\n+\twr32(hw, TXGBE_EPHY_IDAADDR, addr);\n+\tdata = rd32(hw, TXGBE_EPHY_IDADATA);\n+\treturn data;\n+}\n+\n+static inline void\n+wr32_ephy(struct txgbe_hw *hw, u32 addr, u32 data)\n+{\n+\twr32(hw, TXGBE_EPHY_IDAADDR, addr);\n+\twr32(hw, TXGBE_EPHY_IDADATA, data);\n+}\n+\n+#endif /* _TXGBE_REGS_H_ */\ndiff --git a/drivers/net/txgbe/base/txgbe_status.h b/drivers/net/txgbe/base/txgbe_status.h\nnew file mode 100644\nindex 000000000..db5e521e4\n--- /dev/null\n+++ b/drivers/net/txgbe/base/txgbe_status.h\n@@ -0,0 +1,122 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015-2020\n+ */\n+\n+#ifndef _TXGBE_STATUS_H_\n+#define _TXGBE_STATUS_H_\n+\n+/* Error Codes:\n+ * common error\n+ * module error(simple)\n+ * module error(detailed)\n+ *\n+ * (-256, 256): reserved for non-txgbe defined error code\n+ */\n+#define TERR_BASE (0x100)\n+enum txgbe_error {\n+\tTERR_NULL = TERR_BASE,\n+\tTERR_ANY,\n+\tTERR_NOSUPP,\n+\tTERR_NOIMPL,\n+\tTERR_NOMEM,\n+\tTERR_NOSPACE,\n+\tTERR_NOENTRY,\n+\tTERR_CONFIG,\n+\tTERR_ARGS,\n+\tTERR_PARAM,\n+\tTERR_INVALID,\n+\tTERR_TIMEOUT,\n+\tTERR_VERSION,\n+\tTERR_REGISTER,\n+\tTERR_FEATURE,\n+\tTERR_RESET,\n+\tTERR_AUTONEG,\n+\tTERR_MBX,\n+\tTERR_I2C,\n+\tTERR_FC,\n+\tTERR_FLASH,\n+\tTERR_DEVICE,\n+\tTERR_HOSTIF,\n+\tTERR_SRAM,\n+\tTERR_EEPROM,\n+\tTERR_EEPROM_CHECKSUM,\n+\tTERR_EEPROM_PROTECT,\n+\tTERR_EEPROM_VERSION,\n+\tTERR_MAC,\n+\tTERR_MAC_ADDR,\n+\tTERR_SFP,\n+\tTERR_SFP_INITSEQ,\n+\tTERR_SFP_PRESENT,\n+\tTERR_SFP_SUPPORT,\n+\tTERR_SFP_SETUP,\n+\tTERR_PHY,\n+\tTERR_PHY_ADDR,\n+\tTERR_PHY_INIT,\n+\tTERR_FDIR_CMD,\n+\tTERR_FDIR_REINIT,\n+\tTERR_SWFW_SYNC,\n+\tTERR_SWFW_COMMAND,\n+\tTERR_FC_CFG,\n+\tTERR_FC_NEGO,\n+\tTERR_LINK_SETUP,\n+\tTERR_PCIE_PENDING,\n+\tTERR_PBA_SECTION,\n+\tTERR_OVERTEMP,\n+\tTERR_UNDERTEMP,\n+\tTERR_XPCS_POWERUP,\n+};\n+\n+/* WARNING: just for legacy compatibility */\n+#define TXGBE_NOT_IMPLEMENTED 0x7FFFFFFF\n+#define TXGBE_ERR_OPS_DUMMY 0x3FFFFFFF\n+\n+/* Error Codes */\n+#define TXGBE_ERR_EEPROM\t\t\t-(TERR_BASE + 1)\n+#define TXGBE_ERR_EEPROM_CHECKSUM\t\t-(TERR_BASE + 2)\n+#define TXGBE_ERR_PHY\t\t\t\t-(TERR_BASE + 3)\n+#define TXGBE_ERR_CONFIG\t\t\t-(TERR_BASE + 4)\n+#define TXGBE_ERR_PARAM\t\t\t\t-(TERR_BASE + 5)\n+#define TXGBE_ERR_MAC_TYPE\t\t\t-(TERR_BASE + 6)\n+#define TXGBE_ERR_UNKNOWN_PHY\t\t\t-(TERR_BASE + 7)\n+#define TXGBE_ERR_LINK_SETUP\t\t\t-(TERR_BASE + 8)\n+#define TXGBE_ERR_ADAPTER_STOPPED\t\t-(TERR_BASE + 9)\n+#define TXGBE_ERR_INVALID_MAC_ADDR\t\t-(TERR_BASE + 10)\n+#define TXGBE_ERR_DEVICE_NOT_SUPPORTED\t\t-(TERR_BASE + 11)\n+#define TXGBE_ERR_MASTER_REQUESTS_PENDING\t-(TERR_BASE + 12)\n+#define TXGBE_ERR_INVALID_LINK_SETTINGS\t\t-(TERR_BASE + 13)\n+#define TXGBE_ERR_AUTONEG_NOT_COMPLETE\t\t-(TERR_BASE + 14)\n+#define TXGBE_ERR_RESET_FAILED\t\t\t-(TERR_BASE + 15)\n+#define TXGBE_ERR_SWFW_SYNC\t\t\t-(TERR_BASE + 16)\n+#define TXGBE_ERR_PHY_ADDR_INVALID\t\t-(TERR_BASE + 17)\n+#define TXGBE_ERR_I2C\t\t\t\t-(TERR_BASE + 18)\n+#define TXGBE_ERR_SFP_NOT_SUPPORTED\t\t-(TERR_BASE + 19)\n+#define TXGBE_ERR_SFP_NOT_PRESENT\t\t-(TERR_BASE + 20)\n+#define TXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT\t-(TERR_BASE + 21)\n+#define TXGBE_ERR_NO_SAN_ADDR_PTR\t\t-(TERR_BASE + 22)\n+#define TXGBE_ERR_FDIR_REINIT_FAILED\t\t-(TERR_BASE + 23)\n+#define TXGBE_ERR_EEPROM_VERSION\t\t-(TERR_BASE + 24)\n+#define TXGBE_ERR_NO_SPACE\t\t\t-(TERR_BASE + 25)\n+#define TXGBE_ERR_OVERTEMP\t\t\t-(TERR_BASE + 26)\n+#define TXGBE_ERR_FC_NOT_NEGOTIATED\t\t-(TERR_BASE + 27)\n+#define TXGBE_ERR_FC_NOT_SUPPORTED\t\t-(TERR_BASE + 28)\n+#define TXGBE_ERR_SFP_SETUP_NOT_COMPLETE\t-(TERR_BASE + 30)\n+#define TXGBE_ERR_PBA_SECTION\t\t\t-(TERR_BASE + 31)\n+#define TXGBE_ERR_INVALID_ARGUMENT\t\t-(TERR_BASE + 32)\n+#define TXGBE_ERR_HOST_INTERFACE_COMMAND\t-(TERR_BASE + 33)\n+#define TXGBE_ERR_OUT_OF_MEM\t\t\t-(TERR_BASE + 34)\n+#define TXGBE_ERR_FEATURE_NOT_SUPPORTED\t\t-(TERR_BASE + 36)\n+#define TXGBE_ERR_EEPROM_PROTECTED_REGION\t-(TERR_BASE + 37)\n+#define TXGBE_ERR_FDIR_CMD_INCOMPLETE\t\t-(TERR_BASE + 38)\n+#define TXGBE_ERR_FW_RESP_INVALID\t\t-(TERR_BASE + 39)\n+#define TXGBE_ERR_TOKEN_RETRY\t\t\t-(TERR_BASE + 40)\n+#define TXGBE_ERR_FLASH_LOADING_FAILED -(TERR_BASE + 41)\n+\n+#define TXGBE_ERR_NOSUPP -(TERR_BASE + 42)\n+#define TXGBE_ERR_UNDERTEMP -(TERR_BASE + 43)\n+#define TXGBE_ERR_XPCS_POWER_UP_FAILED -(TERR_BASE + 44)\n+#define TXGBE_ERR_PHY_INIT_NOT_DONE -(TERR_BASE + 45)\n+#define TXGBE_ERR_TIMEOUT -(TERR_BASE + 46)\n+#define TXGBE_ERR_REGISTER -(TERR_BASE + 47)\n+#define TXGBE_ERR_MNG_ACCESS_FAILED -(TERR_BASE + 49)\n+\n+#endif /* _TXGBE_STATUS_H_ */\n", "prefixes": [ "v2", "04/56" ] }