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GET /api/patches/79477/?format=api
{ "id": 79477, "url": "https://patches.dpdk.org/api/patches/79477/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1601561366-1821-9-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1601561366-1821-9-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1601561366-1821-9-git-send-email-michaelba@nvidia.com", "date": "2020-10-01T14:09:19", "name": "[v1,08/15] net/mlx5: share Tx control code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d8a1a55174b18e8bb5db04858bdc5e083f7c7c4f", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1601561366-1821-9-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 12645, "url": "https://patches.dpdk.org/api/series/12645/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12645", "date": "2020-10-01T14:09:11", "name": "mlx5 Tx DevX/Verbs separation", "version": 1, "mbox": "https://patches.dpdk.org/series/12645/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79477/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/79477/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F1458A04BA;\n\tThu, 1 Oct 2020 16:13:34 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E8931DBAA;\n\tThu, 1 Oct 2020 16:11:14 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id D6A771DBD1\n for <dev@dpdk.org>; Thu, 1 Oct 2020 16:11:12 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 1 Oct 2020 17:11:08 +0300", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 091EAAEO012743;\n Thu, 1 Oct 2020 17:11:08 +0300" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 1 Oct 2020 14:09:19 +0000", "Message-Id": "<1601561366-1821-9-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1601561366-1821-1-git-send-email-michaelba@nvidia.com>", "References": "<1601561366-1821-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v1 08/15] net/mlx5: share Tx control code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Move Tx object similar resources allocations and debug logs from DevX\nand Verbs modules to a shared location.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 4 +-\n drivers/net/mlx5/linux/mlx5_verbs.c | 84 ++++++++++++-------------------------\n drivers/net/mlx5/linux/mlx5_verbs.h | 3 +-\n drivers/net/mlx5/mlx5.h | 3 +-\n drivers/net/mlx5/mlx5_devx.c | 75 +++++++--------------------------\n drivers/net/mlx5/mlx5_devx.h | 3 +-\n drivers/net/mlx5/mlx5_trigger.c | 31 +++++++++++++-\n drivers/net/mlx5/mlx5_txq.c | 28 ++++++++-----\n 8 files changed, 93 insertions(+), 138 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex c5332a0..0db2b5a 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -520,9 +520,9 @@\n * Queue index in DPDK Tx queue array.\n *\n * @return\n- * The DevX/Verbs object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_txq_obj *\n+static int\n mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex c79c4a2..5568c75 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -807,7 +807,7 @@\n \tstruct ibv_qp_init_attr_ex qp_attr = { 0 };\n \tconst int desc = 1 << txq_data->elts_n;\n \n-\tMLX5_ASSERT(!txq_ctrl->obj);\n+\tMLX5_ASSERT(txq_ctrl->obj);\n \t/* CQ to be associated with the send queue. */\n \tqp_attr.send_cq = txq_obj->cq;\n \t/* CQ to be associated with the receive queue. */\n@@ -851,17 +851,16 @@\n * Queue index in DPDK Tx queue array.\n *\n * @return\n- * The Verbs object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-struct mlx5_txq_obj *\n+int\n mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_txq_obj tmpl;\n-\tstruct mlx5_txq_obj *txq_obj = NULL;\n+\tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n \tstruct ibv_qp_attr mod;\n \tunsigned int cqe_n;\n \tstruct mlx5dv_qp qp;\n@@ -871,26 +870,28 @@ struct mlx5_txq_obj *\n \tint ret = 0;\n \n \tMLX5_ASSERT(txq_data);\n+\tMLX5_ASSERT(txq_obj);\n+\ttxq_obj->type = MLX5_TXQ_OBJ_TYPE_IBV;\n+\ttxq_obj->txq_ctrl = txq_ctrl;\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;\n \tpriv->verbs_alloc_ctx.obj = txq_ctrl;\n \tif (mlx5_getenv_int(\"MLX5_ENABLE_CQE_COMPRESSION\")) {\n \t\tDRV_LOG(ERR, \"Port %u MLX5_ENABLE_CQE_COMPRESSION \"\n \t\t\t\"must never be set.\", dev->data->port_id);\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -rte_errno;\n \t}\n-\tmemset(&tmpl, 0, sizeof(struct mlx5_txq_obj));\n \tcqe_n = desc / MLX5_TX_COMP_THRESH +\n \t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n-\ttmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);\n-\tif (tmpl.cq == NULL) {\n+\ttxq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);\n+\tif (txq_obj->cq == NULL) {\n \t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n \t\t\tdev->data->port_id, idx);\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\ttmpl.qp = mlx5_ibv_qp_new(dev, idx, &tmpl);\n-\tif (tmpl.qp == NULL) {\n+\ttxq_obj->qp = mlx5_ibv_qp_new(dev, idx, txq_obj);\n+\tif (txq_obj->qp == NULL) {\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n@@ -900,7 +901,8 @@ struct mlx5_txq_obj *\n \t\t/* IB device port number. */\n \t\t.port_num = (uint8_t)priv->dev_port,\n \t};\n-\tret = mlx5_glue->modify_qp(tmpl.qp, &mod, (IBV_QP_STATE | IBV_QP_PORT));\n+\tret = mlx5_glue->modify_qp(txq_obj->qp, &mod,\n+\t\t\t\t (IBV_QP_STATE | IBV_QP_PORT));\n \tif (ret) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u Tx queue %u QP state to IBV_QPS_INIT failed.\",\n@@ -911,7 +913,7 @@ struct mlx5_txq_obj *\n \tmod = (struct ibv_qp_attr){\n \t\t.qp_state = IBV_QPS_RTR\n \t};\n-\tret = mlx5_glue->modify_qp(tmpl.qp, &mod, IBV_QP_STATE);\n+\tret = mlx5_glue->modify_qp(txq_obj->qp, &mod, IBV_QP_STATE);\n \tif (ret) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u Tx queue %u QP state to IBV_QPS_RTR failed.\",\n@@ -920,7 +922,7 @@ struct mlx5_txq_obj *\n \t\tgoto error;\n \t}\n \tmod.qp_state = IBV_QPS_RTS;\n-\tret = mlx5_glue->modify_qp(tmpl.qp, &mod, IBV_QP_STATE);\n+\tret = mlx5_glue->modify_qp(txq_obj->qp, &mod, IBV_QP_STATE);\n \tif (ret) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u Tx queue %u QP state to IBV_QPS_RTS failed.\",\n@@ -928,24 +930,15 @@ struct mlx5_txq_obj *\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\ttxq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t sizeof(struct mlx5_txq_obj), 0,\n-\t\t\t txq_ctrl->socket);\n-\tif (!txq_obj) {\n-\t\tDRV_LOG(ERR, \"Port %u Tx queue %u cannot allocate memory.\",\n-\t\t\tdev->data->port_id, idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n \tqp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/* If using DevX, need additional mask to read tisn value. */\n \tif (priv->sh->devx && !priv->sh->tdn)\n \t\tqp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;\n #endif\n-\tobj.cq.in = tmpl.cq;\n+\tobj.cq.in = txq_obj->cq;\n \tobj.cq.out = &cq_info;\n-\tobj.qp.in = tmpl.qp;\n+\tobj.qp.in = txq_obj->qp;\n \tobj.qp.out = &qp;\n \tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);\n \tif (ret != 0) {\n@@ -963,7 +956,7 @@ struct mlx5_txq_obj *\n \ttxq_data->cqe_n = log2above(cq_info.cqe_cnt);\n \ttxq_data->cqe_s = 1 << txq_data->cqe_n;\n \ttxq_data->cqe_m = txq_data->cqe_s - 1;\n-\ttxq_data->qp_num_8s = ((struct ibv_qp *)tmpl.qp)->qp_num << 8;\n+\ttxq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;\n \ttxq_data->wqes = qp.sq.buf;\n \ttxq_data->wqe_n = log2above(qp.sq.wqe_cnt);\n \ttxq_data->wqe_s = 1 << txq_data->wqe_n;\n@@ -978,15 +971,6 @@ struct mlx5_txq_obj *\n \ttxq_data->wqe_pi = 0;\n \ttxq_data->wqe_comp = 0;\n \ttxq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;\n-\ttxq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t\t txq_data->cqe_s * sizeof(*txq_data->fcqs),\n-\t\t\t\t RTE_CACHE_LINE_SIZE, txq_ctrl->socket);\n-\tif (!txq_data->fcqs) {\n-\t\tDRV_LOG(ERR, \"Port %u Tx queue %u can't allocate memory (FCQ).\",\n-\t\t\tdev->data->port_id, idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/*\n \t * If using DevX need to query and store TIS transport domain value.\n@@ -994,7 +978,7 @@ struct mlx5_txq_obj *\n \t * Will use this value on Rx, when creating matching TIR.\n \t */\n \tif (priv->sh->devx && !priv->sh->tdn) {\n-\t\tret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,\n+\t\tret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,\n \t\t\t\t\t\t &priv->sh->tdn);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"Fail to query port %u Tx queue %u QP TIS \"\n@@ -1008,8 +992,6 @@ struct mlx5_txq_obj *\n \t\t}\n \t}\n #endif\n-\ttxq_obj->qp = tmpl.qp;\n-\ttxq_obj->cq = tmpl.cq;\n \ttxq_ctrl->bf_reg = qp.bf.reg;\n \tif (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {\n \t\ttxq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;\n@@ -1024,25 +1006,17 @@ struct mlx5_txq_obj *\n \t\tgoto error;\n \t}\n \ttxq_uar_init(txq_ctrl);\n-\ttxq_obj->txq_ctrl = txq_ctrl;\n-\tLIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n-\treturn txq_obj;\n+\treturn 0;\n error:\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n-\tif (tmpl.cq)\n-\t\tclaim_zero(mlx5_glue->destroy_cq(tmpl.cq));\n-\tif (tmpl.qp)\n-\t\tclaim_zero(mlx5_glue->destroy_qp(tmpl.qp));\n-\tif (txq_data->fcqs) {\n-\t\tmlx5_free(txq_data->fcqs);\n-\t\ttxq_data->fcqs = NULL;\n-\t}\n-\tif (txq_obj)\n-\t\tmlx5_free(txq_obj);\n+\tif (txq_obj->cq)\n+\t\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+\tif (txq_obj->qp)\n+\t\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \trte_errno = ret; /* Restore rte_errno. */\n-\treturn NULL;\n+\treturn -rte_errno;\n }\n \n /**\n@@ -1057,12 +1031,6 @@ struct mlx5_txq_obj *\n \tMLX5_ASSERT(txq_obj);\n \tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n \tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n-\tif (txq_obj->txq_ctrl->txq.fcqs) {\n-\t\tmlx5_free(txq_obj->txq_ctrl->txq.fcqs);\n-\t\ttxq_obj->txq_ctrl->txq.fcqs = NULL;\n-\t}\n-\tLIST_REMOVE(txq_obj, next);\n-\tmlx5_free(txq_obj);\n }\n \n struct mlx5_obj_ops ibv_obj_ops = {\ndiff --git a/drivers/net/mlx5/linux/mlx5_verbs.h b/drivers/net/mlx5/linux/mlx5_verbs.h\nindex 7f6bb99..0670f6c 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.h\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.h\n@@ -12,8 +12,7 @@ struct mlx5_verbs_ops {\n \tmlx5_dereg_mr_t dereg_mr;\n };\n \n-struct mlx5_txq_obj *mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint16_t idx);\n+int mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n void mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj);\n \n /* Verbs ops struct */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8679750..3093f6e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -789,8 +789,7 @@ struct mlx5_obj_ops {\n \tvoid (*hrxq_destroy)(struct mlx5_hrxq *hrxq);\n \tint (*drop_action_create)(struct rte_eth_dev *dev);\n \tvoid (*drop_action_destroy)(struct rte_eth_dev *dev);\n-\tstruct mlx5_txq_obj *(*txq_obj_new)(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint16_t idx);\n+\tint (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);\n \tvoid (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 0b6e116..f3437a6 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -819,9 +819,9 @@\n * Queue index in DPDK Tx queue array.\n *\n * @return\n- * The hairpin DevX object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static struct mlx5_txq_obj *\n+static int\n mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -829,20 +829,11 @@\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n \tstruct mlx5_devx_create_sq_attr attr = { 0 };\n-\tstruct mlx5_txq_obj *tmpl = NULL;\n+\tstruct mlx5_txq_obj *tmpl = txq_ctrl->obj;\n \tuint32_t max_wq_data;\n \n \tMLX5_ASSERT(txq_data);\n-\tMLX5_ASSERT(!txq_ctrl->obj);\n-\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,\n-\t\t\t txq_ctrl->socket);\n-\tif (!tmpl) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot allocate memory resources.\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\treturn NULL;\n-\t}\n+\tMLX5_ASSERT(tmpl);\n \ttmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;\n \ttmpl->txq_ctrl = txq_ctrl;\n \tattr.hairpin = 1;\n@@ -854,9 +845,8 @@\n \t\t\tDRV_LOG(ERR, \"Total data size %u power of 2 is \"\n \t\t\t\t\"too large for hairpin.\",\n \t\t\t\tpriv->config.log_hp_size);\n-\t\t\tmlx5_free(tmpl);\n \t\t\trte_errno = ERANGE;\n-\t\t\treturn NULL;\n+\t\t\treturn -rte_errno;\n \t\t}\n \t\tattr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n \t} else {\n@@ -874,14 +864,10 @@\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u tx hairpin queue %u can't create SQ object.\",\n \t\t\tdev->data->port_id, idx);\n-\t\tmlx5_free(tmpl);\n \t\trte_errno = errno;\n-\t\treturn NULL;\n+\t\treturn -rte_errno;\n \t}\n-\tDRV_LOG(DEBUG, \"Port %u sxq %u updated with %p.\", dev->data->port_id,\n-\t\tidx, (void *)&tmpl);\n-\tLIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);\n-\treturn tmpl;\n+\treturn 0;\n }\n \n #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET\n@@ -1179,9 +1165,9 @@\n * Queue index in DPDK Tx queue array.\n *\n * @return\n- * The DevX object initialized, NULL otherwise and rte_errno is set.\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-struct mlx5_txq_obj *\n+int\n mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n@@ -1195,27 +1181,17 @@ struct mlx5_txq_obj *\n \tDRV_LOG(ERR, \"Port %u Tx queue %u cannot create with DevX, no UAR.\",\n \t\t dev->data->port_id, idx);\n \trte_errno = ENOMEM;\n-\treturn NULL;\n+\treturn -rte_errno;\n #else\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tstruct mlx5_devx_modify_sq_attr msq_attr = { 0 };\n-\tstruct mlx5_txq_obj *txq_obj = NULL;\n+\tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n \tvoid *reg_addr;\n \tuint32_t cqe_n;\n \tint ret = 0;\n \n \tMLX5_ASSERT(txq_data);\n-\tMLX5_ASSERT(!txq_ctrl->obj);\n-\ttxq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t sizeof(struct mlx5_txq_obj), 0,\n-\t\t\t txq_ctrl->socket);\n-\tif (!txq_obj) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot allocate memory resources.\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\treturn NULL;\n-\t}\n+\tMLX5_ASSERT(txq_obj);\n \ttxq_obj->type = MLX5_TXQ_OBJ_TYPE_DEVX_SQ;\n \ttxq_obj->txq_ctrl = txq_ctrl;\n \ttxq_obj->dev = dev;\n@@ -1267,17 +1243,6 @@ struct mlx5_txq_obj *\n \t\t\tdev->data->port_id, idx);\n \t\tgoto error;\n \t}\n-\ttxq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t\t txq_data->cqe_s * sizeof(*txq_data->fcqs),\n-\t\t\t\t RTE_CACHE_LINE_SIZE,\n-\t\t\t\t txq_ctrl->socket);\n-\tif (!txq_data->fcqs) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot allocate memory (FCQ).\",\n-\t\t\tdev->data->port_id, idx);\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/*\n \t * If using DevX need to query and store TIS transport domain value.\n@@ -1294,18 +1259,12 @@ struct mlx5_txq_obj *\n \ttxq_ctrl->uar_mmap_offset =\n \t\t\t\tmlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);\n \ttxq_uar_init(txq_ctrl);\n-\tLIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);\n-\treturn txq_obj;\n+\treturn 0;\n error:\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n \ttxq_release_devx_resources(txq_obj);\n-\tif (txq_data->fcqs) {\n-\t\tmlx5_free(txq_data->fcqs);\n-\t\ttxq_data->fcqs = NULL;\n-\t}\n-\tmlx5_free(txq_obj);\n \trte_errno = ret; /* Restore rte_errno. */\n-\treturn NULL;\n+\treturn -rte_errno;\n #endif\n }\n \n@@ -1327,12 +1286,6 @@ struct mlx5_txq_obj *\n \t\ttxq_release_devx_resources(txq_obj);\n #endif\n \t}\n-\tif (txq_obj->txq_ctrl->txq.fcqs) {\n-\t\tmlx5_free(txq_obj->txq_ctrl->txq.fcqs);\n-\t\ttxq_obj->txq_ctrl->txq.fcqs = NULL;\n-\t}\n-\tLIST_REMOVE(txq_obj, next);\n-\tmlx5_free(txq_obj);\n }\n \n struct mlx5_obj_ops devx_obj_ops = {\ndiff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h\nindex 0bbbbc0..bc8a8d6 100644\n--- a/drivers/net/mlx5/mlx5_devx.h\n+++ b/drivers/net/mlx5/mlx5_devx.h\n@@ -7,8 +7,7 @@\n \n #include \"mlx5.h\"\n \n-struct mlx5_txq_obj *mlx5_txq_devx_obj_new(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint16_t idx);\n+int mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj);\n \n extern struct mlx5_obj_ops devx_obj_ops;\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 6763042..e72e5fb 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -52,16 +52,45 @@\n \n \tfor (i = 0; i != priv->txqs_n; ++i) {\n \t\tstruct mlx5_txq_ctrl *txq_ctrl = mlx5_txq_get(dev, i);\n+\t\tstruct mlx5_txq_data *txq_data = &txq_ctrl->txq;\n+\t\tuint32_t flags = MLX5_MEM_RTE | MLX5_MEM_ZERO;\n \n \t\tif (!txq_ctrl)\n \t\t\tcontinue;\n \t\tif (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)\n \t\t\ttxq_alloc_elts(txq_ctrl);\n-\t\ttxq_ctrl->obj = priv->obj_ops.txq_obj_new(dev, i);\n+\t\tMLX5_ASSERT(!txq_ctrl->obj);\n+\t\ttxq_ctrl->obj = mlx5_malloc(flags, sizeof(struct mlx5_txq_obj),\n+\t\t\t\t\t 0, txq_ctrl->socket);\n \t\tif (!txq_ctrl->obj) {\n+\t\t\tDRV_LOG(ERR, \"Port %u Tx queue %u cannot allocate \"\n+\t\t\t\t\"memory resources.\", dev->data->port_id,\n+\t\t\t\ttxq_data->idx);\n \t\t\trte_errno = ENOMEM;\n \t\t\tgoto error;\n \t\t}\n+\t\tret = priv->obj_ops.txq_obj_new(dev, i);\n+\t\tif (ret < 0) {\n+\t\t\tmlx5_free(txq_ctrl->obj);\n+\t\t\ttxq_ctrl->obj = NULL;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tif (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {\n+\t\t\tsize_t size = txq_data->cqe_s * sizeof(*txq_data->fcqs);\n+\t\t\ttxq_data->fcqs = mlx5_malloc(flags, size,\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t\t\t txq_ctrl->socket);\n+\t\t\tif (!txq_data->fcqs) {\n+\t\t\t\tDRV_LOG(ERR, \"Port %u Tx queue %u cannot \"\n+\t\t\t\t\t\"allocate memory (FCQ).\",\n+\t\t\t\t\tdev->data->port_id, i);\n+\t\t\t\trte_errno = ENOMEM;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t}\n+\t\tDRV_LOG(DEBUG, \"Port %u txq %u updated with %p.\",\n+\t\t\tdev->data->port_id, i, (void *)&txq_ctrl->obj);\n+\t\tLIST_INSERT_HEAD(&priv->txqsobj, txq_ctrl->obj, next);\n \t}\n \treturn 0;\n error:\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex c1d36c3..23213d9 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -1298,21 +1298,29 @@ struct mlx5_txq_ctrl *\n mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_txq_ctrl *txq;\n+\tstruct mlx5_txq_ctrl *txq_ctrl;\n \n \tif (!(*priv->txqs)[idx])\n \t\treturn 0;\n-\ttxq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);\n-\tif (!rte_atomic32_dec_and_test(&txq->refcnt))\n+\ttxq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);\n+\tif (!rte_atomic32_dec_and_test(&txq_ctrl->refcnt))\n \t\treturn 1;\n-\tif (txq->obj) {\n-\t\tpriv->obj_ops.txq_obj_release(txq->obj);\n-\t\ttxq->obj = NULL;\n+\tif (txq_ctrl->obj) {\n+\t\tpriv->obj_ops.txq_obj_release(txq_ctrl->obj);\n+\t\tLIST_REMOVE(txq_ctrl->obj, next);\n+\t\tmlx5_free(txq_ctrl->obj);\n+\t\ttxq_ctrl->obj = NULL;\n+\t}\n+\tif (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {\n+\t\tif (txq_ctrl->txq.fcqs) {\n+\t\t\tmlx5_free(txq_ctrl->txq.fcqs);\n+\t\t\ttxq_ctrl->txq.fcqs = NULL;\n+\t\t}\n+\t\ttxq_free_elts(txq_ctrl);\n+\t\tmlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);\n \t}\n-\ttxq_free_elts(txq);\n-\tmlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);\n-\tLIST_REMOVE(txq, next);\n-\tmlx5_free(txq);\n+\tLIST_REMOVE(txq_ctrl, next);\n+\tmlx5_free(txq_ctrl);\n \t(*priv->txqs)[idx] = NULL;\n \tdev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;\n \treturn 0;\n", "prefixes": [ "v1", "08/15" ] }