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GET /api/patches/79337/?format=api
{ "id": 79337, "url": "https://patches.dpdk.org/api/patches/79337/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-1-ciara.power@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200930130415.11211-1-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200930130415.11211-1-ciara.power@intel.com", "date": "2020-09-30T13:03:56", "name": "[v3,00/18] add max SIMD bitwidth to EAL", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 978, "url": "https://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-1-ciara.power@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/79337/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/79337/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0B7E9A04B5;\n\tWed, 30 Sep 2020 15:08:07 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3645F1C231;\n\tWed, 30 Sep 2020 15:08:06 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id D76CE1C210\n for <dev@dpdk.org>; Wed, 30 Sep 2020 15:08:04 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Sep 2020 06:08:02 -0700", "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:01 -0700" ], "IronPort-SDR": [ "\n muRNjl2jwN4IibY4QKnH1vSil/0rAzwiHmUGQneUaaapvVOx+5n8xwNzez/GETkOmc1EFYD/aq\n KK9nYGeA5cfg==", "\n Yd3LM3EHH6rppoTB+Ui+BgDHUYkyTBzlnOisME0ikHIIUP5ro+83WdXNyGCsAezhAZiic5EbEk\n kpDriColC2yg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9759\"; a=\"150223428\"", "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"150223428\"", "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"294603134\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "Ciara Power <ciara.power@intel.com>", "Date": "Wed, 30 Sep 2020 14:03:56 +0100", "Message-Id": "<20200930130415.11211-1-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200807155859.63888-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 00/18] add max SIMD bitwidth to EAL", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A number of components in DPDK have optional AVX-512 or other vector\ncode paths which can be selected at runtime. Rather than having each\ncomponent provide its own mechanism to select a code path, this patchset\nadds support for a single setting to control what code paths are used.\nThis can be used to enable some non-default code paths e.g. ones using\nAVX-512, but also to limit the code paths to certain vector widths, or\nto scalar code only, which is useful for testing.\n\nThe max SIMD bitwidth setting can be set by the app itself through use of\nthe available API, or can be overriden by a commandline argument passed by\nthe user.\n\nv3:\n - Added patch to add check for LPM lib\n - Modified default max bitwidth for Arm to disable max SIMD bitwidth,\n which will allow for SVE.\n - Added \"0\" as an acceptable value for command-line flag, which internally\n is used as UINT16_MAX to essentially disable max SIMD bitwidth limits.\n - Made suggested changes to net lib patch.\n - Rebased onto main.\nv2:\n - Added some documentation.\n - Modified default max bitwidth for Arm.\n - Moved mlx5 condition check into existing check vec support function.\n - Added max SIMD bitwidth checks to some libraries.\n\nCiara Power (18):\n eal: add max SIMD bitwidth\n eal: add default SIMD bitwidth values\n doc: add detail on using max SIMD bitwidth\n net/i40e: add checks for max SIMD bitwidth\n net/axgbe: add checks for max SIMD bitwidth\n net/bnxt: add checks for max SIMD bitwidth\n net/enic: add checks for max SIMD bitwidth\n net/fm10k: add checks for max SIMD bitwidth\n net/iavf: add checks for max SIMD bitwidth\n net/ice: add checks for max SIMD bitwidth\n net/ixgbe: add checks for max SIMD bitwidth\n net/mlx5: add checks for max SIMD bitwidth\n net/virtio: add checks for max SIMD bitwidth\n distributor: add checks for max SIMD bitwidth\n member: add checks for max SIMD bitwidth\n efd: add checks for max SIMD bitwidth\n net: add checks for max SIMD bitwidth\n lpm: choose vector path at runtime\n\n doc/guides/howto/avx512.rst | 36 ++++++++++\n doc/guides/howto/index.rst | 1 +\n doc/guides/linux_gsg/eal_args.include.rst | 16 +++++\n .../prog_guide/env_abstraction_layer.rst | 32 +++++++++\n drivers/net/axgbe/axgbe_rxtx.c | 3 +-\n drivers/net/bnxt/bnxt_ethdev.c | 6 +-\n drivers/net/enic/enic_rxtx_vec_avx2.c | 3 +-\n drivers/net/fm10k/fm10k_ethdev.c | 11 ++-\n drivers/net/i40e/i40e_rxtx.c | 19 ++++--\n drivers/net/iavf/iavf_rxtx.c | 16 +++--\n drivers/net/ice/ice_rxtx.c | 20 ++++--\n drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-\n drivers/net/mlx5/mlx5_rxtx_vec.c | 2 +\n drivers/net/virtio/virtio_ethdev.c | 9 ++-\n lib/librte_distributor/rte_distributor.c | 3 +-\n lib/librte_eal/arm/include/rte_vect.h | 2 +\n lib/librte_eal/common/eal_common_options.c | 67 +++++++++++++++++++\n lib/librte_eal/common/eal_internal_cfg.h | 8 +++\n lib/librte_eal/common/eal_options.h | 2 +\n lib/librte_eal/include/rte_eal.h | 33 +++++++++\n lib/librte_eal/ppc/include/rte_vect.h | 2 +\n lib/librte_eal/rte_eal_version.map | 4 ++\n lib/librte_eal/x86/include/rte_vect.h | 2 +\n lib/librte_efd/rte_efd.c | 7 +-\n lib/librte_lpm/rte_lpm.h | 57 +++++++++++++---\n lib/librte_lpm/rte_lpm_altivec.h | 2 +-\n lib/librte_lpm/rte_lpm_neon.h | 2 +-\n lib/librte_lpm/rte_lpm_sse.h | 2 +-\n lib/librte_member/rte_member_ht.c | 3 +-\n lib/librte_net/rte_net_crc.c | 26 ++++---\n lib/librte_net/rte_net_crc.h | 3 +-\n 31 files changed, 351 insertions(+), 55 deletions(-)\n create mode 100644 doc/guides/howto/avx512.rst", "diff": null, "prefixes": [ "v3", "00/18" ] }