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{
    "id": 78735,
    "url": "https://patches.dpdk.org/api/patches/78735/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-3-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1600949555-28043-3-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1600949555-28043-3-git-send-email-arybchenko@solarflare.com",
    "date": "2020-09-24T12:11:37",
    "name": "[v3,02/60] common/sfc_efx/base: update MCDI headers",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "e4682a673399bda3e199da5a2974397b4670fb4f",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-3-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [
        {
            "id": 12473,
            "url": "https://patches.dpdk.org/api/series/12473/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12473",
            "date": "2020-09-24T12:11:40",
            "name": "common/sfc_efx: support Riverhead NIC family",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/12473/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/78735/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/78735/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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            "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:45 +0100",
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            "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id C6C031613BE\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:45 +0100 (BST)"
        ],
        "X-Virus-Scanned": "Proofpoint Essentials engine",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Thu, 24 Sep 2020 13:11:37 +0100",
        "Message-ID": "<1600949555-28043-3-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1600949555-28043-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>\n <1600949555-28043-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
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        "X-TM-AS-User-Approved-Sender": "Yes",
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        "X-TMASE-Result": "10--17.926700-8.000000",
        "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003",
        "X-MDID": "1600949582-qIZuGrbhMVFl",
        "Subject": "[dpdk-dev] [PATCH v3 02/60] common/sfc_efx/base: update MCDI headers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/common/sfc_efx/base/efx_regs_mcdi.h   | 5483 ++++++++++++++++-\n .../common/sfc_efx/base/efx_regs_mcdi_aoe.h   |  201 +-\n .../common/sfc_efx/base/efx_regs_mcdi_strs.h  |    2 +-\n 3 files changed, 5415 insertions(+), 271 deletions(-)",
    "diff": "diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\nindex ffb9a9b02a..f31a25e4ff 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h\n@@ -7,7 +7,7 @@\n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n  * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n- * rebuild this file with \"make -C doc mcdiheaders\".\n+ * rebuild this file with \"make mcdi_headers_v5\".\n  */\n \n #ifndef _SIENA_MC_DRIVER_PCOL_H\n@@ -405,7 +405,23 @@\n  */\n #define\tMC_CMD_ERR_PIOBUFS_PRESENT 0x101b\n \n-/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10\n+/* MC_CMD_RESOURCE_SPECIFIER enum */\n+/* enum: Any */\n+#define\tMC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff\n+#define\tMC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */\n+\n+/* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will\n+ * be parsed to an inner frame. Other values are reserved. Unknown values\n+ * should be treated same as NONE.\n+ */\n+#define\tMAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */\n+/* enum: Don't assume enum aligns with support bitmask... */\n+#define\tMAE_MCDI_ENCAP_TYPE_VXLAN 0x1\n+#define\tMAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */\n+#define\tMAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */\n+#define\tMAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */\n+\n+/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100\n  * platforms\n  */\n #define\tMCDI_EVENT_LEN 8\n@@ -423,14 +439,19 @@\n #define\tMCDI_EVENT_LEVEL_FATAL 0x3\n #define\tMCDI_EVENT_DATA_OFST 0\n #define\tMCDI_EVENT_DATA_LEN 4\n+#define\tMCDI_EVENT_CMDDONE_SEQ_OFST 0\n #define\tMCDI_EVENT_CMDDONE_SEQ_LBN 0\n #define\tMCDI_EVENT_CMDDONE_SEQ_WIDTH 8\n+#define\tMCDI_EVENT_CMDDONE_DATALEN_OFST 0\n #define\tMCDI_EVENT_CMDDONE_DATALEN_LBN 8\n #define\tMCDI_EVENT_CMDDONE_DATALEN_WIDTH 8\n+#define\tMCDI_EVENT_CMDDONE_ERRNO_OFST 0\n #define\tMCDI_EVENT_CMDDONE_ERRNO_LBN 16\n #define\tMCDI_EVENT_CMDDONE_ERRNO_WIDTH 8\n+#define\tMCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0\n #define\tMCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16\n+#define\tMCDI_EVENT_LINKCHANGE_SPEED_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_LBN 16\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4\n /* enum: Link is down or link speed could not be determined */\n@@ -449,26 +470,36 @@\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_50G 0x6\n /* enum: 100Gbs */\n #define\tMCDI_EVENT_LINKCHANGE_SPEED_100G 0x7\n+#define\tMCDI_EVENT_LINKCHANGE_FCNTL_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_FCNTL_LBN 20\n #define\tMCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4\n+#define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24\n #define\tMCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_MONITOR_OFST 0\n #define\tMCDI_EVENT_SENSOREVT_MONITOR_LBN 0\n #define\tMCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_STATE_OFST 0\n #define\tMCDI_EVENT_SENSOREVT_STATE_LBN 8\n #define\tMCDI_EVENT_SENSOREVT_STATE_WIDTH 8\n+#define\tMCDI_EVENT_SENSOREVT_VALUE_OFST 0\n #define\tMCDI_EVENT_SENSOREVT_VALUE_LBN 16\n #define\tMCDI_EVENT_SENSOREVT_VALUE_WIDTH 16\n+#define\tMCDI_EVENT_FWALERT_DATA_OFST 0\n #define\tMCDI_EVENT_FWALERT_DATA_LBN 8\n #define\tMCDI_EVENT_FWALERT_DATA_WIDTH 24\n+#define\tMCDI_EVENT_FWALERT_REASON_OFST 0\n #define\tMCDI_EVENT_FWALERT_REASON_LBN 0\n #define\tMCDI_EVENT_FWALERT_REASON_WIDTH 8\n /* enum: SRAM Access. */\n #define\tMCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1\n+#define\tMCDI_EVENT_FLR_VF_OFST 0\n #define\tMCDI_EVENT_FLR_VF_LBN 0\n #define\tMCDI_EVENT_FLR_VF_WIDTH 8\n+#define\tMCDI_EVENT_TX_ERR_TXQ_OFST 0\n #define\tMCDI_EVENT_TX_ERR_TXQ_LBN 0\n #define\tMCDI_EVENT_TX_ERR_TXQ_WIDTH 12\n+#define\tMCDI_EVENT_TX_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_TX_ERR_TYPE_LBN 12\n #define\tMCDI_EVENT_TX_ERR_TYPE_WIDTH 4\n /* enum: Descriptor loader reported failure */\n@@ -483,12 +514,16 @@\n #define\tMCDI_EVENT_TX_OPT_IN_PKT 0x8\n /* enum: DMA or PIO data access error */\n #define\tMCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9\n+#define\tMCDI_EVENT_TX_ERR_INFO_OFST 0\n #define\tMCDI_EVENT_TX_ERR_INFO_LBN 16\n #define\tMCDI_EVENT_TX_ERR_INFO_WIDTH 16\n+#define\tMCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0\n #define\tMCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12\n #define\tMCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1\n+#define\tMCDI_EVENT_TX_FLUSH_TXQ_OFST 0\n #define\tMCDI_EVENT_TX_FLUSH_TXQ_LBN 0\n #define\tMCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12\n+#define\tMCDI_EVENT_PTP_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_PTP_ERR_TYPE_LBN 0\n #define\tMCDI_EVENT_PTP_ERR_TYPE_WIDTH 8\n /* enum: PLL lost lock */\n@@ -499,6 +534,7 @@\n #define\tMCDI_EVENT_PTP_ERR_FIFO 0x3\n /* enum: Merge queue overflow */\n #define\tMCDI_EVENT_PTP_ERR_QUEUE 0x4\n+#define\tMCDI_EVENT_AOE_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_TYPE_LBN 0\n #define\tMCDI_EVENT_AOE_ERR_TYPE_WIDTH 8\n /* enum: AOE failed to load - no valid image? */\n@@ -545,8 +581,10 @@\n #define\tMCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13\n /* enum: Notify that FPGA Controller is alive to serve MCDI requests */\n #define\tMCDI_EVENT_AOE_FC_RUNNING 0x14\n+#define\tMCDI_EVENT_AOE_ERR_DATA_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_DATA_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8\n /* enum: FC Assert happened, but the register information is not available */\n@@ -554,6 +592,7 @@\n /* enum: The register information for FC Assert is ready for readinng by driver\n  */\n #define\tMCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8\n /* enum: Reading from NV failed */\n@@ -574,28 +613,38 @@\n #define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7\n /* enum: Unsupported DDR rank */\n #define\tMCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8\n /* enum: Primary boot flash */\n #define\tMCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0\n /* enum: Secondary boot flash */\n #define\tMCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8\n+#define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8\n #define\tMCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8\n+#define\tMCDI_EVENT_RX_ERR_RXQ_OFST 0\n #define\tMCDI_EVENT_RX_ERR_RXQ_LBN 0\n #define\tMCDI_EVENT_RX_ERR_RXQ_WIDTH 12\n+#define\tMCDI_EVENT_RX_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_RX_ERR_TYPE_LBN 12\n #define\tMCDI_EVENT_RX_ERR_TYPE_WIDTH 4\n+#define\tMCDI_EVENT_RX_ERR_INFO_OFST 0\n #define\tMCDI_EVENT_RX_ERR_INFO_LBN 16\n #define\tMCDI_EVENT_RX_ERR_INFO_WIDTH 16\n+#define\tMCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0\n #define\tMCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12\n #define\tMCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1\n+#define\tMCDI_EVENT_RX_FLUSH_RXQ_OFST 0\n #define\tMCDI_EVENT_RX_FLUSH_RXQ_LBN 0\n #define\tMCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12\n+#define\tMCDI_EVENT_MC_REBOOT_COUNT_OFST 0\n #define\tMCDI_EVENT_MC_REBOOT_COUNT_LBN 0\n #define\tMCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16\n+#define\tMCDI_EVENT_MUM_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_MUM_ERR_TYPE_LBN 0\n #define\tMCDI_EVENT_MUM_ERR_TYPE_WIDTH 8\n /* enum: MUM failed to load - no valid image? */\n@@ -604,10 +653,13 @@\n #define\tMCDI_EVENT_MUM_ASSERT 0x2\n /* enum: MUM not kicking watchdog */\n #define\tMCDI_EVENT_MUM_WATCHDOG 0x3\n+#define\tMCDI_EVENT_MUM_ERR_DATA_OFST 0\n #define\tMCDI_EVENT_MUM_ERR_DATA_LBN 8\n #define\tMCDI_EVENT_MUM_ERR_DATA_WIDTH 8\n+#define\tMCDI_EVENT_DBRET_SEQ_OFST 0\n #define\tMCDI_EVENT_DBRET_SEQ_LBN 0\n #define\tMCDI_EVENT_DBRET_SEQ_WIDTH 8\n+#define\tMCDI_EVENT_SUC_ERR_TYPE_OFST 0\n #define\tMCDI_EVENT_SUC_ERR_TYPE_LBN 0\n #define\tMCDI_EVENT_SUC_ERR_TYPE_WIDTH 8\n /* enum: Corrupted or bad SUC application. */\n@@ -618,30 +670,48 @@\n #define\tMCDI_EVENT_SUC_EXCEPTION 0x3\n /* enum: SUC watchdog timer expired. */\n #define\tMCDI_EVENT_SUC_WATCHDOG 0x4\n+#define\tMCDI_EVENT_SUC_ERR_ADDRESS_OFST 0\n #define\tMCDI_EVENT_SUC_ERR_ADDRESS_LBN 8\n #define\tMCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24\n+#define\tMCDI_EVENT_SUC_ERR_DATA_OFST 0\n #define\tMCDI_EVENT_SUC_ERR_DATA_LBN 8\n #define\tMCDI_EVENT_SUC_ERR_DATA_WIDTH 24\n+#define\tMCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0\n #define\tMCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24\n+#define\tMCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24\n #define\tMCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4\n /*             Enum values, see field(s): */\n /*                MCDI_EVENT/LINKCHANGE_SPEED */\n+#define\tMCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28\n #define\tMCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1\n+#define\tMCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0\n #define\tMCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29\n #define\tMCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3\n /*             Enum values, see field(s): */\n /*                MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */\n+#define\tMCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0\n #define\tMCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0\n #define\tMCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30\n+#define\tMCDI_EVENT_MODULECHANGE_SEQ_OFST 0\n #define\tMCDI_EVENT_MODULECHANGE_SEQ_LBN 30\n #define\tMCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2\n #define\tMCDI_EVENT_DATA_LBN 0\n #define\tMCDI_EVENT_DATA_WIDTH 32\n+/* Alias for PTP_DATA. */\n #define\tMCDI_EVENT_SRC_LBN 36\n #define\tMCDI_EVENT_SRC_WIDTH 8\n+/* Data associated with PTP events which doesn't fit into the main DATA field\n+ */\n+#define\tMCDI_EVENT_PTP_DATA_LBN 36\n+#define\tMCDI_EVENT_PTP_DATA_WIDTH 8\n+/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the\n+ * event ring\n+ */\n+#define\tMCDI_EVENT_EV_EVQ_PHASE_LBN 59\n+#define\tMCDI_EVENT_EV_EVQ_PHASE_WIDTH 1\n #define\tMCDI_EVENT_EV_CODE_LBN 60\n #define\tMCDI_EVENT_EV_CODE_WIDTH 4\n #define\tMCDI_EVENT_CODE_LBN 44\n@@ -737,6 +807,27 @@\n  * contains the value.\n  */\n #define\tMCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23\n+/* enum: Notification that a descriptor proxy function configuration has been\n+ * pushed to \"live\" status (visible to host). SRC field contains the handle of\n+ * the affected descriptor proxy function. DATA field contains the generation\n+ * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /\n+ * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.\n+ */\n+#define\tMCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24\n+/* enum: Notification that a descriptor proxy function has been reset. SRC\n+ * field contains the handle of the affected descriptor proxy function. See\n+ * SF-122927-TC for details.\n+ */\n+#define\tMCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25\n+/* enum: Notification that a driver attached to a descriptor proxy function.\n+ * SRC field contains the handle of the affected descriptor proxy function. For\n+ * Virtio proxy functions this message consists of two MCDI events, where the\n+ * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0\n+ * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy\n+ * functions event length and meaning of DATA field is not yet defined. See\n+ * SF-122927-TC for details.\n+ */\n+#define\tMCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26\n /* enum: Artificial event generated by host and posted via MC for test\n  * purposes.\n  */\n@@ -888,6 +979,22 @@\n /* The current state of a sensor. */\n #define\tMCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36\n #define\tMCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8\n+#define\tMCDI_EVENT_DESC_PROXY_DATA_OFST 0\n+#define\tMCDI_EVENT_DESC_PROXY_DATA_LEN 4\n+#define\tMCDI_EVENT_DESC_PROXY_DATA_LBN 0\n+#define\tMCDI_EVENT_DESC_PROXY_DATA_WIDTH 32\n+/* Generation count of applied configuration set */\n+#define\tMCDI_EVENT_DESC_PROXY_GENERATION_OFST 0\n+#define\tMCDI_EVENT_DESC_PROXY_GENERATION_LEN 4\n+#define\tMCDI_EVENT_DESC_PROXY_GENERATION_LBN 0\n+#define\tMCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32\n+/* Virtio features negotiated with the host driver. First event (CONT=1)\n+ * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.\n+ */\n+#define\tMCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0\n+#define\tMCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4\n+#define\tMCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0\n+#define\tMCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32\n \n /* FCDI_EVENT structuredef */\n #define\tFCDI_EVENT_LEN 8\n@@ -905,6 +1012,7 @@\n #define\tFCDI_EVENT_LEVEL_FATAL 0x3\n #define\tFCDI_EVENT_DATA_OFST 0\n #define\tFCDI_EVENT_DATA_LEN 4\n+#define\tFCDI_EVENT_LINK_STATE_STATUS_OFST 0\n #define\tFCDI_EVENT_LINK_STATE_STATUS_LBN 0\n #define\tFCDI_EVENT_LINK_STATE_STATUS_WIDTH 1\n #define\tFCDI_EVENT_LINK_DOWN 0x0 /* enum */\n@@ -1040,24 +1148,33 @@\n #define\tMUM_EVENT_LEVEL_FATAL 0x3\n #define\tMUM_EVENT_DATA_OFST 0\n #define\tMUM_EVENT_DATA_LEN 4\n+#define\tMUM_EVENT_SENSOR_ID_OFST 0\n #define\tMUM_EVENT_SENSOR_ID_LBN 0\n #define\tMUM_EVENT_SENSOR_ID_WIDTH 8\n /*             Enum values, see field(s): */\n /*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */\n+#define\tMUM_EVENT_SENSOR_STATE_OFST 0\n #define\tMUM_EVENT_SENSOR_STATE_LBN 8\n #define\tMUM_EVENT_SENSOR_STATE_WIDTH 8\n+#define\tMUM_EVENT_PORT_PHY_READY_OFST 0\n #define\tMUM_EVENT_PORT_PHY_READY_LBN 0\n #define\tMUM_EVENT_PORT_PHY_READY_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_LINK_UP_OFST 0\n #define\tMUM_EVENT_PORT_PHY_LINK_UP_LBN 1\n #define\tMUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_LOL_OFST 0\n #define\tMUM_EVENT_PORT_PHY_TX_LOL_LBN 2\n #define\tMUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_RX_LOL_OFST 0\n #define\tMUM_EVENT_PORT_PHY_RX_LOL_LBN 3\n #define\tMUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_LOS_OFST 0\n #define\tMUM_EVENT_PORT_PHY_TX_LOS_LBN 4\n #define\tMUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_RX_LOS_OFST 0\n #define\tMUM_EVENT_PORT_PHY_RX_LOS_LBN 5\n #define\tMUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1\n+#define\tMUM_EVENT_PORT_PHY_TX_FAULT_OFST 0\n #define\tMUM_EVENT_PORT_PHY_TX_FAULT_LBN 6\n #define\tMUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1\n #define\tMUM_EVENT_DATA_LBN 0\n@@ -1205,16 +1322,22 @@\n  * below)\n  */\n #define\tMC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1\n+#define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6\n #define\tMC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1\n /* Destination address */\n@@ -1272,10 +1395,13 @@\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1\n+#define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2\n #define\tMC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1\n \n@@ -1547,14 +1673,19 @@\n /* Flags indicating which extended fields are valid */\n #define\tMC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0\n #define\tMC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1\n #define\tMC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2\n #define\tMC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3\n #define\tMC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4\n #define\tMC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1\n /* MC firmware unique build ID (as binary SHA-1 value) */\n@@ -2088,8 +2219,10 @@\n /* Original field containing queue ID. Now extended to include flags. */\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16\n+#define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31\n #define\tMC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1\n \n@@ -2395,12 +2528,16 @@\n /* Various PTP capabilities */\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1\n+#define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1\n #define\tMC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12\n@@ -2728,10 +2865,13 @@\n #define\tMC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16\n+#define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15\n #define\tMC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1\n+#define\tMC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4\n #define\tMC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14\n #define\tMC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1\n #define\tMC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32\n@@ -2980,10 +3120,13 @@\n #define\tMC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32\n #define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15\n #define\tMC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1\n+#define\tMC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4\n #define\tMC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14\n #define\tMC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1\n #define\tMC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32\n@@ -3051,22 +3194,31 @@\n /* new state to set if UPDATE=1 */\n #define\tMC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4\n+#define\tMC_CMD_DRV_ATTACH_OFST 0\n #define\tMC_CMD_DRV_ATTACH_LBN 0\n #define\tMC_CMD_DRV_ATTACH_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0\n #define\tMC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1\n+#define\tMC_CMD_DRV_PREBOOT_OFST 0\n #define\tMC_CMD_DRV_PREBOOT_LBN 1\n #define\tMC_CMD_DRV_PREBOOT_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1\n #define\tMC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2\n #define\tMC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5\n #define\tMC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1\n /* 1 to set new state, or 0 to just report the existing state */\n@@ -3113,22 +3265,31 @@\n /* new state to set if UPDATE=1 */\n #define\tMC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4\n+/*             MC_CMD_DRV_ATTACH_OFST 0 */\n /*             MC_CMD_DRV_ATTACH_LBN 0 */\n /*             MC_CMD_DRV_ATTACH_WIDTH 1 */\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1\n+/*             MC_CMD_DRV_PREBOOT_OFST 0 */\n /*             MC_CMD_DRV_PREBOOT_LBN 1 */\n /*             MC_CMD_DRV_PREBOOT_WIDTH 1 */\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1\n #define\tMC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2\n #define\tMC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1\n+#define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5\n #define\tMC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1\n /* 1 to set new state, or 0 to just report the existing state */\n@@ -3263,6 +3424,7 @@\n  */\n #define\tMC_CMD_ENTITY_RESET_IN_FLAG_OFST 0\n #define\tMC_CMD_ENTITY_RESET_IN_FLAG_LEN 4\n+#define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0\n #define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0\n #define\tMC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1\n \n@@ -3381,8 +3543,10 @@\n #define\tMC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)\n #define\tMC_CMD_PUTS_IN_DEST_OFST 0\n #define\tMC_CMD_PUTS_IN_DEST_LEN 4\n+#define\tMC_CMD_PUTS_IN_UART_OFST 0\n #define\tMC_CMD_PUTS_IN_UART_LBN 0\n #define\tMC_CMD_PUTS_IN_UART_WIDTH 1\n+#define\tMC_CMD_PUTS_IN_PORT_OFST 0\n #define\tMC_CMD_PUTS_IN_PORT_LBN 1\n #define\tMC_CMD_PUTS_IN_PORT_WIDTH 1\n #define\tMC_CMD_PUTS_IN_DHOST_OFST 4\n@@ -3415,18 +3579,25 @@\n /* flags */\n #define\tMC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3\n #define\tMC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4\n #define\tMC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5\n #define\tMC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1\n+#define\tMC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6\n #define\tMC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1\n /* ?? */\n@@ -3435,46 +3606,67 @@\n /* Bitmask of supported capabilities */\n #define\tMC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8\n #define\tMC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4\n+#define\tMC_CMD_PHY_CAP_10HDX_OFST 8\n #define\tMC_CMD_PHY_CAP_10HDX_LBN 1\n #define\tMC_CMD_PHY_CAP_10HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_10FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_10FDX_LBN 2\n #define\tMC_CMD_PHY_CAP_10FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100HDX_OFST 8\n #define\tMC_CMD_PHY_CAP_100HDX_LBN 3\n #define\tMC_CMD_PHY_CAP_100HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_100FDX_LBN 4\n #define\tMC_CMD_PHY_CAP_100FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_1000HDX_OFST 8\n #define\tMC_CMD_PHY_CAP_1000HDX_LBN 5\n #define\tMC_CMD_PHY_CAP_1000HDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_1000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_1000FDX_LBN 6\n #define\tMC_CMD_PHY_CAP_1000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_10000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_10000FDX_LBN 7\n #define\tMC_CMD_PHY_CAP_10000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_PAUSE_OFST 8\n #define\tMC_CMD_PHY_CAP_PAUSE_LBN 8\n #define\tMC_CMD_PHY_CAP_PAUSE_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_ASYM_OFST 8\n #define\tMC_CMD_PHY_CAP_ASYM_LBN 9\n #define\tMC_CMD_PHY_CAP_ASYM_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_AN_OFST 8\n #define\tMC_CMD_PHY_CAP_AN_LBN 10\n #define\tMC_CMD_PHY_CAP_AN_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_40000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_40000FDX_LBN 11\n #define\tMC_CMD_PHY_CAP_40000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_DDM_OFST 8\n #define\tMC_CMD_PHY_CAP_DDM_LBN 12\n #define\tMC_CMD_PHY_CAP_DDM_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_100000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_100000FDX_LBN 13\n #define\tMC_CMD_PHY_CAP_100000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_25000FDX_LBN 14\n #define\tMC_CMD_PHY_CAP_25000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_50000FDX_OFST 8\n #define\tMC_CMD_PHY_CAP_50000FDX_LBN 15\n #define\tMC_CMD_PHY_CAP_50000FDX_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_OFST 8\n #define\tMC_CMD_PHY_CAP_BASER_FEC_LBN 16\n #define\tMC_CMD_PHY_CAP_BASER_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8\n #define\tMC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17\n #define\tMC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_RS_FEC_OFST 8\n #define\tMC_CMD_PHY_CAP_RS_FEC_LBN 18\n #define\tMC_CMD_PHY_CAP_RS_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8\n #define\tMC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19\n #define\tMC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8\n #define\tMC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20\n #define\tMC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1\n+#define\tMC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8\n #define\tMC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21\n #define\tMC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1\n /* ?? */\n@@ -4089,20 +4281,28 @@\n /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n #define\tMC_CMD_GET_LINK_OUT_FLAGS_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_LINK_OUT_LINK_UP_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_LINK_UP_LBN 0\n #define\tMC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1\n #define\tMC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2\n #define\tMC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3\n #define\tMC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6\n #define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7\n #define\tMC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8\n #define\tMC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9\n #define\tMC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1\n /* This returns the negotiated flow control value. */\n@@ -4112,12 +4312,16 @@\n /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */\n #define\tMC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24\n #define\tMC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4\n+#define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24\n #define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0\n #define\tMC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24\n #define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1\n #define\tMC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24\n #define\tMC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2\n #define\tMC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1\n+#define\tMC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24\n #define\tMC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3\n #define\tMC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1\n \n@@ -4145,20 +4349,28 @@\n /*               MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */\n #define\tMC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4\n+#define\tMC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1\n #define\tMC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2\n #define\tMC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3\n #define\tMC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7\n #define\tMC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8\n #define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16\n #define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9\n #define\tMC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1\n /* This returns the negotiated flow control value. */\n@@ -4168,12 +4380,16 @@\n /*               MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */\n #define\tMC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24\n #define\tMC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4\n+/*             MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */\n /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */\n /*             MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */\n+/*             MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */\n /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */\n /*             MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */\n+/*             MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */\n /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */\n /*             MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */\n+/*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */\n /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */\n /*             MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */\n /* True local device capabilities (taking into account currently used PMD/MDI,\n@@ -4197,24 +4413,36 @@\n /*               FEC_TYPE/TYPE */\n #define\tMC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2\n #define\tMC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3\n #define\tMC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4\n #define\tMC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5\n #define\tMC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6\n #define\tMC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7\n #define\tMC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40\n #define\tMC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8\n #define\tMC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1\n+#define\tMC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40\n+#define\tMC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9\n+#define\tMC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1\n \n \n /***********************************/\n@@ -4237,12 +4465,18 @@\n /* Flags */\n #define\tMC_CMD_SET_LINK_IN_FLAGS_OFST 4\n #define\tMC_CMD_SET_LINK_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_LINK_IN_LOWPOWER_OFST 4\n #define\tMC_CMD_SET_LINK_IN_LOWPOWER_LBN 0\n #define\tMC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_POWEROFF_OFST 4\n #define\tMC_CMD_SET_LINK_IN_POWEROFF_LBN 1\n #define\tMC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_TXDIS_OFST 4\n #define\tMC_CMD_SET_LINK_IN_TXDIS_LBN 2\n #define\tMC_CMD_SET_LINK_IN_TXDIS_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_LINKDOWN_OFST 4\n+#define\tMC_CMD_SET_LINK_IN_LINKDOWN_LBN 3\n+#define\tMC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1\n /* Loopback mode. */\n #define\tMC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8\n #define\tMC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4\n@@ -4267,12 +4501,18 @@\n /* Flags */\n #define\tMC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4\n #define\tMC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4\n+#define\tMC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4\n #define\tMC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0\n #define\tMC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4\n #define\tMC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1\n #define\tMC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4\n #define\tMC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2\n #define\tMC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1\n+#define\tMC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4\n+#define\tMC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3\n+#define\tMC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1\n /* Loopback mode. */\n #define\tMC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8\n #define\tMC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4\n@@ -4285,8 +4525,10 @@\n #define\tMC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1\n+#define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7\n+#define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7\n #define\tMC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1\n \n@@ -4340,8 +4582,10 @@\n #define\tMC_CMD_SET_MAC_IN_ADDR_HI_OFST 12\n #define\tMC_CMD_SET_MAC_IN_REJECT_OFST 16\n #define\tMC_CMD_SET_MAC_IN_REJECT_LEN 4\n+#define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16\n #define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0\n #define\tMC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16\n #define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1\n #define\tMC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_IN_FCNTL_OFST 20\n@@ -4360,6 +4604,7 @@\n #define\tMC_CMD_FCNTL_GENERATE 0x5\n #define\tMC_CMD_SET_MAC_IN_FLAGS_OFST 24\n #define\tMC_CMD_SET_MAC_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24\n #define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0\n #define\tMC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1\n \n@@ -4378,8 +4623,10 @@\n #define\tMC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1\n #define\tMC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1\n #define\tMC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20\n@@ -4398,6 +4645,7 @@\n /*               MC_CMD_FCNTL_GENERATE 0x5 */\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1\n /* Select which parameters to configure. A parameter will only be modified if\n@@ -4407,14 +4655,19 @@\n  */\n #define\tMC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1\n+#define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4\n #define\tMC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1\n \n@@ -4536,18 +4789,25 @@\n #define\tMC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4\n #define\tMC_CMD_MAC_STATS_IN_CMD_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_CMD_LEN 4\n+#define\tMC_CMD_MAC_STATS_IN_DMA_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_DMA_LBN 0\n #define\tMC_CMD_MAC_STATS_IN_DMA_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_CLEAR_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_CLEAR_LBN 1\n #define\tMC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5\n #define\tMC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1\n+#define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8\n #define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16\n #define\tMC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16\n /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as\n@@ -5053,8 +5313,10 @@\n /*            MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1\n+#define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1\n #define\tMC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1\n \n@@ -5211,18 +5473,25 @@\n #define\tMC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0\n #define\tMC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_TLV_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_TLV_LBN 1\n #define\tMC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2\n #define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_CRC_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_CRC_LBN 3\n #define\tMC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5\n #define\tMC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6\n #define\tMC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_OUT_A_B_OFST 12\n #define\tMC_CMD_NVRAM_INFO_OUT_A_B_LBN 7\n #define\tMC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16\n@@ -5242,14 +5511,19 @@\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1\n+#define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1\n #define\tMC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16\n@@ -5298,6 +5572,7 @@\n /*               MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4\n+#define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n #define\tMC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n \n@@ -5477,10 +5752,13 @@\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2\n #define\tMC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1\n \n@@ -5676,6 +5954,7 @@\n #define\tMC_CMD_REBOOT_MODE_SNAPPER 0x3\n /* enum: snapper fake POR */\n #define\tMC_CMD_REBOOT_MODE_SNAPPER_POR 0x4\n+#define\tMC_CMD_REBOOT_MODE_IN_FAKE_OFST 0\n #define\tMC_CMD_REBOOT_MODE_IN_FAKE_LBN 7\n #define\tMC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1\n \n@@ -5748,6 +6027,7 @@\n /* Flags controlling information retrieved */\n #define\tMC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4\n #define\tMC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4\n+#define\tMC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4\n #define\tMC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0\n #define\tMC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1\n \n@@ -5970,6 +6250,7 @@\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4\n /*            Enum values, see field(s): */\n /*               MC_CMD_SENSOR_INFO_OUT */\n+#define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31\n #define\tMC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1\n /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */\n@@ -6025,7 +6306,11 @@\n \n /* MC_CMD_READ_SENSORS_IN msgrequest */\n #define\tMC_CMD_READ_SENSORS_IN_LEN 8\n-/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */\n+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).\n+ *\n+ * If the address is 0xffffffffffffffff send the readings in the response (used\n+ * by cmdclient).\n+ */\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0\n@@ -6033,7 +6318,11 @@\n \n /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_LEN 12\n-/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */\n+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).\n+ *\n+ * If the address is 0xffffffffffffffff send the readings in the response (used\n+ * by cmdclient).\n+ */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0\n@@ -6044,7 +6333,11 @@\n \n /* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16\n-/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */\n+/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).\n+ *\n+ * If the address is 0xffffffffffffffff send the readings in the response (used\n+ * by cmdclient).\n+ */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0\n@@ -6055,6 +6348,7 @@\n /* Flags controlling information retrieved */\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4\n+#define\tMC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0\n #define\tMC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1\n \n@@ -6336,6 +6630,7 @@\n #define\tMC_CMD_WORKAROUND_EXT_OUT_LEN 4\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0\n #define\tMC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1\n \n@@ -6558,10 +6853,13 @@\n #define\tMC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0\n #define\tMC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1\n #define\tMC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1\n+#define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4\n #define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2\n #define\tMC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1\n /* Subtype ID code for content of this partition */\n@@ -6686,6 +6984,7 @@\n #define\tMC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2\n #define\tMC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12\n #define\tMC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4\n+#define\tMC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12\n #define\tMC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0\n #define\tMC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1\n \n@@ -6700,6 +6999,7 @@\n /*            MC_CMD_CLP_IN_OP_LEN 4 */\n #define\tMC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4\n #define\tMC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4\n+#define\tMC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4\n #define\tMC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0\n #define\tMC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1\n \n@@ -6751,6 +7051,7 @@\n #define\tMC_CMD_MUM_IN_LEN 4\n #define\tMC_CMD_MUM_IN_OP_HDR_OFST 0\n #define\tMC_CMD_MUM_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_OP_OFST 0\n #define\tMC_CMD_MUM_IN_OP_LBN 0\n #define\tMC_CMD_MUM_IN_OP_WIDTH 8\n /* enum: NULL MCDI command to MUM */\n@@ -6892,6 +7193,7 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_GPIO_OPCODE_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OPCODE_LBN 0\n #define\tMC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8\n #define\tMC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */\n@@ -6954,12 +7256,14 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8\n #define\tMC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */\n+#define\tMC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16\n #define\tMC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8\n \n@@ -6976,6 +7280,7 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8\n \n@@ -6985,6 +7290,7 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8\n \n@@ -6994,6 +7300,7 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24\n #define\tMC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8\n \n@@ -7004,8 +7311,10 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4\n #define\tMC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4\n #define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0\n #define\tMC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8\n+#define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4\n #define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8\n #define\tMC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8\n \n@@ -7023,10 +7332,13 @@\n /* Control flags for clock programming */\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1\n+#define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2\n #define\tMC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1\n \n@@ -7052,6 +7364,7 @@\n /*            MC_CMD_MUM_IN_CMD_LEN 4 */\n #define\tMC_CMD_MUM_IN_QSFP_HDR_OFST 4\n #define\tMC_CMD_MUM_IN_QSFP_HDR_LEN 4\n+#define\tMC_CMD_MUM_IN_QSFP_OPCODE_OFST 4\n #define\tMC_CMD_MUM_IN_QSFP_OPCODE_LBN 0\n #define\tMC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4\n #define\tMC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */\n@@ -7238,10 +7551,13 @@\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24\n #define\tMC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8\n \n@@ -7267,8 +7583,10 @@\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1\n+#define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1\n #define\tMC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1\n \n@@ -7313,8 +7631,10 @@\n /* Discrete (soldered) DDR resistor strap info */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16\n /* Number of SODIMM info records */\n@@ -7328,6 +7648,7 @@\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8\n /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */\n@@ -7336,10 +7657,13 @@\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1\n /* enum: Total number of SODIMM banks */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */\n@@ -7348,10 +7672,13 @@\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */\n /* enum: Values 5-15 are reserved for future usage */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4\n /* enum: No module present */\n@@ -7369,6 +7696,7 @@\n /* enum: Modules may or may not be present, but cannot establish contact by I2C\n  */\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6\n+#define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52\n #define\tMC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12\n \n@@ -7677,12 +8005,6 @@\n /* MC_CMD_EVENT_CTRL_OUT msgrequest */\n #define\tMC_CMD_EVENT_CTRL_OUT_LEN 0\n \n-/* MC_CMD_RESOURCE_SPECIFIER enum */\n-/* enum: Any */\n-#define\tMC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff\n-/* enum: None */\n-#define\tMC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe\n-\n /* EVB_PORT_ID structuredef */\n #define\tEVB_PORT_ID_LEN 4\n #define\tEVB_PORT_ID_PORT_ID_OFST 0\n@@ -7902,24 +8224,34 @@\n #define\tLICENSED_FEATURES_MASK_LEN 8\n #define\tLICENSED_FEATURES_MASK_LO_OFST 0\n #define\tLICENSED_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_FEATURES_RX_CUT_THROUGH_OFST 0\n #define\tLICENSED_FEATURES_RX_CUT_THROUGH_LBN 0\n #define\tLICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_FEATURES_PIO_OFST 0\n #define\tLICENSED_FEATURES_PIO_LBN 1\n #define\tLICENSED_FEATURES_PIO_WIDTH 1\n+#define\tLICENSED_FEATURES_EVQ_TIMER_OFST 0\n #define\tLICENSED_FEATURES_EVQ_TIMER_LBN 2\n #define\tLICENSED_FEATURES_EVQ_TIMER_WIDTH 1\n+#define\tLICENSED_FEATURES_CLOCK_OFST 0\n #define\tLICENSED_FEATURES_CLOCK_LBN 3\n #define\tLICENSED_FEATURES_CLOCK_WIDTH 1\n+#define\tLICENSED_FEATURES_RX_TIMESTAMPS_OFST 0\n #define\tLICENSED_FEATURES_RX_TIMESTAMPS_LBN 4\n #define\tLICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_FEATURES_TX_TIMESTAMPS_OFST 0\n #define\tLICENSED_FEATURES_TX_TIMESTAMPS_LBN 5\n #define\tLICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_FEATURES_RX_SNIFF_OFST 0\n #define\tLICENSED_FEATURES_RX_SNIFF_LBN 6\n #define\tLICENSED_FEATURES_RX_SNIFF_WIDTH 1\n+#define\tLICENSED_FEATURES_TX_SNIFF_OFST 0\n #define\tLICENSED_FEATURES_TX_SNIFF_LBN 7\n #define\tLICENSED_FEATURES_TX_SNIFF_WIDTH 1\n+#define\tLICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0\n #define\tLICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8\n #define\tLICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1\n+#define\tLICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0\n #define\tLICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9\n #define\tLICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1\n #define\tLICENSED_FEATURES_MASK_LBN 0\n@@ -7932,36 +8264,52 @@\n #define\tLICENSED_V3_APPS_MASK_LEN 8\n #define\tLICENSED_V3_APPS_MASK_LO_OFST 0\n #define\tLICENSED_V3_APPS_MASK_HI_OFST 4\n+#define\tLICENSED_V3_APPS_ONLOAD_OFST 0\n #define\tLICENSED_V3_APPS_ONLOAD_LBN 0\n #define\tLICENSED_V3_APPS_ONLOAD_WIDTH 1\n+#define\tLICENSED_V3_APPS_PTP_OFST 0\n #define\tLICENSED_V3_APPS_PTP_LBN 1\n #define\tLICENSED_V3_APPS_PTP_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARSECURE_OFST 0\n #define\tLICENSED_V3_APPS_SOLARSECURE_LBN 3\n #define\tLICENSED_V3_APPS_SOLARSECURE_WIDTH 1\n+#define\tLICENSED_V3_APPS_PERF_MONITOR_OFST 0\n #define\tLICENSED_V3_APPS_PERF_MONITOR_LBN 4\n #define\tLICENSED_V3_APPS_PERF_MONITOR_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1\n+#define\tLICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0\n #define\tLICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7\n #define\tLICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1\n+#define\tLICENSED_V3_APPS_TCP_DIRECT_OFST 0\n #define\tLICENSED_V3_APPS_TCP_DIRECT_LBN 8\n #define\tLICENSED_V3_APPS_TCP_DIRECT_WIDTH 1\n+#define\tLICENSED_V3_APPS_LOW_LATENCY_OFST 0\n #define\tLICENSED_V3_APPS_LOW_LATENCY_LBN 9\n #define\tLICENSED_V3_APPS_LOW_LATENCY_WIDTH 1\n+#define\tLICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10\n #define\tLICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1\n+#define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12\n #define\tLICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1\n+#define\tLICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0\n #define\tLICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13\n #define\tLICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1\n+#define\tLICENSED_V3_APPS_DSHBRD_OFST 0\n #define\tLICENSED_V3_APPS_DSHBRD_LBN 14\n #define\tLICENSED_V3_APPS_DSHBRD_WIDTH 1\n+#define\tLICENSED_V3_APPS_SCATRD_OFST 0\n #define\tLICENSED_V3_APPS_SCATRD_LBN 15\n #define\tLICENSED_V3_APPS_SCATRD_WIDTH 1\n #define\tLICENSED_V3_APPS_MASK_LBN 0\n@@ -7974,24 +8322,34 @@\n #define\tLICENSED_V3_FEATURES_MASK_LEN 8\n #define\tLICENSED_V3_FEATURES_MASK_LO_OFST 0\n #define\tLICENSED_V3_FEATURES_MASK_HI_OFST 4\n+#define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0\n #define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0\n #define\tLICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_PIO_OFST 0\n #define\tLICENSED_V3_FEATURES_PIO_LBN 1\n #define\tLICENSED_V3_FEATURES_PIO_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_EVQ_TIMER_OFST 0\n #define\tLICENSED_V3_FEATURES_EVQ_TIMER_LBN 2\n #define\tLICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_CLOCK_OFST 0\n #define\tLICENSED_V3_FEATURES_CLOCK_LBN 3\n #define\tLICENSED_V3_FEATURES_CLOCK_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0\n #define\tLICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4\n #define\tLICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0\n #define\tLICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5\n #define\tLICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_RX_SNIFF_OFST 0\n #define\tLICENSED_V3_FEATURES_RX_SNIFF_LBN 6\n #define\tLICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_TX_SNIFF_OFST 0\n #define\tLICENSED_V3_FEATURES_TX_SNIFF_LBN 7\n #define\tLICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0\n #define\tLICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8\n #define\tLICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1\n+#define\tLICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0\n #define\tLICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9\n #define\tLICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1\n #define\tLICENSED_V3_FEATURES_MASK_LBN 0\n@@ -8044,12 +8402,16 @@\n  */\n #define\tRSS_MODE_HASH_SELECTOR_OFST 0\n #define\tRSS_MODE_HASH_SELECTOR_LEN 1\n+#define\tRSS_MODE_HASH_SRC_ADDR_OFST 0\n #define\tRSS_MODE_HASH_SRC_ADDR_LBN 0\n #define\tRSS_MODE_HASH_SRC_ADDR_WIDTH 1\n+#define\tRSS_MODE_HASH_DST_ADDR_OFST 0\n #define\tRSS_MODE_HASH_DST_ADDR_LBN 1\n #define\tRSS_MODE_HASH_DST_ADDR_WIDTH 1\n+#define\tRSS_MODE_HASH_SRC_PORT_OFST 0\n #define\tRSS_MODE_HASH_SRC_PORT_LBN 2\n #define\tRSS_MODE_HASH_SRC_PORT_WIDTH 1\n+#define\tRSS_MODE_HASH_DST_PORT_OFST 0\n #define\tRSS_MODE_HASH_DST_PORT_LBN 3\n #define\tRSS_MODE_HASH_DST_PORT_WIDTH 1\n #define\tRSS_MODE_HASH_SELECTOR_LBN 0\n@@ -8164,18 +8526,25 @@\n /* tbd */\n #define\tMC_CMD_INIT_EVQ_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6\n #define\tMC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20\n@@ -8250,20 +8619,28 @@\n /* tbd */\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4\n /* enum: All initialisation flags specified by host. */\n@@ -8285,6 +8662,9 @@\n  * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.\n  */\n #define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11\n+#define\tMC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20\n #define\tMC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4\n /* enum: Disabled */\n@@ -8335,12 +8715,16 @@\n /* Actual configuration applied on the card */\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1\n+#define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3\n #define\tMC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1\n \n@@ -8401,20 +8785,28 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3\n #define\tMC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9\n #define\tMC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_IN_UNUSED_OFST 16\n #define\tMC_CMD_INIT_RXQ_IN_UNUSED_LBN 10\n #define\tMC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8458,20 +8850,28 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3\n #define\tMC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10\n #define\tMC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4\n /* enum: One packet per descriptor (for normal networking) */\n@@ -8487,8 +8887,10 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2\n /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */\n@@ -8496,10 +8898,13 @@\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */\n #define\tMC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20\n #define\tMC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8542,20 +8947,28 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3\n #define\tMC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10\n #define\tMC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4\n /* enum: One packet per descriptor (for normal networking) */\n@@ -8571,8 +8984,10 @@\n #define\tMC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2\n /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */\n #define\tMC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n #define\tMC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n #define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */\n@@ -8580,10 +8995,13 @@\n #define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */\n #define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */\n #define\tMC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20\n #define\tMC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8655,20 +9073,28 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3\n #define\tMC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10\n #define\tMC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4\n /* enum: One packet per descriptor (for normal networking) */\n@@ -8684,8 +9110,10 @@\n #define\tMC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2\n /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */\n #define\tMC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n #define\tMC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n #define\tMC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */\n@@ -8693,10 +9121,13 @@\n #define\tMC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */\n #define\tMC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */\n #define\tMC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20\n #define\tMC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8781,20 +9212,28 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3\n #define\tMC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10\n #define\tMC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4\n /* enum: One packet per descriptor (for normal networking) */\n@@ -8810,8 +9249,10 @@\n #define\tMC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2\n /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */\n #define\tMC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15\n #define\tMC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3\n #define\tMC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */\n@@ -8819,10 +9260,13 @@\n #define\tMC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */\n #define\tMC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */\n #define\tMC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1\n+#define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20\n #define\tMC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8939,22 +9383,31 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_TXQ_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4\n #define\tMC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11\n #define\tMC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n@@ -8995,30 +9448,51 @@\n /* There will be more flags here. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4\n #define\tMC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14\n #define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_OFST 16\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_LBN 17\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_WIDTH 1\n /* Owner ID to use if in buffer mode (zero if physical) */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20\n #define\tMC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4\n@@ -9036,8 +9510,10 @@\n /* Flags related to Qbb flow control mode. */\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1\n+#define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1\n #define\tMC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3\n \n@@ -9148,8 +9624,10 @@\n /* The handle of the target function. */\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_OFST 0\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_LEN 4\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16\n+#define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16\n #define\tMC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16\n #define\tMC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */\n@@ -9213,6 +9691,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_IN_LEN 108\n #define\tMC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0\n #define\tMC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0\n #define\tMC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n@@ -9257,6 +9736,7 @@\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4\n+#define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0\n #define\tMC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1\n /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS\n@@ -9466,32 +9946,46 @@\n /* fields to include in match criteria */\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3\n #define\tMC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5\n #define\tMC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6\n #define\tMC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7\n #define\tMC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8\n #define\tMC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9\n #define\tMC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11\n #define\tMC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n #define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n #define\tMC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n /* receive destination */\n@@ -9539,8 +10033,10 @@\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_LEN 4\n /* enum: request default behaviour (based on filter type) */\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1\n #define\tMC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1\n /* source MAC address to match (as bytes in network order) */\n@@ -9606,60 +10102,88 @@\n /* fields to include in match criteria */\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n #define\tMC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n /* receive destination */\n@@ -9707,8 +10231,10 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4\n /* enum: request default behaviour (based on filter type) */\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1\n #define\tMC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1\n /* source MAC address to match (as bytes in network order) */\n@@ -9744,8 +10270,10 @@\n  */\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8\n /* enum: Match VXLAN traffic with this VNI */\n@@ -9754,8 +10282,10 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1\n /* enum: Reserved for experimental development use */\n #define\tMC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72\n #define\tMC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0\n #define\tMC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72\n #define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24\n #define\tMC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8\n /* enum: Match NVGRE traffic with this VSID */\n@@ -9827,9 +10357,10 @@\n #define\tMC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16\n \n /* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional\n- * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via\n- * its rte_flow API. This extension is only useful with the sfc_efx driver\n- * included as part of DPDK, used in conjunction with the dpdk datapath\n+ * filter actions for EF100. Some of these actions are also supported on EF10,\n+ * for Intel's DPDK (Data Plane Development Kit, dpdk.org) via its rte_flow\n+ * API. In the latter case, this extension is only useful with the sfc_efx\n+ * driver included as part of DPDK, used in conjunction with the dpdk datapath\n  * firmware variant.\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_LEN 180\n@@ -9850,60 +10381,88 @@\n /* fields to include in match criteria */\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1\n /* receive destination */\n@@ -9951,8 +10510,10 @@\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4\n /* enum: request default behaviour (based on filter type) */\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1\n #define\tMC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1\n /* source MAC address to match (as bytes in network order) */\n@@ -9988,8 +10549,10 @@\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8\n /* enum: Match VXLAN traffic with this VNI */\n@@ -9998,8 +10561,10 @@\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1\n /* enum: Reserved for experimental development use */\n #define\tMC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72\n #define\tMC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0\n #define\tMC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24\n+#define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72\n #define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24\n #define\tMC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8\n /* enum: Match NVGRE traffic with this VSID */\n@@ -10069,11 +10634,39 @@\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156\n #define\tMC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16\n-/* Set an action for all packets matching this filter. The DPDK driver and dpdk\n- * f/w variant use their own specific delivery structures, which are documented\n- * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything\n- * other than MATCH_ACTION_NONE when the NIC is running another f/w variant\n- * will cause the filter insertion to fail with ENOTSUP.\n+/* Flags controlling mutations of the user_mark and user_flag fields of\n+ * matching packets, with logic as follows: if (req.MATCH_BITOR_FLAG == 1)\n+ * user_flag = req.MATCH_SET_FLAG bit_or user_flag; else user_flag =\n+ * req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark = 0; else if\n+ * (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK bit_or user_mark;\n+ * else user_mark = req.MATCH_SET_MARK; N.B. These flags overlap with the\n+ * MATCH_ACTION field, which is deprecated in favour of this field. For the\n+ * cases where these flags induce a valid encoding of the MATCH_ACTION field,\n+ * the semantics agree.\n+ */\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_LBN 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_LBN 2\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_WIDTH 1\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3\n+#define\tMC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1\n+/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the\n+ * functionality of this field in an ABI-backwards-compatible manner, and\n+ * should be used instead. Any future extensions should be made to the\n+ * MATCH_ACTION_FLAGS field, and not to this field. Set an action for all\n+ * packets matching this filter. The DPDK driver and (on EF10) dpdk f/w variant\n+ * use their own specific delivery structures, which are documented in the DPDK\n+ * Firmware Driver Interface (SF-119419-TC). Requesting anything other than\n+ * MATCH_ACTION_NONE on an EF10 NIC running another f/w variant will cause the\n+ * filter insertion to fail with ENOTSUP.\n  */\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172\n #define\tMC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4\n@@ -10164,6 +10757,10 @@\n  * frames (Medford only)\n  */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4\n+/* enum: read the list of supported matches for the encapsulation detection\n+ * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5\n \n /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */\n #define\tMC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8\n@@ -10198,6 +10795,7 @@\n /* bitfield of filter insertion restrictions */\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4\n+#define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0\n #define\tMC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1\n \n@@ -10243,6 +10841,34 @@\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32\n #define\tMC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4\n \n+/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is\n+ * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value\n+ * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the\n+ * supported match types that can be used in the encapsulation detection rules\n+ * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)\n+/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_GET_PARSER_DISP_INFO_IN/OP */\n+/* number of supported match types */\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4\n+/* array of supported match types (valid MATCH_FLAGS values for\n+ * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order\n+ */\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61\n+#define\tMC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253\n+\n \n /***********************************/\n /* MC_CMD_PARSER_DISP_RW\n@@ -10388,9 +11014,15 @@\n \n /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */\n #define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4\n-/* Identifies the port assignment for this function. */\n+/* Identifies the port assignment for this function. On EF100, it is possible\n+ * for the function to have no network port assigned (either because it is not\n+ * yet configured, or assigning a port to a given function personality makes no\n+ * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.\n+ */\n #define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0\n #define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4\n+/* enum: Special value to indicate no port is assigned to a function. */\n+#define\tMC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff\n \n \n /***********************************/\n@@ -10497,6 +11129,7 @@\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0\n #define\tMC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1\n /* RID offset of first VF from PF. */\n@@ -10526,6 +11159,7 @@\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4\n #define\tMC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8\n #define\tMC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0\n #define\tMC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1\n /* RID offset of first VF from PF, or 0 for no change, or\n@@ -10619,10 +11253,13 @@\n /* Combined metadata field. */\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8\n /* TXDPCPU raw table data for queue. */\n@@ -10645,14 +11282,19 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24\n /* RXDPCPU raw table data for queue. */\n@@ -10675,12 +11317,16 @@\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8\n+#define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32\n #define\tMC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8\n \n@@ -10832,38 +11478,55 @@\n /* Amalgamated TLP info word. */\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2\n+#define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9\n #define\tMC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23\n \n@@ -10886,32 +11549,46 @@\n /* Amalgamated TLP info word. */\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2\n+#define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10\n #define\tMC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22\n \n@@ -11063,62 +11740,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -11179,8 +11885,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11228,8 +11936,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11283,62 +11993,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -11399,8 +12138,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11448,8 +12189,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11497,70 +12240,106 @@\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC (when\n@@ -11624,62 +12403,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -11740,8 +12548,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11789,8 +12599,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -11838,70 +12650,106 @@\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC (when\n@@ -11990,62 +12838,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -12106,8 +12983,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12155,8 +13034,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12204,70 +13085,106 @@\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC (when\n@@ -12364,62 +13281,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -12480,8 +13426,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12529,8 +13477,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12578,70 +13528,106 @@\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC (when\n@@ -12743,62 +13729,91 @@\n /* First word of flags. */\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1\n /* RxDPCPU firmware id. */\n@@ -12859,8 +13874,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12908,8 +13925,10 @@\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n /* enum: reserved value - do not use (may indicate alternative interpretation\n@@ -12957,70 +13976,106 @@\n /* Second word of flags. Not present on older firmware (check the length). */\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n /* Number of FATSOv2 contexts per datapath supported by this NIC (when\n@@ -13128,190 +14183,2248 @@\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4\n #define\tMC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16\n \n-\n-/***********************************/\n-/* MC_CMD_V2_EXTN\n- * Encapsulation for a v2 extended command\n+/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: DPDK RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: DPDK TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n  */\n-#define\tMC_CMD_V2_EXTN 0x7f\n-\n-/* MC_CMD_V2_EXTN_IN msgrequest */\n-#define\tMC_CMD_V2_EXTN_IN_LEN 4\n-/* the extended command number */\n-#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0\n-#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15\n-#define\tMC_CMD_V2_EXTN_IN_UNUSED_LBN 15\n-#define\tMC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1\n-/* the actual length of the encapsulated command (which is not in the v1\n- * header)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n  */\n-#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16\n-#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10\n-#define\tMC_CMD_V2_EXTN_IN_UNUSED2_LBN 26\n-#define\tMC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2\n-/* Type of command/response */\n-#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28\n-#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4\n-/* enum: MCDI command directed to or response originating from the MC. */\n-#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0\n-/* enum: MCDI command directed to a TSA controller. MCDI responses of this type\n- * are not defined.\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)\n  */\n-#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1\n-\n-\n-/***********************************/\n-/* MC_CMD_TCM_BUCKET_ALLOC\n- * Allocate a pacer bucket (for qau rp or a snapper test)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n  */\n-#define\tMC_CMD_TCM_BUCKET_ALLOC 0xb2\n-#undef\tMC_CMD_0xb2_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */\n-#define\tMC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0\n-\n-/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */\n-#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4\n-/* the bucket id */\n-#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0\n-#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4\n-\n-\n-/***********************************/\n-/* MC_CMD_TCM_BUCKET_FREE\n- * Free a pacer bucket\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n  */\n-#define\tMC_CMD_TCM_BUCKET_FREE 0xb3\n-#undef\tMC_CMD_0xb3_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */\n-#define\tMC_CMD_TCM_BUCKET_FREE_IN_LEN 4\n-/* the bucket id */\n-#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0\n-#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4\n-\n-/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */\n-#define\tMC_CMD_TCM_BUCKET_FREE_OUT_LEN 0\n-\n-\n-/***********************************/\n-/* MC_CMD_TCM_BUCKET_INIT\n- * Initialise pacer bucket with a given rate\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n  */\n-#define\tMC_CMD_TCM_BUCKET_INIT 0xb4\n-#undef\tMC_CMD_0xb4_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */\n-#define\tMC_CMD_TCM_BUCKET_INIT_IN_LEN 8\n-/* the bucket id */\n-#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0\n-#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4\n-/* the rate in mbps */\n-#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4\n-#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4\n-\n-/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12\n-/* the bucket id */\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4\n-/* the rate in mbps */\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4\n-/* the desired maximum fill level */\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8\n-#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4\n-\n-/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */\n-#define\tMC_CMD_TCM_BUCKET_INIT_OUT_LEN 0\n-\n-\n-/***********************************/\n-/* MC_CMD_TCM_TXQ_INIT\n- * Initialise txq in pacer with given options or set options\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n  */\n-#define\tMC_CMD_TCM_TXQ_INIT 0xb5\n-#undef\tMC_CMD_0xb5_PRIVILEGE_CTG\n-\n-#define\tMC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n-\n-/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_LEN 28\n-/* the txq id */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4\n-/* the static priority associated with the txq */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4\n-/* bitmask of the priority queues this txq is inserted into when inserted. */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1\n-/* the reaction point (RP) bucket */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4\n-/* an already reserved bucket (typically set to bucket associated with outer\n- * vswitch)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n  */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4\n-/* an already reserved bucket (typically set to bucket associated with inner\n- * vswitch)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n  */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4\n-/* the min bucket (typically for ETS/minimum bandwidth) */\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24\n-#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4\n-\n-/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32\n-/* the txq id */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4\n-/* the static priority associated with the txq */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4\n-/* bitmask of the priority queues this txq is inserted into when inserted. */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1\n-/* the reaction point (RP) bucket */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4\n-/* an already reserved bucket (typically set to bucket associated with outer\n- * vswitch)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)\n  */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4\n-/* an already reserved bucket (typically set to bucket associated with inner\n- * vswitch)\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n  */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4\n-/* the min bucket (typically for ETS/minimum bandwidth) */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4\n-/* the static priority associated with the txq */\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28\n-#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4\n-\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC (when\n+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+/* Entry count in the MAC stats array, including the final GENERATION_END\n+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to\n+ * hold at least this many 64-bit stats values, if they wish to receive all\n+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the\n+ * stats array returned will be truncated.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2\n+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field\n+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4\n+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in\n+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when\n+ * they create an RX queue. Due to hardware limitations, only a small number of\n+ * different buffer sizes may be available concurrently. Nonzero entries in\n+ * this array are the sizes of buffers which the system guarantees will be\n+ * available for use. If the list is empty, there are no limitations on\n+ * concurrent buffer sizes.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16\n+/* Third word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+\n+/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: DPDK RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: DPDK TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC (when\n+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+/* Entry count in the MAC stats array, including the final GENERATION_END\n+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to\n+ * hold at least this many 64-bit stats values, if they wish to receive all\n+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the\n+ * stats array returned will be truncated.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2\n+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field\n+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4\n+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in\n+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when\n+ * they create an RX queue. Due to hardware limitations, only a small number of\n+ * different buffer sizes may be available concurrently. Nonzero entries in\n+ * this array are the sizes of buffers which the system guarantees will be\n+ * available for use. If the list is empty, there are no limitations on\n+ * concurrent buffer sizes.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16\n+/* Third word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+/* These bits are reserved for communicating test-specific capabilities to\n+ * host-side test software. All production drivers should treat this field as\n+ * opaque.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156\n+\n+/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: DPDK RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: DPDK TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC (when\n+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+/* Entry count in the MAC stats array, including the final GENERATION_END\n+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to\n+ * hold at least this many 64-bit stats values, if they wish to receive all\n+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the\n+ * stats array returned will be truncated.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2\n+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field\n+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4\n+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in\n+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when\n+ * they create an RX queue. Due to hardware limitations, only a small number of\n+ * different buffer sizes may be available concurrently. Nonzero entries in\n+ * this array are the sizes of buffers which the system guarantees will be\n+ * available for use. If the list is empty, there are no limitations on\n+ * concurrent buffer sizes.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16\n+/* Third word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+/* These bits are reserved for communicating test-specific capabilities to\n+ * host-side test software. All production drivers should treat this field as\n+ * opaque.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156\n+/* The minimum size (in table entries) of indirection table to be allocated\n+ * from the pool for an RSS context. Note that the table size used must be a\n+ * power of 2.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4\n+/* The maximum size (in table entries) of indirection table to be allocated\n+ * from the pool for an RSS context. Note that the table size used must be a\n+ * power of 2.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4\n+/* The maximum number of queues that can be used by an RSS context in exclusive\n+ * mode. In exclusive mode the context has a configurable indirection table and\n+ * a configurable RSS key.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4\n+/* The maximum number of queues that can be used by an RSS context in even-\n+ * spreading mode. In even-spreading mode the context has no indirection table\n+ * but it does have a configurable RSS key.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4\n+/* The total number of RSS contexts supported. Note that the number of\n+ * available contexts using indirection tables is also limited by the\n+ * availability of indirection table space allocated from a common pool.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4\n+/* The total amount of indirection table space that can be shared between RSS\n+ * contexts.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180\n+#define\tMC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4\n+\n+/* MC_CMD_GET_CAPABILITIES_V10_OUT msgresponse */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_LEN 192\n+/* First word of flags. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_QBB_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_QBB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVB_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_WIDTH 1\n+/* RxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0\n+/* enum: Low latency RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1\n+/* enum: Packed stream RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2\n+/* enum: Rules engine RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5\n+/* enum: DPDK RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6\n+/* enum: BIST RXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a\n+/* enum: RXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101\n+/* enum: RXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102\n+/* enum: RXDP Test firmware image 3 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103\n+/* enum: RXDP Test firmware image 4 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104\n+/* enum: RXDP Test firmware image 5 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105\n+/* enum: RXDP Test firmware image 6 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106\n+/* enum: RXDP Test firmware image 7 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107\n+/* enum: RXDP Test firmware image 8 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108\n+/* enum: RXDP Test firmware image 9 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b\n+/* enum: RXDP Test firmware image 10 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c\n+/* TxDPCPU firmware id. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_OFST 6\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_LEN 2\n+/* enum: Standard TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0\n+/* enum: Low latency TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1\n+/* enum: High packet rate TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3\n+/* enum: Rules engine TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5\n+/* enum: DPDK TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6\n+/* enum: BIST TXDP firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d\n+/* enum: TXDP Test firmware image 1 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101\n+/* enum: TXDP Test firmware image 2 */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102\n+/* enum: TXDP CSR bus test firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_OFST 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial RX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: RX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant RX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+/* enum: Low latency RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5\n+/* enum: Packed stream RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6\n+/* enum: RX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK RX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* enum: RX PD firmware parsing but not filtering network overlay tunnel\n+ * encapsulations (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_WIDTH 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_OFST 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4\n+/* enum: reserved value - do not use (may indicate alternative interpretation\n+ * of REV field in future)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0\n+/* enum: Trivial TX PD firmware for early Huntington development (Huntington\n+ * development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1\n+/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1\n+/* enum: TX PD firmware with approximately Siena-compatible behaviour\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2\n+/* enum: Full featured TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3\n+/* enum: (deprecated original name for the FULL_FEATURED variant) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3\n+/* enum: siena_compat variant TX PD firmware using PM rather than MAC\n+ * (Huntington development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */\n+/* enum: TX PD firmware handling layer 2 only for high packet rate performance\n+ * tests (Medford development only)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7\n+/* enum: Rules engine TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8\n+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9\n+/* enum: DPDK TX PD production firmware */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa\n+/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe\n+/* Hardware capabilities of NIC */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_OFST 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4\n+/* Licensed capabilities */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_OFST 16\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4\n+/* Second word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_LBN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_LBN 9\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_LBN 10\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_LBN 11\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_LBN 13\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_LBN 14\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_LBN 15\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_LBN 16\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_LBN 17\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_LBN 19\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_LBN 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_LBN 22\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_LBN 24\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_LBN 25\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_LBN 26\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_LBN 28\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_LBN 29\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_LBN 30\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1\n+/* Number of FATSOv2 contexts per datapath supported by this NIC (when\n+ * TX_TSO_V2 == 1). Not present on older firmware (check the length).\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2\n+/* One byte per PF containing the number of the external port assigned to this\n+ * PF, indexed by PF number. Special values indicate that a PF is either not\n+ * present or not assigned.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff\n+/* enum: PF does not exist. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe\n+/* enum: PF does exist but is not assigned to any external port. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd\n+/* enum: This value indicates that PF is assigned, but it cannot be expressed\n+ * in this field. It is intended for a possible future situation where a more\n+ * complex scheme of PFs to ports mapping is being used. The future driver\n+ * should look for a new field supporting the new scheme. The current/old\n+ * driver should treat this value as PF_NOT_ASSIGNED.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc\n+/* One byte per PF containing the number of its VFs, indexed by PF number. A\n+ * special value indicates that a PF is not present.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_OFST 42\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_LEN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_NUM 16\n+/* enum: The caller is not permitted to access information on this PF. */\n+/*               MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */\n+/* enum: PF does not exist. */\n+/*               MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */\n+/* Number of VIs available for each external port */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4\n+/* Size of RX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ RX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_OFST 66\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_LEN 1\n+/* Size of TX descriptor cache expressed as binary logarithm The actual size\n+ * equals (2 ^ TX_DESC_CACHE_SIZE)\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_OFST 67\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_LEN 1\n+/* Total number of available PIO buffers */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_OFST 68\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_LEN 2\n+/* Size of a single PIO buffer */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_OFST 70\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_LEN 2\n+/* On chips later than Medford the amount of address space assigned to each VI\n+ * is configurable. This is a global setting that the driver must query to\n+ * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available\n+ * with 8k VI windows.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_OFST 72\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_LEN 1\n+/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.\n+ * CTPIO is not mapped.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0\n+/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1\n+/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2\n+/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1\n+/* Number of buffers per adapter that can be used for VFIFO Stuffing\n+ * (SF-115995-SW) in the present configuration of firmware and port mode.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2\n+/* Entry count in the MAC stats array, including the final GENERATION_END\n+ * entry. For MAC stats DMA, drivers should allocate a buffer large enough to\n+ * hold at least this many 64-bit stats values, if they wish to receive all\n+ * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the\n+ * stats array returned will be truncated.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_OFST 76\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_LEN 2\n+/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field\n+ * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_OFST 80\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4\n+/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in\n+ * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when\n+ * they create an RX queue. Due to hardware limitations, only a small number of\n+ * different buffer sizes may be available concurrently. Nonzero entries in\n+ * this array are the sizes of buffers which the system guarantees will be\n+ * available for use. If the list is empty, there are no limitations on\n+ * concurrent buffer sizes.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16\n+/* Third word of flags. Not present on older firmware (check the length). */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_LBN 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_LBN 3\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1\n+/* These bits are reserved for communicating test-specific capabilities to\n+ * host-side test software. All production drivers should treat this field as\n+ * opaque.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156\n+/* The minimum size (in table entries) of indirection table to be allocated\n+ * from the pool for an RSS context. Note that the table size used must be a\n+ * power of 2.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4\n+/* The maximum size (in table entries) of indirection table to be allocated\n+ * from the pool for an RSS context. Note that the table size used must be a\n+ * power of 2.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4\n+/* The maximum number of queues that can be used by an RSS context in exclusive\n+ * mode. In exclusive mode the context has a configurable indirection table and\n+ * a configurable RSS key.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4\n+/* The maximum number of queues that can be used by an RSS context in even-\n+ * spreading mode. In even-spreading mode the context has no indirection table\n+ * but it does have a configurable RSS key.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4\n+/* The total number of RSS contexts supported. Note that the number of\n+ * available contexts using indirection tables is also limited by the\n+ * availability of indirection table space allocated from a common pool.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_OFST 176\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4\n+/* The total amount of indirection table space that can be shared between RSS\n+ * contexts.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_OFST 180\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4\n+/* A bitmap of the queue sizes the device can provide, where bit N being set\n+ * indicates that 2**N is a valid size. The device may be limited in the number\n+ * of different queue sizes that can exist simultaneously, so a bit being set\n+ * here does not guarantee that an attempt to create a queue of that size will\n+ * succeed.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_OFST 184\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4\n+/* A bitmap of queue sizes that are always available, in the same format as\n+ * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes\n+ * will never fail due to unavailability of the requested size.\n+ */\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188\n+#define\tMC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_V2_EXTN\n+ * Encapsulation for a v2 extended command\n+ */\n+#define\tMC_CMD_V2_EXTN 0x7f\n+\n+/* MC_CMD_V2_EXTN_IN msgrequest */\n+#define\tMC_CMD_V2_EXTN_IN_LEN 4\n+/* the extended command number */\n+#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0\n+#define\tMC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED_LBN 15\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1\n+/* the actual length of the encapsulated command (which is not in the v1\n+ * header)\n+ */\n+#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16\n+#define\tMC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED2_LBN 26\n+#define\tMC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2\n+/* Type of command/response */\n+#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28\n+#define\tMC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4\n+/* enum: MCDI command directed to or response originating from the MC. */\n+#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0\n+/* enum: MCDI command directed to a TSA controller. MCDI responses of this type\n+ * are not defined.\n+ */\n+#define\tMC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_ALLOC\n+ * Allocate a pacer bucket (for qau rp or a snapper test)\n+ */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC 0xb2\n+#undef\tMC_CMD_0xb2_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0\n+\n+/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_FREE\n+ * Free a pacer bucket\n+ */\n+#define\tMC_CMD_TCM_BUCKET_FREE 0xb3\n+#undef\tMC_CMD_0xb3_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_LEN 4\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4\n+\n+/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_FREE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_BUCKET_INIT\n+ * Initialise pacer bucket with a given rate\n+ */\n+#define\tMC_CMD_TCM_BUCKET_INIT 0xb4\n+#undef\tMC_CMD_0xb4_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_LEN 8\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4\n+/* the rate in mbps */\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4\n+#define\tMC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4\n+\n+/* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12\n+/* the bucket id */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4\n+/* the rate in mbps */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4\n+/* the desired maximum fill level */\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8\n+#define\tMC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4\n+\n+/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */\n+#define\tMC_CMD_TCM_BUCKET_INIT_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_TCM_TXQ_INIT\n+ * Initialise txq in pacer with given options or set options\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT 0xb5\n+#undef\tMC_CMD_0xb5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LEN 28\n+/* the txq id */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4\n+/* bitmask of the priority queues this txq is inserted into when inserted. */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1\n+/* the reaction point (RP) bucket */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4\n+/* an already reserved bucket (typically set to bucket associated with outer\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4\n+/* an already reserved bucket (typically set to bucket associated with inner\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4\n+/* the min bucket (typically for ETS/minimum bandwidth) */\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24\n+#define\tMC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4\n+\n+/* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32\n+/* the txq id */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4\n+/* bitmask of the priority queues this txq is inserted into when inserted. */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_OFST 8\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1\n+/* the reaction point (RP) bucket */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4\n+/* an already reserved bucket (typically set to bucket associated with outer\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4\n+/* an already reserved bucket (typically set to bucket associated with inner\n+ * vswitch)\n+ */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4\n+/* the min bucket (typically for ETS/minimum bandwidth) */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4\n+/* the static priority associated with the txq */\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28\n+#define\tMC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4\n+\n /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */\n #define\tMC_CMD_TCM_TXQ_INIT_OUT_LEN 0\n \n@@ -13387,6 +16500,7 @@\n /* Flags controlling v-port creation */\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4\n+#define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n #define\tMC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,\n@@ -13481,8 +16595,10 @@\n /* Flags controlling v-port creation */\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1\n+#define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1\n #define\tMC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1\n /* The number of VLAN tags to insert/remove. An error will be returned if\n@@ -13494,8 +16610,10 @@\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16\n #define\tMC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16\n \n@@ -13542,8 +16660,10 @@\n /* Flags controlling v-adaptor creation */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1\n /* The number of VLAN tags to strip on receive */\n@@ -13555,8 +16675,10 @@\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16\n #define\tMC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16\n /* The MAC address to assign to this v-adaptor */\n@@ -13677,8 +16799,10 @@\n /* The target function to modify. */\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16\n+#define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16\n #define\tMC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16\n \n@@ -13792,12 +16916,68 @@\n  * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.\n  */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1\n-/* Number of queues spanned by this context, in the range 1-64; valid offsets\n- * in the indirection table will be in the range 0 to NUM_QUEUES-1.\n+/* enum: Allocate a context to spread evenly across an arbitrary number of\n+ * queues. No indirection table space is allocated for this context. (EF100 and\n+ * later)\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2\n+/* Number of queues spanned by this context. For exclusive contexts this must\n+ * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where\n+ * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if\n+ * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in\n+ * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-\n+ * spreading contexts this must be in the range 1 to\n+ * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note\n+ * that specifying NUM_QUEUES = 1 will not perform any spreading but may still\n+ * be useful as a way of obtaining the Toeplitz hash.\n  */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4\n \n+/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16\n+/* The handle of the owning upstream port */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4\n+/* The type of context to allocate */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4\n+/* enum: Allocate a context for exclusive use. The key and indirection table\n+ * must be explicitly configured.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0\n+/* enum: Allocate a context for shared use; this will spread across a range of\n+ * queues, but the key and indirection table are pre-configured and may not be\n+ * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1\n+/* enum: Allocate a context to spread evenly across an arbitrary number of\n+ * queues. No indirection table space is allocated for this context. (EF100 and\n+ * later)\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2\n+/* Number of queues spanned by this context. For exclusive contexts this must\n+ * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where\n+ * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if\n+ * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in\n+ * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-\n+ * spreading contexts this must be in the range 1 to\n+ * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note\n+ * that specifying NUM_QUEUES = 1 will not perform any spreading but may still\n+ * be useful as a way of obtaining the Toeplitz hash.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4\n+/* Size of indirection table to be allocated to this context from the pool.\n+ * Must be a power of 2. The minimum and maximum table size can be queried\n+ * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in\n+ * the common pool to allocate the requested table size, due to allocating\n+ * table space to other RSS contexts, then the command will fail with\n+ * MC_CMD_ERR_ENOSPC.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12\n+#define\tMC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4\n+\n /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */\n #define\tMC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4\n /* The handle of the new RSS context. This should be considered opaque to the\n@@ -13875,7 +17055,9 @@\n \n /***********************************/\n /* MC_CMD_RSS_CONTEXT_SET_TABLE\n- * Set the indirection table for an RSS context.\n+ * Set the indirection table for an RSS context. This command should only be\n+ * used with indirection tables containing 128 entries, which is the default\n+ * when the RSS context is allocated without specifying a table size.\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_TABLE 0xa2\n #undef\tMC_CMD_0xa2_PRIVILEGE_CTG\n@@ -13897,7 +17079,9 @@\n \n /***********************************/\n /* MC_CMD_RSS_CONTEXT_GET_TABLE\n- * Get the indirection table for an RSS context.\n+ * Get the indirection table for an RSS context. This command should only be\n+ * used with indirection tables containing 128 entries, which is the default\n+ * when the RSS context is allocated without specifying a table size.\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE 0xa3\n #undef\tMC_CMD_0xa3_PRIVILEGE_CTG\n@@ -13917,6 +17101,93 @@\n #define\tMC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128\n \n \n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE\n+ * Write a portion of a selectable-size indirection table for an RSS context.\n+ * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the\n+ * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e\n+#undef\tMC_CMD_0x13e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4\n+/* An array of index-value pairs to be written to the table. Structure is\n+ * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254\n+\n+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0\n+\n+/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4\n+/* The index of the table entry to be written. */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16\n+/* The value to write into the table entry. */\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16\n+#define\tMC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16\n+\n+\n+/***********************************/\n+/* MC_CMD_RSS_CONTEXT_READ_TABLE\n+ * Read a portion of a selectable-size indirection table for an RSS context.\n+ * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the\n+ * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.\n+ */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE 0x13f\n+#undef\tMC_CMD_0x13f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)\n+/* The handle of the RSS context */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4\n+/* An array containing the indices of the entries to be read. */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508\n+\n+/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)\n+/* A buffer containing the requested entries read from the table. */\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126\n+#define\tMC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510\n+\n+\n /***********************************/\n /* MC_CMD_RSS_CONTEXT_SET_FLAGS\n  * Set various control flags for an RSS context.\n@@ -13945,26 +17216,37 @@\n  */\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28\n #define\tMC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4\n \n@@ -14004,26 +17286,37 @@\n  */\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4\n+#define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28\n #define\tMC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4\n \n@@ -14275,8 +17568,10 @@\n /* Flags requesting what should be changed. */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1\n /* The number of VLAN tags to insert/remove. An error will be returned if\n@@ -14288,8 +17583,10 @@\n /* The actual VLAN tags to insert/remove */\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16\n+#define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16\n #define\tMC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16\n /* The number of MAC addresses to add */\n@@ -14304,6 +17601,7 @@\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_LEN 4\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0\n #define\tMC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1\n \n@@ -14383,8 +17681,10 @@\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_LEN 4\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1\n+#define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1\n #define\tMC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2\n /* enum: pad to 64 bytes */\n@@ -14414,8 +17714,10 @@\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_LEN 4\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1\n+#define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1\n #define\tMC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2\n /*             Enum values, see field(s): */\n@@ -14564,6 +17866,7 @@\n  */\n #define\tMC_CMD_DPCPU_RPC_IN_DATA_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_DATA_LEN 32\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8\n #define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */\n@@ -14575,14 +17878,19 @@\n #define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48\n #define\tMC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */\n@@ -14590,17 +17898,22 @@\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80\n #define\tMC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */\n+#define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64\n #define\tMC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16\n #define\tMC_CMD_DPCPU_RPC_IN_WDATA_OFST 12\n@@ -14619,8 +17932,10 @@\n /* DATA */\n #define\tMC_CMD_DPCPU_RPC_OUT_DATA_OFST 4\n #define\tMC_CMD_DPCPU_RPC_OUT_DATA_LEN 32\n+#define\tMC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4\n #define\tMC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32\n #define\tMC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16\n+#define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48\n #define\tMC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16\n #define\tMC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12\n@@ -15122,6 +18437,7 @@\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8\n /* enum: Attenuation (0-15, Huntington) */\n@@ -15248,6 +18564,7 @@\n /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))\n  */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */\n@@ -15255,12 +18572,16 @@\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n #define\tMC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n \n@@ -15282,20 +18603,26 @@\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8\n /*             Enum values, see field(s): */\n /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3\n /*             Enum values, see field(s): */\n /*                MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24\n #define\tMC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8\n \n@@ -15323,6 +18650,7 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8\n /* enum: TX Amplitude (Huntington, Medford, Medford2) */\n@@ -15363,6 +18691,7 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11\n /* enum: Post-cursor Tap (Retimer Hostside) */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */\n@@ -15370,10 +18699,13 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24\n #define\tMC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8\n \n@@ -15395,18 +18727,23 @@\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8\n /*             Enum values, see field(s): */\n /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3\n /*             Enum values, see field(s): */\n /*                MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24\n #define\tMC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8\n \n@@ -15447,8 +18784,10 @@\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31\n #define\tMC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1\n /* Scan duration / cycle count */\n@@ -15489,8 +18828,10 @@\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8\n+#define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31\n #define\tMC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1\n \n@@ -15644,6 +18985,7 @@\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8\n /* enum: Attenuation (0-15) */\n@@ -15668,6 +19010,7 @@\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9\n /* enum: CTLE EQ Resistor (DC Gain) */\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */\n@@ -15687,10 +19030,13 @@\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n #define\tMC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n \n@@ -15712,20 +19058,26 @@\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8\n /*             Enum values, see field(s): */\n /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5\n /*             Enum values, see field(s): */\n /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8\n+#define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24\n #define\tMC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8\n \n@@ -15753,6 +19105,7 @@\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8\n /* enum: TxMargin (PIPE) */\n@@ -15765,12 +19118,15 @@\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3\n /* enum: De-emphasis coefficient C(+1) (PIPE) */\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4\n /*             Enum values, see field(s): */\n /*                MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12\n+#define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24\n #define\tMC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8\n \n@@ -16335,8 +19691,10 @@\n /* configuration flags */\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n+#define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1\n #define\tMC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1\n /* receive queue handle (for RSS mode, this is the base queue) */\n@@ -16379,8 +19737,10 @@\n /* configuration flags */\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n+#define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1\n #define\tMC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1\n /* receiving queue handle (for RSS mode, this is the base queue) */\n@@ -16501,6 +19861,7 @@\n /* configuration flags */\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0\n #define\tMC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1\n /* receive queue handle (for RSS mode, this is the base queue) */\n@@ -16543,6 +19904,7 @@\n /* configuration flags */\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0\n #define\tMC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1\n /* receiving queue handle (for RSS mode, this is the base queue) */\n@@ -16576,6 +19938,7 @@\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4\n+#define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0\n #define\tMC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1\n \n@@ -16699,6 +20062,7 @@\n #define\tMC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8\n #define\tMC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0\n #define\tMC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4\n+#define\tMC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0\n #define\tMC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0\n #define\tMC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1\n /* New mode (TLV_PORT_MODE_*) to set, if override enabled */\n@@ -16792,8 +20156,10 @@\n  */\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16\n #define\tMC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16\n #define\tMC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */\n@@ -16866,8 +20232,10 @@\n  */\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16\n #define\tMC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16\n /* New link state mode to be set */\n@@ -16986,8 +20354,10 @@\n /* For VFS_OF_PF specify the PF, for ONE specify the target function */\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16\n+#define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16\n #define\tMC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16\n /* Privileges to be added to the target functions. For privilege definitions\n@@ -17342,34 +20712,49 @@\n /* fields to include in match criteria */\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_OFST 0\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14\n #define\tMC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1\n /* remote MAC address to match (as bytes in network order) */\n@@ -17792,6 +21177,7 @@\n /* Flags */\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1\n /* The number of entries in the ENTRIES array */\n@@ -17811,6 +21197,7 @@\n /* Flags */\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2\n+#define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0\n #define\tMC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1\n \n@@ -18871,10 +22258,13 @@\n /* Flags specifying what type of security features are being set */\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_OFST 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_OFST 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1\n+#define\tMC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_OFST 0\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31\n #define\tMC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1\n \n@@ -18909,6 +22299,7 @@\n #define\tMC_CMD_TSA_INFO_IN_LEN 4\n #define\tMC_CMD_TSA_INFO_IN_OP_HDR_OFST 0\n #define\tMC_CMD_TSA_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_OP_OFST 0\n #define\tMC_CMD_TSA_INFO_IN_OP_LBN 0\n #define\tMC_CMD_TSA_INFO_IN_OP_WIDTH 16\n /* enum: Information about recently discovered local IP address of the adapter\n@@ -18946,10 +22337,13 @@\n  */\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8\n /* enum: ARP reply sent out of the physical port */\n@@ -18960,8 +22354,10 @@\n #define\tMC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2\n /* enum: DHCP ACK packet received on the physical port */\n #define\tMC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25\n #define\tMC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7\n /* IPV4 address retrieved from the sampled packets. This field is relevant only\n@@ -19001,18 +22397,25 @@\n /* Additional metadata describing the sampled packet */\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1\n+#define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_OFST 4\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18\n #define\tMC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1\n /* 128-byte raw prefix of the sampled packet which includes the ethernet\n@@ -19034,6 +22437,7 @@\n #define\tMC_CMD_TSA_INFO_IN_UNBIND_LEN 12\n #define\tMC_CMD_TSA_INFO_IN_UNBIND_OP_HDR_OFST 0\n #define\tMC_CMD_TSA_INFO_IN_UNBIND_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_INFO_IN_UNBIND_OP_OFST 0\n #define\tMC_CMD_TSA_INFO_IN_UNBIND_OP_LBN 0\n #define\tMC_CMD_TSA_INFO_IN_UNBIND_OP_WIDTH 16\n /* Type of the unbind attempt. */\n@@ -19072,6 +22476,7 @@\n /* sub-operation code info */\n #define\tMC_CMD_HOST_INFO_IN_OP_HDR_OFST 0\n #define\tMC_CMD_HOST_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_HOST_INFO_IN_OP_OFST 0\n #define\tMC_CMD_HOST_INFO_IN_OP_LBN 0\n #define\tMC_CMD_HOST_INFO_IN_OP_WIDTH 16\n /* enum: Read a 16-byte unique host identifier from the adapter. This UUID\n@@ -19138,6 +22543,7 @@\n /* sub-operation code info */\n #define\tMC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0\n #define\tMC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSAN_INFO_IN_OP_OFST 0\n #define\tMC_CMD_TSAN_INFO_IN_OP_LBN 0\n #define\tMC_CMD_TSAN_INFO_IN_OP_WIDTH 16\n /* enum: Read configuration parameters and IDs that uniquely identify an\n@@ -19157,10 +22563,13 @@\n /* Information about the configuration parameters returned in this response. */\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8\n /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID\n@@ -19181,10 +22590,13 @@\n /* Information about the configuration parameters returned in this response. */\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_LEN 4\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_LBN 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_WIDTH 16\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_LBN 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_WIDTH 1\n+#define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_OFST 0\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_LBN 16\n #define\tMC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_WIDTH 8\n /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID\n@@ -19270,8 +22682,10 @@\n /* Parameters describing the statistics operation */\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_OFST 4\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1\n+#define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_OFST 4\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1\n #define\tMC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1\n /* Counter ID list specification type */\n@@ -19458,6 +22872,7 @@\n  */\n #define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0\n #define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4\n+#define\tMC_TSA_IPV4_ITEM_PORT_IDX_OFST 0\n #define\tMC_TSA_IPV4_ITEM_PORT_IDX_LBN 0\n #define\tMC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8\n #define\tMC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0\n@@ -19488,6 +22903,7 @@\n  */\n #define\tMC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_OP_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_OP_LBN 0\n #define\tMC_CMD_TSA_IPADDR_IN_OP_WIDTH 16\n /* enum: Request that the adapter verifies that the IPv4 addresses supplied are\n@@ -19516,6 +22932,7 @@\n  */\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0\n #define\tMC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16\n /* Number of IPv4 addresses to validate. */\n@@ -19545,6 +22962,7 @@\n  */\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4\n+#define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_OFST 0\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0\n #define\tMC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16\n /* Number of IPv4 addresses to remove. */\n@@ -19579,6 +22997,7 @@\n /* sub-operation code info */\n #define\tMC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0\n #define\tMC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_SECURE_NIC_INFO_IN_OP_OFST 0\n #define\tMC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0\n #define\tMC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16\n /* enum: Get the status of various security settings, all signed along with a\n@@ -19811,6 +23230,12 @@\n  * FRU_INFORMATION partition. Attempts to write to read-only FRUs are rejected.\n  */\n #define\tMC_CMD_SUC_MANFTEST_FRU_WRITE 0x7\n+/* enum: Read UDID Vendor Specific ID from SUC persistent storage. */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ 0x8\n+/* enum: Write UDID Vendor Specific ID to SUC persistent storage for use in\n+ * SMBus ARP.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE 0x9\n \n /* MC_CMD_SUC_MANFTEST_OUT msgresponse */\n #define\tMC_CMD_SUC_MANFTEST_OUT_LEN 0\n@@ -19867,12 +23292,16 @@\n /* The combined status of the calibration operation. */\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_OFST 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_OFST 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_OFST 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4\n+#define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_OFST 0\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6\n #define\tMC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2\n \n@@ -19936,6 +23365,34 @@\n /* MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT msgresponse */\n #define\tMC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0\n \n+/* MC_CMD_SUC_MANFTEST_SMBUS_ID_READ_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_IN_LEN 4\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_SMBUS_ID_READ.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_IN_OP_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_SMBUS_ID_READ_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_OUT_LEN 4\n+/* The SMBus ID. */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_OUT_SMBUS_ID_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_READ_OUT_SMBUS_ID_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN msgrequest */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN_LEN 8\n+/* The manftest operation to be performed. This must be\n+ * MC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE.\n+ */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN_OP_OFST 0\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN_OP_LEN 4\n+/* The SMBus ID. */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN_SMBUS_ID_OFST 4\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_IN_SMBUS_ID_LEN 4\n+\n+/* MC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_OUT msgresponse */\n+#define\tMC_CMD_SUC_MANFTEST_SMBUS_ID_WRITE_OUT_LEN 0\n+\n \n /***********************************/\n /* MC_CMD_GET_CERTIFICATE\n@@ -20112,10 +23569,13 @@\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_NUM(len) (((len)-8)/8)\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_OFST 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_OFST 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_LBN 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_WIDTH 1\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_OFST 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_LBN 1\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_WIDTH 1\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_OFST 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_LBN 31\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_WIDTH 1\n /* The number of rows present in this response. */\n@@ -20128,12 +23588,16 @@\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM_MCDI2 126\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_OFST 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_LBN 0\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_WIDTH 6\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_OFST 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_LBN 6\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_WIDTH 1\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_OFST 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_LBN 7\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_WIDTH 1\n+#define\tMC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_OFST 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_LBN 8\n #define\tMC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_WIDTH 24\n /* The time of the LTSSM transition. Times are reported as fractional\n@@ -20184,14 +23648,19 @@\n  */\n #define\tTELEMETRY_CONFIG_FLAGS_OFST 0\n #define\tTELEMETRY_CONFIG_FLAGS_LEN 4\n+#define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_IP_VALID_OFST 0\n #define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_IP_VALID_LBN 0\n #define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_IP_VALID_WIDTH 1\n+#define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_PORT_VALID_OFST 0\n #define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_PORT_VALID_LBN 1\n #define\tTELEMETRY_CONFIG_METRICS_COLLECTOR_PORT_VALID_WIDTH 1\n+#define\tTELEMETRY_CONFIG_MONITOR_TIMEOUT_MS_VALID_OFST 0\n #define\tTELEMETRY_CONFIG_MONITOR_TIMEOUT_MS_VALID_LBN 2\n #define\tTELEMETRY_CONFIG_MONITOR_TIMEOUT_MS_VALID_WIDTH 1\n+#define\tTELEMETRY_CONFIG_MAX_METRICS_COUNT_VALID_OFST 0\n #define\tTELEMETRY_CONFIG_MAX_METRICS_COUNT_VALID_LBN 3\n #define\tTELEMETRY_CONFIG_MAX_METRICS_COUNT_VALID_WIDTH 1\n+#define\tTELEMETRY_CONFIG_RESERVED1_OFST 0\n #define\tTELEMETRY_CONFIG_RESERVED1_LBN 4\n #define\tTELEMETRY_CONFIG_RESERVED1_WIDTH 28\n #define\tTELEMETRY_CONFIG_FLAGS_LBN 0\n@@ -20320,24 +23789,34 @@\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LEN 8\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_LBN 2\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_CLASS_LBN 3\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_LBN 5\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_LBN 6\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_LBN 7\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_LBN 8\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1\n+#define\tMC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_LBN 9\n #define\tMC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1\n \n@@ -20534,36 +24013,24 @@\n \n /* MC_CMD_GET_VPD_IN msgresponse */\n #define\tMC_CMD_GET_VPD_IN_LEN 4\n-/* To request only VPD tags from a certain origin. */\n-#define\tMC_CMD_GET_VPD_IN_STORAGE_TYPE_OFST 0\n-#define\tMC_CMD_GET_VPD_IN_STORAGE_TYPE_LEN 2\n-/* enum: Return all VPD regardless of origin. */\n-#define\tMC_CMD_GET_VPD_IN_STORAGE_TYPE_ALL 0x0\n-/* enum: Return only VPD tags generated by MCFW (not stored in NVRAM) */\n-#define\tMC_CMD_GET_VPD_IN_STORAGE_TYPE_LIVE 0x1\n-/* enum: Return only VPD tags stored in NVRAM (not generated by MCFW) */\n-#define\tMC_CMD_GET_VPD_IN_STORAGE_TYPE_NVRAM 0x2\n /* VPD address to start from. In case VPD is longer than MCDI buffer\n  * (unlikely), user can make multiple calls with different starting addresses.\n  */\n-#define\tMC_CMD_GET_VPD_IN_ADDR_OFST 2\n-#define\tMC_CMD_GET_VPD_IN_ADDR_LEN 2\n+#define\tMC_CMD_GET_VPD_IN_ADDR_OFST 0\n+#define\tMC_CMD_GET_VPD_IN_ADDR_LEN 4\n \n /* MC_CMD_GET_VPD_OUT msgresponse */\n-#define\tMC_CMD_GET_VPD_OUT_LENMIN 5\n+#define\tMC_CMD_GET_VPD_OUT_LENMIN 0\n #define\tMC_CMD_GET_VPD_OUT_LENMAX 252\n #define\tMC_CMD_GET_VPD_OUT_LENMAX_MCDI2 1020\n-#define\tMC_CMD_GET_VPD_OUT_LEN(num) (4+1*(num))\n-#define\tMC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-4)/1)\n-/* Length of VPD data returned. */\n-#define\tMC_CMD_GET_VPD_OUT_DATALEN_OFST 0\n-#define\tMC_CMD_GET_VPD_OUT_DATALEN_LEN 4\n+#define\tMC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))\n+#define\tMC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)\n /* VPD data returned. */\n-#define\tMC_CMD_GET_VPD_OUT_DATA_OFST 4\n+#define\tMC_CMD_GET_VPD_OUT_DATA_OFST 0\n #define\tMC_CMD_GET_VPD_OUT_DATA_LEN 1\n-#define\tMC_CMD_GET_VPD_OUT_DATA_MINNUM 1\n-#define\tMC_CMD_GET_VPD_OUT_DATA_MAXNUM 248\n-#define\tMC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1016\n+#define\tMC_CMD_GET_VPD_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_GET_VPD_OUT_DATA_MAXNUM 252\n+#define\tMC_CMD_GET_VPD_OUT_DATA_MAXNUM_MCDI2 1020\n \n \n /***********************************/\n@@ -20599,12 +24066,16 @@\n /* General status */\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_OFST 8\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4\n+#define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_OFST 8\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_WIDTH 2\n+#define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_OFST 8\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_LBN 2\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1\n+#define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_OFST 8\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_LBN 3\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1\n+#define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_OFST 8\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4\n #define\tMC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1\n \n@@ -20632,59 +24103,55 @@\n #define\tMC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_OFST 24\n #define\tMC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4\n \n-/* EF100_MCDI_EVENT structuredef: The structure of an MCDI_EVENT on EF100\n- * platforms\n+\n+/***********************************/\n+/* MC_CMD_FIRMWARE_SET_LOCKDOWN\n+ * System lockdown, when enabled firmware updates are blocked.\n  */\n-#define\tEF100_MCDI_EVENT_LEN 8\n-/* Defined by QMDA. Will be 1 for all SFC events */\n-#define\tEF100_MCDI_EVENT_EV_DATA_FORMAT_LBN 0\n-#define\tEF100_MCDI_EVENT_EV_DATA_FORMAT_WIDTH 1\n-/* Defined by QMDA. The phase bit, changes each time round the event ring */\n-#define\tEF100_MCDI_EVENT_EV_EVQ_PHASE_LBN 1\n-#define\tEF100_MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1\n-/* Defined by QDMA. Meaning unclear. */\n-#define\tEF100_MCDI_EVENT_EV_ERROR_LBN 2\n-#define\tEF100_MCDI_EVENT_EV_ERROR_WIDTH 1\n-/* Defined by QMDA. Indicates a descriptor was consumed. */\n-#define\tEF100_MCDI_EVENT_EV_DESC_USED_LBN 3\n-#define\tEF100_MCDI_EVENT_EV_DESC_USED_WIDTH 1\n-/* Indicates the top-level type of the event. Event types are as documented in\n- * SF-119689-TC and defined in events.yml. For MCDI events it's always\n- * EF100_EV_MCDI. HW can generate other event type for its events.\n- */\n-#define\tEF100_MCDI_EVENT_EV_TYPE_LBN 4\n-#define\tEF100_MCDI_EVENT_EV_TYPE_WIDTH 4\n-#define\tEF100_MCDI_EVENT_CODE_OFST 1\n-#define\tEF100_MCDI_EVENT_CODE_LEN 1\n-/*            Enum values, see field(s): */\n-/*               MCDI_EVENT/CODE */\n-#define\tEF100_MCDI_EVENT_CODE_LBN 8\n-#define\tEF100_MCDI_EVENT_CODE_WIDTH 8\n-/* Data associated with PTP events which doesn't fit into the main DATA field\n+#define\tMC_CMD_FIRMWARE_SET_LOCKDOWN 0x16f\n+#undef\tMC_CMD_0x16f_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16f_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_FIRMWARE_SET_LOCKDOWN_IN msgrequest: This MCDI command is to enable\n+ * only because lockdown can only be disabled by a PMCI command or a cold reset\n+ * of the system.\n  */\n-#define\tEF100_MCDI_EVENT_PTP_DATA_OFST 2\n-#define\tEF100_MCDI_EVENT_PTP_DATA_LEN 1\n-#define\tEF100_MCDI_EVENT_PTP_DATA_LBN 16\n-#define\tEF100_MCDI_EVENT_PTP_DATA_WIDTH 8\n-/* Alias for PTP_DATA. Nobody uses SRC to mean the source of anything, but\n- * there's code that uses it to refer to ptp data\n- */\n-#define\tEF100_MCDI_EVENT_SRC_OFST 2\n-#define\tEF100_MCDI_EVENT_SRC_LEN 1\n-#define\tEF100_MCDI_EVENT_SRC_LBN 16\n-#define\tEF100_MCDI_EVENT_SRC_WIDTH 8\n-/* Set if this message continues into another event */\n-#define\tEF100_MCDI_EVENT_CONT_LBN 24\n-#define\tEF100_MCDI_EVENT_CONT_WIDTH 1\n-#define\tEF100_MCDI_EVENT_LEVEL_LBN 25\n-#define\tEF100_MCDI_EVENT_LEVEL_WIDTH 3\n-/*            Enum values, see field(s): */\n-/*               MCDI_EVENT/LEVEL */\n-/* Data associated with this event. Format depends on the event code. */\n-#define\tEF100_MCDI_EVENT_DATA_OFST 4\n-#define\tEF100_MCDI_EVENT_DATA_LEN 4\n-#define\tEF100_MCDI_EVENT_DATA_LBN 32\n-#define\tEF100_MCDI_EVENT_DATA_WIDTH 32\n+#define\tMC_CMD_FIRMWARE_SET_LOCKDOWN_IN_LEN 0\n+\n+/* MC_CMD_FIRMWARE_SET_LOCKDOWN_OUT msgresponse */\n+#define\tMC_CMD_FIRMWARE_SET_LOCKDOWN_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_TEST_FEATURES\n+ * This command returns device details knowledge of which may be required by\n+ * test infrastructure. Although safe, it is not intended to be used by\n+ * production drivers, and the structure returned intentionally has no public\n+ * documentation.\n+ */\n+#define\tMC_CMD_GET_TEST_FEATURES 0x1ac\n+#undef\tMC_CMD_0x1ac_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1ac_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_GET_TEST_FEATURES_IN msgrequest: Request test features. */\n+#define\tMC_CMD_GET_TEST_FEATURES_IN_LEN 0\n+\n+/* MC_CMD_GET_TEST_FEATURE_OUT msgresponse */\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_LENMIN 4\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_LENMAX 252\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_LEN(num) (0+4*(num))\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_NUM(len) (((len)-0)/4)\n+/* Test-specific NIC information. Production drivers must treat this as opaque.\n+ * The layout is defined in the private TEST_FEATURES_LAYOUT structure.\n+ */\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_OFST 0\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_LEN 4\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MINNUM 1\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM 63\n+#define\tMC_CMD_GET_TEST_FEATURE_OUT_TEST_FEATURES_MAXNUM_MCDI2 255\n \n /* CLOCK_INFO structuredef: Information about a single hardware clock */\n #define\tCLOCK_INFO_LEN 28\n@@ -20710,6 +24177,7 @@\n /* Assorted flags */\n #define\tCLOCK_INFO_FLAGS_OFST 2\n #define\tCLOCK_INFO_FLAGS_LEN 2\n+#define\tCLOCK_INFO_SETTABLE_OFST 2\n #define\tCLOCK_INFO_SETTABLE_LBN 0\n #define\tCLOCK_INFO_SETTABLE_WIDTH 1\n #define\tCLOCK_INFO_FLAGS_LBN 16\n@@ -20754,4 +24222,1481 @@\n #define\tMC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM 9\n #define\tMC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MAXNUM_MCDI2 36\n \n+\n+/***********************************/\n+/* MC_CMD_VNIC_ENCAP_RULE_ADD\n+ * Add a rule for detecting encapsulations in the VNIC stage. Currently this\n+ * only affects checksum validation in VNIC RX - on TX the send descriptor\n+ * explicitly specifies encapsulation. These rules are per-VNIC, i.e. only\n+ * apply to the current driver. If a rule matches, then the packet is\n+ * considered to have the corresponding encapsulation type, and the inner\n+ * packet is parsed. It is up to the driver to ensure that overlapping rules\n+ * are not inserted. (If a packet would match multiple rules, a random one of\n+ * them will be used.) A rule with the exact same match criteria may not be\n+ * inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are\n+ * supported, use MC_CMD_GET_PARSER_DISP_INFO with OP\n+ * OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported\n+ * combinations. Each driver may only have a limited set of active rules -\n+ * returns ENOSPC if the caller's table is full.\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD 0x16d\n+#undef\tMC_CMD_0x16d_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36\n+/* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4\n+/* Any non-zero bits other than the ones named below or an unsupported\n+ * combination will cause the NIC to return EOPNOTSUPP. In the future more\n+ * flags may be added.\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1\n+/* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order.\n+ * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2\n+/* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order.\n+ * (Deprecated)\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12\n+/* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12\n+/* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the\n+ * case of IPv4, the IP should be in the first 4 bytes and all other bytes\n+ * should be zero.\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16\n+/* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1\n+/* Actions that should be applied to packets match the rule. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1\n+/* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2\n+/* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4\n+\n+/* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4\n+/* Handle to inserted rule. Used for removing the rule. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE\n+ * Remove a VNIC encapsulation rule. Packets which would have previously\n+ * matched the rule will then be considered as unencapsulated. Returns EALREADY\n+ * if the input HANDLE doesn't correspond to an existing rule.\n+ */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e\n+#undef\tMC_CMD_0x16e_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4\n+/* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4\n+\n+/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */\n+#define\tMC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0\n+\n+/* UUID structuredef: An RFC4122 standard UUID. The values here are stored in\n+ * the endianness specified by the RFC; users should ignore the broken-out\n+ * fields and instead do straight memory copies to ensure correct ordering.\n+ */\n+#define\tUUID_LEN 16\n+#define\tUUID_TIME_LOW_OFST 0\n+#define\tUUID_TIME_LOW_LEN 4\n+#define\tUUID_TIME_LOW_LBN 0\n+#define\tUUID_TIME_LOW_WIDTH 32\n+#define\tUUID_TIME_MID_OFST 4\n+#define\tUUID_TIME_MID_LEN 2\n+#define\tUUID_TIME_MID_LBN 32\n+#define\tUUID_TIME_MID_WIDTH 16\n+#define\tUUID_TIME_HI_LBN 52\n+#define\tUUID_TIME_HI_WIDTH 12\n+#define\tUUID_VERSION_LBN 48\n+#define\tUUID_VERSION_WIDTH 4\n+#define\tUUID_RESERVED_LBN 64\n+#define\tUUID_RESERVED_WIDTH 2\n+#define\tUUID_CLK_SEQ_LBN 66\n+#define\tUUID_CLK_SEQ_WIDTH 14\n+#define\tUUID_NODE_OFST 10\n+#define\tUUID_NODE_LEN 6\n+#define\tUUID_NODE_LBN 80\n+#define\tUUID_NODE_WIDTH 48\n+\n+/* MC_CMD_DEVEL_DUMP_VI_ENTRY structuredef */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_LEN 28\n+/* Type of entry */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_C2H 0x0 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_SW_H2C 0x1 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_C2H 0x2 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_HW_H2C 0x3 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_C2H 0x4 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_CR_H2C 0x5 /* enum */\n+/* enum: First QDMA writeback/completion queue. Used for ef100, C2H VDPA and\n+ * plain virtio.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_WRB 0x6\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QDMA_PFTCH 0x7 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_QTBL 0x100 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_C2H_QTBL 0x101 /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_DMAC_H2C_VIO 0x10a /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_LBN 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_TYPE_WIDTH 32\n+/* Internal QDMA/dmac queue number for this entry */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_OFST 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_LBN 32\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_QUEUE_NUMBER_WIDTH 32\n+/* Size of entry data */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_OFST 8\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_LBN 64\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_SIZE_WIDTH 32\n+/* Offset of entry data from start of MCDI message response payload */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_OFST 12\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_LBN 96\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_OFFSET_WIDTH 32\n+/* Absolute VI of the entry, or 0xffffffff if not available/applicable */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_OFST 16\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_NO_ABS_VI 0xffffffff /* enum */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_LBN 128\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_ABS_VI_WIDTH 32\n+/* Reserved */\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_OFST 20\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LEN 8\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LO_OFST 20\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_HI_OFST 24\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_LBN 160\n+#define\tMC_CMD_DEVEL_DUMP_VI_ENTRY_RESERVED_WIDTH 64\n+\n+\n+/***********************************/\n+/* MC_CMD_DEVEL_DUMP_VI\n+ * Dump various parts of the hardware's state for a VI.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI 0x1b5\n+#undef\tMC_CMD_0x1b5_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1b5_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_DEVEL_DUMP_VI_IN msgrequest */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_LEN 4\n+/* Absolute queue id of queue to dump state for */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_QID_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_QID_LEN 4\n+\n+/* MC_CMD_DEVEL_DUMP_VI_IN_V2 msgrequest */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_LEN 20\n+/* Which queue to dump. The meaning of this field dependes on ADDRESS_MODE. */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ID_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ID_LEN 4\n+/* Method of referring to the queue to dump */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_OFST 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ADDRESS_MODE_LEN 4\n+/* enum: First field refers to queue number as understood by QDMA/DMAC hardware\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_QUEUE_NUMBER 0x0\n+/* enum: First field refers to absolute VI number */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_ABS_VI 0x1\n+/* enum: First field refers to function-relative VI number on the command's\n+ * function\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI 0x2\n+/* enum: First field refers to function-relative VI number on a specified\n+ * function\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_REL_VI_PROXY 0x3\n+/* Type of VI. Not needed if ADDRESS_MODE is QUEUE_NUMBER. */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_OFST 8\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VI_TYPE_LEN 4\n+/* enum: Return only entries used for ef100 queues (a single hardware queue) */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_EF100 0x0\n+/* enum: Return entries used for virtio (Potentially two hardware queues,\n+ * depending on hardware implementation)\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VIRTIO 0x1\n+/* Only if ADDRESS_MODE is REL_VI_PROXY. Interface of function the queue is on.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_OFST 12\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PCIE_INTERFACE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               DEVEL_PCIE_INTERFACE */\n+/* Only if ADDRESS_MODE is REL_VI_PROXY. PF number of the function the queue is\n+ * on.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PF_OFST 16\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_PF_LEN 2\n+/* Only if ADDRESS_MODE is REL_VI_PROXY. VF number of the function the queue is\n+ * on.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_OFST 18\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_LEN 2\n+/* enum: The function is on a PF, not a VF. */\n+#define\tMC_CMD_DEVEL_DUMP_VI_IN_V2_VF_NULL 0xffff\n+\n+/* MC_CMD_DEVEL_DUMP_VI_OUT msgresponse */\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMIN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMAX 252\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LENMAX_MCDI2 1012\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_LEN(num) (0+1*(num))\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_NUM(len) (((len)-0)/1)\n+/* Number of dump entries returned */\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_NUM_ENTRIES_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_LBN 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_WIDTH 8\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MINNUM 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM 252\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_DATA_MAXNUM_MCDI2 1020\n+/* Array of MC_CMD_DEVEL_DUMP_VI_ENTRY structures of length NUM_ENTRIES */\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_OFST 4\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_LEN 28\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MINNUM 0\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM 8\n+#define\tMC_CMD_DEVEL_DUMP_VI_OUT_ENTRIES_MAXNUM_MCDI2 36\n+\n+/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structuredef */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_LEN 16\n+/* What register this is */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LEN 4\n+/* enum: Catchall for registers that aren't in this enum. Nothing should be in\n+ * this long-term\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_UNKNOWN 0xffffffff\n+/* enum: S2IC Converter Debug Packet Counter register. Informs number of\n+ * packets passed through Converter.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_H2C_S2IC_DBG_PKT_CNT 0x0\n+/* enum: IC2S Converter Debug Packet Counter register. Informs number of\n+ * packets passed through Converter.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_C2H_IC2S_DBG_PKT_CNT 0x1\n+/* enum: Event Controller Tx path Debug register. Count of Moderator Tx events,\n+ * not incl D2C, VirtIO, Dproxy.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DEBUG 0x2\n+/* enum: Event Controller Rx path Debug register. Count of Moderator Rx events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_DEBUG 0x3\n+/* enum: Event Controller Debug register. Count of Total EVC events. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TOTAL_DEBUG 0x4\n+/* enum: Same info as EVC_RX_DEBUG; collected at different location in design\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EF100_DEBUG 0x5\n+/* enum: Same info as EVC_TX_DEBUG; collected at different location in design\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_EF100_DEBUG 0x6\n+/* enum: Event Controller Debug register. Count of Tx VirtIO events. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTIO_DEBUG 0x7\n+/* enum: Event Controller Debug register. Count of Tx Descriptor Proxy events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_DPRXY_DEBUG 0x8\n+/* enum: Event Controller Debug register. Count of Tx VirtQ Descriptor Proxy\n+ * events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_DPRXY_DEBUG 0x9\n+/* enum: Event Controller Debug register. Count of Tx Descriptor-to-Completion\n+ * events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_D2C_DEBUG 0xa\n+/* enum: Event Controller Debug register. Count of Tx VirtIO Descriptor-to-\n+ * Completion events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_VIRTQ_D2C_DEBUG 0xb\n+/* enum: Event Controller Debug register. Count of Tx Timestamp events. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_TX_TSTAMP_DEBUG 0xc\n+/* enum: Event Controller Debug register. Count of Rx EvQ Timeout events. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_RX_EVQ_TIMEOUT_DEBUG 0xd\n+/* enum: Event Controller Debug register. Count of MC events. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_MC_DEBUG 0xe\n+/* enum: Event Controller Debug register. Count of EQDMA VirtIO Control events.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_EVC_EQDMA_VIO_CTL_DEBUG 0xf\n+/* enum: Counter of QDMA Dropped C2H packets. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_DMAC_C2H_DROP_CTR_REG 0x10\n+/* enum: Number of packets received by c host fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_IN_TBL 0x11\n+/* enum: Number of packets sent by c host fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_H_PACKETS_OUT_TBL 0x12\n+/* enum: Number of packets received by c plugin fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_P_PACKETS_IN_TBL 0x13\n+/* enum: Number of packets received by b host fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_H_PACKETS_IN_TBL 0x14\n+/* enum: Number of packets received by b net fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_N_PACKETS_IN_TBL 0x15\n+/* enum: Number of packets received by b host fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PH_PACKETS_IN_TBL 0x16\n+/* enum: Number of packets received by b net fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PN_PACKETS_IN_TBL 0x17\n+/* enum: Number of packets sent by b net fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_B_PACKETS_OUT_TBL 0x18\n+/* enum: Number of packets received by c net fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_IN_TBL 0x19\n+/* enum: Number of packets sent by c net fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_C_N_PACKETS_OUT_TBL 0x1a\n+/* enum: Number of packets received by ha fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_IN_TBL 0x1b\n+/* enum: Number of packets received by ha host shadow fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PH_PACKETS_IN_TBL 0x1c\n+/* enum: Number of packets received by ha fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_HA_PACKETS_OUT_TBL 0x1d\n+/* enum: Number of packets received by d hub fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_IN_TBL 0x1e\n+/* enum: Number of packets received by d hub plugin fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_P_PACKETS_IN_TBL 0x1f\n+/* enum: Number of packets received by d hub plugin fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_O_PACKETS_IN_TBL 0x20\n+/* enum: Number of packets sent to dmac. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_D_PACKETS_OUT_TBL 0x21\n+/* enum: Number of packets received by na fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_IN_TBL 0x22\n+/* enum: Number of packets dropped by na fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_DROPPED_TBL 0x23\n+/* enum: Number of packets sent by na fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_NA_PACKETS_OUT_TBL 0x24\n+/* enum: Number of packets received by rp hub fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_IN_TBL 0x25\n+/* enum: Number of packets removed from fifo. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_SSS_RP_PACKETS_OUT_TBL 0x26\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_LBN 0\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_REG_WIDTH 32\n+/* If REG is a table, the table row. */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_OFST 4\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_LBN 32\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ROW_WIDTH 32\n+/* Address of the register (as seen by the MC) */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_OFST 8\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_LBN 64\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_ADDRESS_WIDTH 32\n+/* Value of the register */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_OFST 12\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LEN 4\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_LBN 96\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY_VALUE_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_DEVEL_DUMP_RHEAD_REGS\n+ * Dump an assortment of hopefully useful riverhead debug registers\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS 0x1b6\n+#undef\tMC_CMD_0x1b6_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1b6_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_IN msgrequest */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_LEN 4\n+/* Which page of registers to retrieve. Page 0 always exists, later pages may\n+ * also exist if there are too many registers to fit in a single mcdi response.\n+ * NUM_PAGES in the response will tell you how many there are.\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_IN_PAGE_LEN 4\n+\n+/* MC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT msgresponse */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMIN 8\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX 248\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LENMAX_MCDI2 1016\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_LEN(num) (8+16*(num))\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_NUM(len) (((len)-8)/16)\n+/* Number of registers dumped in this response */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_OFST 0\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_REGS_LEN 4\n+/* How many pages of registers are available to extract */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_OFST 4\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_NUM_PAGES_LEN 4\n+/* Array of MC_CMD_DEVEL_DUMP_RHEAD_REGS_ENTRY structs, one for each register\n+ */\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_OFST 8\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_LEN 16\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MINNUM 0\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM 15\n+#define\tMC_CMD_DEVEL_DUMP_RHEAD_REGS_OUT_REGS_MAXNUM_MCDI2 63\n+\n+/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are\n+ * defined in SF-120734-TC with more information in SF-122717-TC.\n+ */\n+#define\tFUNCTION_PERSONALITY_LEN 4\n+#define\tFUNCTION_PERSONALITY_ID_OFST 0\n+#define\tFUNCTION_PERSONALITY_ID_LEN 4\n+/* enum: Function has no assigned personality */\n+#define\tFUNCTION_PERSONALITY_NULL 0x0\n+/* enum: Function has an EF100-style function control window and VI windows\n+ * with both EF100 and vDPA doorbells.\n+ */\n+#define\tFUNCTION_PERSONALITY_EF100 0x1\n+/* enum: Function has virtio net device configuration registers and doorbells\n+ * for virtio queue pairs.\n+ */\n+#define\tFUNCTION_PERSONALITY_VIRTIO_NET 0x2\n+/* enum: Function has virtio block device configuration registers and a\n+ * doorbell for a single virtqueue.\n+ */\n+#define\tFUNCTION_PERSONALITY_VIRTIO_BLK 0x3\n+/* enum: Function is a Xilinx acceleration device - management function */\n+#define\tFUNCTION_PERSONALITY_ACCEL_MGMT 0x4\n+/* enum: Function is a Xilinx acceleration device - user function */\n+#define\tFUNCTION_PERSONALITY_ACCEL_USR 0x5\n+#define\tFUNCTION_PERSONALITY_ID_LBN 0\n+#define\tFUNCTION_PERSONALITY_ID_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_VIRTIO_GET_FEATURES\n+ * Get a list of the virtio features supported by the device.\n+ */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES 0x168\n+#undef\tMC_CMD_0x168_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VIRTIO_GET_FEATURES_IN msgrequest */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4\n+/* Type of device to get features for. Matches the device id as defined by the\n+ * virtio spec.\n+ */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4\n+/* enum: Reserved. Do not use. */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0\n+/* enum: Net device. */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1\n+/* enum: Block device. */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2\n+\n+/* MC_CMD_VIRTIO_GET_FEATURES_OUT msgresponse */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_LEN 8\n+/* Features supported by the device. The result is a bitfield in the format of\n+ * the feature bits of the specified device type as defined in the virtIO 1.1\n+ * specification ( https://docs.oasis-\n+ * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )\n+ */\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4\n+\n+\n+/***********************************/\n+/* MC_CMD_VIRTIO_TEST_FEATURES\n+ * Query whether a given set of features is supported. Fails with ENOSUP if the\n+ * driver requests a feature the device doesn't support. Fails with EINVAL if\n+ * the driver fails to request a feature which the device requires.\n+ */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES 0x169\n+#undef\tMC_CMD_0x169_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VIRTIO_TEST_FEATURES_IN msgrequest */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_LEN 16\n+/* Type of device to test features for. Matches the device id as defined by the\n+ * virtio spec.\n+ */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4\n+/* Features requested. Same format as the returned value from\n+ * MC_CMD_VIRTIO_GET_FEATURES.\n+ */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12\n+\n+/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */\n+#define\tMC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VIRTIO_INIT_QUEUE\n+ * Create a virtio virtqueue. Fails with EALREADY if the queue already exists.\n+ * Fails with ENOSUP if a feature is requested that isn't supported. Fails with\n+ * EINVAL if a required feature isn't requested, or any other parameter is\n+ * invalid.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE 0x16a\n+#undef\tMC_CMD_0x16a_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VIRTIO_INIT_QUEUE_REQ msgrequest */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_LEN 68\n+/* Type of virtqueue to create. A network rxq and a txq can exist at the same\n+ * time on a single VI.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1\n+/* enum: A network device receive queue */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0\n+/* enum: A network device transmit queue */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1\n+/* enum: A block device request queue */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1\n+/* If the calling function is a PF and this field is not VF_NULL, create the\n+ * queue on the specified child VF instead of on the PF.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_OFST 2\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_LEN 2\n+/* enum: No VF, create queue on the PF. */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff\n+/* Desired instance. This is the function-local index of the associated VI, not\n+ * the virtqueue number as counted by the virtqueue spec.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4\n+/* Queue size, in entries. Must be a power of two. */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_OFST 8\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4\n+/* Flags */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_OFST 12\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_OFST 12\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1\n+/* Address of the descriptor table in the virtqueue. */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20\n+/* Address of the available ring in the virtqueue. */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28\n+/* Address of the used ring in the virtqueue. */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36\n+/* PASID to use on PCIe transactions involving this queue. Ignored if the\n+ * USE_PASID flag is not set.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_OFST 40\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4\n+/* Which MSIX vector to use for this virtqueue, or NO_VECTOR if MSIX should not\n+ * be used.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_OFST 44\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_LEN 2\n+/* enum: Do not enable interrupts for this virtqueue */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_OFST 46\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_LEN 2\n+/* Virtio features to apply to this queue. Same format as the in the virtio\n+ * spec and in the return from MC_CMD_VIRTIO_GET_FEATURES. Must be a subset of\n+ * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-\n+ * queue because with vDPA multiple queues on the same function can be passed\n+ * through to different virtual hosts as independent devices.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */\n+/* The initial producer index for this queue's used ring. If this queue is\n+ * being created to be migrated into, this should be the FINAL_PIDX value\n+ * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from.\n+ * Otherwise, it should be zero.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_OFST 56\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4\n+/* The initial consumer index for this queue's available ring. If this queue is\n+ * being created to be migrated into, this should be the FINAL_CIDX value\n+ * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from.\n+ * Otherwise, it should be zero.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_OFST 60\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4\n+/* A MAE_MPORT_SELECTOR defining which mport this queue should be associated\n+ * with. Use MAE_MPORT_SELECTOR_ASSIGNED to request the default mport for the\n+ * function this queue is being created on.\n+ */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_OFST 64\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4\n+\n+/* MC_CMD_VIRTIO_INIT_QUEUE_RESP msgresponse */\n+#define\tMC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_VIRTIO_FINI_QUEUE\n+ * Destroy a virtio virtqueue\n+ */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE 0x16b\n+#undef\tMC_CMD_0x16b_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VIRTIO_FINI_QUEUE_REQ msgrequest */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_LEN 8\n+/* Type of virtqueue to destroy. */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_VIRTIO_INIT_QUEUE/MC_CMD_VIRTIO_INIT_QUEUE_REQ/QUEUE_TYPE */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1\n+/* If the calling function is a PF and this field is not VF_NULL, destroy the\n+ * queue on the specified child VF instead of on the PF.\n+ */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_OFST 2\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_LEN 2\n+/* enum: No VF, destroy the queue on the PF. */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff\n+/* Instance to destroy */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4\n+\n+/* MC_CMD_VIRTIO_FINI_QUEUE_RESP msgresponse */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_RESP_LEN 8\n+/* The producer index of the used ring when the queue was stopped. */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4\n+/* The consumer index of the available ring when the queue was stopped. */\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4\n+#define\tMC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET\n+ * Get the offset in the BAR of the doorbells for a VI. Doesn't require the\n+ * queue(s) to be allocated.\n+ */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c\n+#undef\tMC_CMD_0x16c_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL\n+\n+/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ msgrequest */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_LEN 8\n+/* Type of device to get information for. Matches the device id as defined by\n+ * the virtio spec.\n+ */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1\n+/* If the calling function is a PF and this field is not VF_NULL, query the VI\n+ * on the specified child VF instead of on the PF.\n+ */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_OFST 2\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_LEN 2\n+/* enum: No VF, query the PF. */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff\n+/* VI instance to query */\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4\n+#define\tMC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4\n+\n+/* MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP msgresponse */\n+#define\tMC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_LEN 8\n+/* Offset of RX doorbell in BAR */\n+#define\tMC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4\n+/* Offset of TX doorbell in BAR */\n+#define\tMC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4\n+#define\tMC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4\n+\n+/* MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP msgresponse */\n+#define\tMC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4\n+/* Offset of request doorbell in BAR */\n+#define\tMC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0\n+#define\tMC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4\n+\n+/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID\n+ * (interface/PF/VF tuple)\n+ */\n+#define\tPCIE_FUNCTION_LEN 8\n+/* PCIe PF function number */\n+#define\tPCIE_FUNCTION_PF_OFST 0\n+#define\tPCIE_FUNCTION_PF_LEN 2\n+/* enum: Wildcard value representing any available function (e.g in resource\n+ * allocation requests)\n+ */\n+#define\tPCIE_FUNCTION_PF_ANY 0xfffe\n+/* enum: Value representing invalid (null) function */\n+#define\tPCIE_FUNCTION_PF_NULL 0xffff\n+#define\tPCIE_FUNCTION_PF_LBN 0\n+#define\tPCIE_FUNCTION_PF_WIDTH 16\n+/* PCIe VF Function number (PF relative) */\n+#define\tPCIE_FUNCTION_VF_OFST 2\n+#define\tPCIE_FUNCTION_VF_LEN 2\n+/* enum: Wildcard value representing any available function (e.g in resource\n+ * allocation requests)\n+ */\n+#define\tPCIE_FUNCTION_VF_ANY 0xfffe\n+/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==\n+ * PF_NULL)\n+ */\n+#define\tPCIE_FUNCTION_VF_NULL 0xffff\n+#define\tPCIE_FUNCTION_VF_LBN 16\n+#define\tPCIE_FUNCTION_VF_WIDTH 16\n+/* PCIe interface of the function */\n+#define\tPCIE_FUNCTION_INTF_OFST 4\n+#define\tPCIE_FUNCTION_INTF_LEN 4\n+/* enum: Host PCIe interface */\n+#define\tPCIE_FUNCTION_INTF_HOST 0x0\n+/* enum: Application Processor interface */\n+#define\tPCIE_FUNCTION_INTF_AP 0x1\n+#define\tPCIE_FUNCTION_INTF_LBN 32\n+#define\tPCIE_FUNCTION_INTF_WIDTH 32\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_CREATE\n+ * Descriptor proxy functions are abstract devices that forward all request\n+ * submitted to the host PCIe function (descriptors submitted to Virtio or\n+ * EF100 queues) to be handled on another function (most commonly on the\n+ * embedded Application Processor), via EF100 descriptor proxy, memory-to-\n+ * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk\n+ * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy\n+ * function on the host and assigns a user-defined label. The actual function\n+ * configuration is not persisted until the caller configures it with\n+ * MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN and commits with\n+ * MC_CMD_DESC_PROXY_FUNC_COMMIT_IN.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE 0x172\n+#undef\tMC_CMD_0x172_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x172_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CREATE_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_LEN 52\n+/* PCIe Function ID to allocate (as struct PCIE_FUNCTION). Set to\n+ * {PF_ANY,VF_ANY,interface} for \"any available function\" Set to\n+ * {PF_ANY,VF_NULL,interface} for \"any available PF\"\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LEN 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4\n+/* The personality to set. The meanings of the personalities are defined in\n+ * SF-120734-TC with more information in SF-122717-TC. At present, we only\n+ * support proxying for VIRTIO_BLK\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_OFST 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4\n+/*            Enum values, see field(s): */\n+/*               FUNCTION_PERSONALITY/ID */\n+/* User-defined label (zero-terminated ASCII string) to uniquely identify the\n+ * function\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_OFST 12\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_IN_LABEL_LEN 40\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CREATE_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_LEN 12\n+/* Handle to the descriptor proxy function */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4\n+/* Allocated function ID (as struct PCIE_FUNCTION) */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LEN 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_OFST 8\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_DESTROY\n+ * Remove an existing descriptor proxy function. Underlying function\n+ * personality and configuration reverts back to factory default. Function\n+ * configuration is committed immediately to specified store and any function\n+ * ownership is released.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY 0x173\n+#undef\tMC_CMD_0x173_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x173_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_DESTROY_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LEN 44\n+/* User-defined label (zero-terminated ASCII string) to uniquely identify the\n+ * function\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_LEN 40\n+/* Store from which to remove function configuration */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_OFST 40\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4\n+/*            Enum values, see field(s): */\n+/*               MC_CMD_DESC_PROXY_FUNC_COMMIT/MC_CMD_DESC_PROXY_FUNC_COMMIT_IN/STORE */\n+\n+/* MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0\n+\n+/* VIRTIO_BLK_CONFIG structuredef: Virtio block device configuration. See\n+ * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature\n+ * bits. See Virtio specification v1.1, Section 5.2.4 (struct\n+ * virtio_blk_config) for definition of remaining configuration fields\n+ */\n+#define\tVIRTIO_BLK_CONFIG_LEN 68\n+/* Virtio block device features to advertise, per Virtio 1.1, 5.2.3 and 6 */\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LEN 8\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_LBN 2\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_LBN 5\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_LBN 6\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_LBN 7\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_LBN 9\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_LBN 10\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_LBN 11\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_LBN 12\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_LBN 13\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_LBN 14\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_LBN 28\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_LBN 29\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_LBN 32\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_LBN 33\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_LBN 34\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_LBN 35\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_LBN 36\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_LBN 37\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_LBN 38\n+#define\tVIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_LBN 0\n+#define\tVIRTIO_BLK_CONFIG_FEATURES_WIDTH 64\n+/* The capacity of the device (expressed in 512-byte sectors) */\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_OFST 8\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LEN 8\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LO_OFST 8\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_HI_OFST 12\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_LBN 64\n+#define\tVIRTIO_BLK_CONFIG_CAPACITY_WIDTH 64\n+/* Maximum size of any single segment. Only valid when VIRTIO_BLK_F_SIZE_MAX is\n+ * set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_SIZE_MAX_OFST 16\n+#define\tVIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_SIZE_MAX_LBN 128\n+#define\tVIRTIO_BLK_CONFIG_SIZE_MAX_WIDTH 32\n+/* Maximum number of segments in a request. Only valid when\n+ * VIRTIO_BLK_F_SEG_MAX is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_SEG_MAX_OFST 20\n+#define\tVIRTIO_BLK_CONFIG_SEG_MAX_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_SEG_MAX_LBN 160\n+#define\tVIRTIO_BLK_CONFIG_SEG_MAX_WIDTH 32\n+/* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is\n+ * set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_CYLINDERS_OFST 24\n+#define\tVIRTIO_BLK_CONFIG_CYLINDERS_LEN 2\n+#define\tVIRTIO_BLK_CONFIG_CYLINDERS_LBN 192\n+#define\tVIRTIO_BLK_CONFIG_CYLINDERS_WIDTH 16\n+/* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_HEADS_OFST 26\n+#define\tVIRTIO_BLK_CONFIG_HEADS_LEN 1\n+#define\tVIRTIO_BLK_CONFIG_HEADS_LBN 208\n+#define\tVIRTIO_BLK_CONFIG_HEADS_WIDTH 8\n+/* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_SECTORS_OFST 27\n+#define\tVIRTIO_BLK_CONFIG_SECTORS_LEN 1\n+#define\tVIRTIO_BLK_CONFIG_SECTORS_LBN 216\n+#define\tVIRTIO_BLK_CONFIG_SECTORS_WIDTH 8\n+/* Block size of disk. Only valid when VIRTIO_BLK_F_BLK_SIZE is set. */\n+#define\tVIRTIO_BLK_CONFIG_BLK_SIZE_OFST 28\n+#define\tVIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_BLK_SIZE_LBN 224\n+#define\tVIRTIO_BLK_CONFIG_BLK_SIZE_WIDTH 32\n+/* Block topology - number of logical blocks per physical block (log2). Only\n+ * valid when VIRTIO_BLK_F_TOPOLOGY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_OFST 32\n+#define\tVIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1\n+#define\tVIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LBN 256\n+#define\tVIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_WIDTH 8\n+/* Block topology - offset of first aligned logical block. Only valid when\n+ * VIRTIO_BLK_F_TOPOLOGY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_OFST 33\n+#define\tVIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1\n+#define\tVIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LBN 264\n+#define\tVIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_WIDTH 8\n+/* Block topology - suggested minimum I/O size in blocks. Only valid when\n+ * VIRTIO_BLK_F_TOPOLOGY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_MIN_IO_SIZE_OFST 34\n+#define\tVIRTIO_BLK_CONFIG_MIN_IO_SIZE_LEN 2\n+#define\tVIRTIO_BLK_CONFIG_MIN_IO_SIZE_LBN 272\n+#define\tVIRTIO_BLK_CONFIG_MIN_IO_SIZE_WIDTH 16\n+/* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid\n+ * when VIRTIO_BLK_F_TOPOLOGY is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_OPT_IO_SIZE_OFST 36\n+#define\tVIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_OPT_IO_SIZE_LBN 288\n+#define\tVIRTIO_BLK_CONFIG_OPT_IO_SIZE_WIDTH 32\n+/* Unused, set to zero. Note that virtio_blk_config.writeback is volatile and\n+ * not carried in config data.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_UNUSED0_OFST 40\n+#define\tVIRTIO_BLK_CONFIG_UNUSED0_LEN 2\n+#define\tVIRTIO_BLK_CONFIG_UNUSED0_LBN 320\n+#define\tVIRTIO_BLK_CONFIG_UNUSED0_WIDTH 16\n+/* Number of queues. Only valid if the VIRTIO_BLK_F_MQ feature is negotiated.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_NUM_QUEUES_OFST 42\n+#define\tVIRTIO_BLK_CONFIG_NUM_QUEUES_LEN 2\n+#define\tVIRTIO_BLK_CONFIG_NUM_QUEUES_LBN 336\n+#define\tVIRTIO_BLK_CONFIG_NUM_QUEUES_WIDTH 16\n+/* Maximum discard sectors size, in 512-byte units. Only valid if\n+ * VIRTIO_BLK_F_DISCARD is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_OFST 44\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LBN 352\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_WIDTH 32\n+/* Maximum discard segment number. Only valid if VIRTIO_BLK_F_DISCARD is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_OFST 48\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LBN 384\n+#define\tVIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_WIDTH 32\n+/* Discard sector alignment, in 512-byte units. Only valid if\n+ * VIRTIO_BLK_F_DISCARD is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_OFST 52\n+#define\tVIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LBN 416\n+#define\tVIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_WIDTH 32\n+/* Maximum write zeroes sectors size, in 512-byte units. Only valid if\n+ * VIRTIO_BLK_F_WRITE_ZEROES is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_OFST 56\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LBN 448\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_WIDTH 32\n+/* Maximum write zeroes segment number. Only valid if VIRTIO_BLK_F_WRITE_ZEROES\n+ * is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_OFST 60\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LBN 480\n+#define\tVIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_WIDTH 32\n+/* Write zeroes request can result in deallocating one or more sectors. Only\n+ * valid if VIRTIO_BLK_F_WRITE_ZEROES is set.\n+ */\n+#define\tVIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_OFST 64\n+#define\tVIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1\n+#define\tVIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LBN 512\n+#define\tVIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_WIDTH 8\n+/* Unused, set to zero. */\n+#define\tVIRTIO_BLK_CONFIG_UNUSED1_OFST 65\n+#define\tVIRTIO_BLK_CONFIG_UNUSED1_LEN 3\n+#define\tVIRTIO_BLK_CONFIG_UNUSED1_LBN 520\n+#define\tVIRTIO_BLK_CONFIG_UNUSED1_WIDTH 24\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET\n+ * Set configuration for an existing descriptor proxy function. Configuration\n+ * data must match function personality. The actual function configuration is\n+ * not persisted until the caller commits with MC_CMD_DESC_PROXY_FUNC_COMMIT_IN\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174\n+#undef\tMC_CMD_0x174_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x174_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMIN 20\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX 252\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LENMAX_MCDI2 1020\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num))\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)\n+/* Handle to descriptor proxy function (as returned by\n+ * MC_CMD_DESC_PROXY_FUNC_OPEN)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4\n+/* Reserved for future extension, set to zero. */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_LEN 16\n+/* Configuration data. Format of configuration data is determined implicitly\n+ * from function personality referred to by HANDLE. Currently, only supported\n+ * format is VIRTIO_BLK_CONFIG.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_OFST 20\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM 232\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MAXNUM_MCDI2 1000\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_COMMIT\n+ * Commit function configuration to non-volatile or volatile store. Once\n+ * configuration is applied to hardware (which may happen immediately or on\n+ * next function/device reset) a DESC_PROXY_FUNC_CONFIG_SET MCDI event will be\n+ * delivered to callers MCDI event queue.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT 0x175\n+#undef\tMC_CMD_0x175_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x175_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_COMMIT_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_LEN 8\n+/* Handle to descriptor proxy function (as returned by\n+ * MC_CMD_DESC_PROXY_FUNC_OPEN)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4\n+/* enum: Store into non-volatile (dynamic) config */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0\n+/* enum: Store into volatile (ephemeral) config */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1\n+\n+/* MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4\n+/* Generation count to be delivered in an event once configuration becomes live\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_OPEN\n+ * Retrieve a handle for an existing descriptor proxy function. Returns an\n+ * integer handle, valid until function is deallocated, MC rebooted or power-\n+ * cycle. Returns ENODEV if no function with given label exists.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN 0x176\n+#undef\tMC_CMD_0x176_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x176_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_OPEN_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_IN_LEN 40\n+/* User-defined label (zero-terminated ASCII string) to uniquely identify the\n+ * function\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_LEN 40\n+\n+/* MC_CMD_DESC_PROXY_FUNC_OPEN_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMIN 40\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX 252\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LENMAX_MCDI2 1020\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num))\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)\n+/* Handle to the descriptor proxy function */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4\n+/* PCIe Function ID (as struct PCIE_FUNCTION) */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LEN 8\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_OFST 8\n+/* Function personality */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_OFST 12\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4\n+/*            Enum values, see field(s): */\n+/*               FUNCTION_PERSONALITY/ID */\n+/* Function configuration state */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_OFST 16\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4\n+/* enum: Function configuration is visible to the host (live) */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0\n+/* enum: Function configuration is pending reset */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1\n+/* enum: Function configuration is missing (created, but no configuration\n+ * committed)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_UNCONFIGURED 0x2\n+/* Generation count to be delivered in an event once the configuration becomes\n+ * live (if status is \"pending\")\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_OFST 20\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4\n+/* Reserved for future extension, set to zero. */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_OFST 24\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_RESERVED_LEN 16\n+/* Configuration data corresponding to function personality. Currently, only\n+ * supported format is VIRTIO_BLK_CONFIG. Not valid if status is UNCONFIGURED.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_OFST 40\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM 212\n+#define\tMC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MAXNUM_MCDI2 980\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_CLOSE\n+ * Releases a handle for an open descriptor proxy function. If proxying was\n+ * enabled on the device, the caller is expected to gracefully stop it using\n+ * MC_CMD_DESC_PROXY_FUNC_DISABLE prior to calling this function. Closing an\n+ * active device without disabling proxying will result in forced close, which\n+ * will put the device into a failed state and signal the host driver of the\n+ * error (for virtio, DEVICE_NEEDS_RESET flag would be set on the host side)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1\n+#undef\tMC_CMD_0x1a1_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1a1_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CLOSE_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4\n+/* Handle to the descriptor proxy function */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4\n+\n+/* MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0\n+\n+/* DESC_PROXY_FUNC_MAP structuredef */\n+#define\tDESC_PROXY_FUNC_MAP_LEN 52\n+/* PCIe function ID (as struct PCIE_FUNCTION) */\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_OFST 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LEN 8\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_LBN 0\n+#define\tDESC_PROXY_FUNC_MAP_FUNC_WIDTH 64\n+/* Function personality */\n+#define\tDESC_PROXY_FUNC_MAP_PERSONALITY_OFST 8\n+#define\tDESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4\n+/*            Enum values, see field(s): */\n+/*               FUNCTION_PERSONALITY/ID */\n+#define\tDESC_PROXY_FUNC_MAP_PERSONALITY_LBN 64\n+#define\tDESC_PROXY_FUNC_MAP_PERSONALITY_WIDTH 32\n+/* User-defined label (zero-terminated ASCII string) to uniquely identify the\n+ * function\n+ */\n+#define\tDESC_PROXY_FUNC_MAP_LABEL_OFST 12\n+#define\tDESC_PROXY_FUNC_MAP_LABEL_LEN 40\n+#define\tDESC_PROXY_FUNC_MAP_LABEL_LBN 96\n+#define\tDESC_PROXY_FUNC_MAP_LABEL_WIDTH 320\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_ENUM\n+ * Enumerate existing descriptor proxy functions\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM 0x177\n+#undef\tMC_CMD_0x177_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x177_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_ENUM_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4\n+/* Starting index, set to 0 on first request. See\n+ * MC_CMD_DESC_PROXY_FUNC_ENUM_OUT/FLAGS.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4\n+\n+/* MC_CMD_DESC_PROXY_FUNC_ENUM_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX 212\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMAX_MCDI2 992\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1\n+/* Function map, as array of DESC_PROXY_FUNC_MAP */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_LEN 52\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM_MCDI2 19\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_ENABLE\n+ * Enable descriptor proxying for function into target event queue. Returns VI\n+ * allocation info for the proxy source function, so that the caller can map\n+ * absolute VI IDs from descriptor proxy events back to the originating\n+ * function.\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE 0x178\n+#undef\tMC_CMD_0x178_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x178_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_ENABLE_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_IN_LEN 8\n+/* Handle to descriptor proxy function (as returned by\n+ * MC_CMD_DESC_PROXY_FUNC_OPEN)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4\n+/* Descriptor proxy sink queue (caller function relative). Must be extended\n+ * width event queue\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4\n+\n+/* MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_LEN 8\n+/* The number of VIs allocated on the function */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4\n+/* The base absolute VI number allocated to the function. */\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4\n+#define\tMC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4\n+\n+\n+/***********************************/\n+/* MC_CMD_DESC_PROXY_FUNC_DISABLE\n+ * Disable descriptor proxying for function\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE 0x179\n+#undef\tMC_CMD_0x179_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x179_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_DESC_PROXY_FUNC_DISABLE_IN msgrequest */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4\n+/* Handle to descriptor proxy function (as returned by\n+ * MC_CMD_DESC_PROXY_FUNC_OPEN)\n+ */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4\n+\n+/* MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT msgresponse */\n+#define\tMC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0\n+\n+\n+/***********************************/\n+/* MC_CMD_GET_ADDR_SPC_ID\n+ * Get Address space identifier for use in mem2mem descriptors for a given\n+ * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem\n+ * descriptors.\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID 0x1a0\n+#undef\tMC_CMD_0x1a0_PRIVILEGE_CTG\n+\n+#define\tMC_CMD_0x1a0_PRIVILEGE_CTG SRIOV_CTG_ADMIN\n+\n+/* MC_CMD_GET_ADDR_SPC_ID_IN msgrequest */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_LEN 16\n+/* Resource type to get ADDR_SPC_ID for */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4\n+/* enum: Address space ID for host/AP memory DMA over the same interface this\n+ * MCDI was called on\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0\n+/* enum: Address space ID for host/AP memory DMA via PCI interface and function\n+ * specified by FUNC\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1\n+/* enum: Address space ID for host/AP memory DMA via PCI interface and function\n+ * specified by FUNC with PASID value specified by PASID\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2\n+/* enum: Address space ID for host/AP memory DMA via PCI interface and function\n+ * specified by FUNC with PASID value of relative VI specified by VI\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3\n+/* enum: Address space ID for host/AP memory DMA via PCI interface, function\n+ * and PASID value of absolute VI specified by VI\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4\n+/* enum: Address space ID for host memory DMA via PCI interface and function of\n+ * descriptor proxy function specified by HANDLE\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5\n+/* enum: Address space ID for DMA to/from MC memory */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6\n+/* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7\n+/* PCIe Function ID (as struct PCIE_FUNCTION). Only valid if TYPE is PCI_FUNC,\n+ * PCI_FUNC_PASID or REL_VI.\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LEN 8\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_OFST 8\n+/* PASID value. Only valid if TYPE is PCI_FUNC_PASID. */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_PASID_OFST 12\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4\n+/* Relative or absolute VI number. Only valid if TYPE is REL_VI or ABS_VI */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_VI_OFST 12\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4\n+/* Descriptor proxy function handle. Only valid if TYPE is DESC_PROXY_HANDLE.\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4\n+#define\tMC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4\n+\n+/* MC_CMD_GET_ADDR_SPC_ID_OUT msgresponse */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_LEN 8\n+/* Address Space ID for the requested target. Only the lower 36 bits are valid\n+ * in the current SmartNIC implementation.\n+ */\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LEN 8\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0\n+#define\tMC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4\n+\n+/* MAE_MPORT_SELECTOR structuredef: MPORTS are identified by an opaque unsigned\n+ * integer value (mport_id) that is guaranteed to be representable within\n+ * 32-bits or within any NIC interface field that needs store the value\n+ * (whichever is narrowers). This selector structure provides a stable way to\n+ * refer to m-ports.\n+ */\n+#define\tMAE_MPORT_SELECTOR_LEN 4\n+/* Used to force the tools to output bitfield-style defines for this structure.\n+ */\n+#define\tMAE_MPORT_SELECTOR_FLAT_OFST 0\n+#define\tMAE_MPORT_SELECTOR_FLAT_LEN 4\n+/* enum: An m-port selector value that is guaranteed never to represent a real\n+ * mport\n+ */\n+#define\tMAE_MPORT_SELECTOR_NULL 0x0\n+/* enum: The m-port assigned to the calling client. */\n+#define\tMAE_MPORT_SELECTOR_ASSIGNED 0x1000000\n+#define\tMAE_MPORT_SELECTOR_TYPE_OFST 0\n+#define\tMAE_MPORT_SELECTOR_TYPE_LBN 24\n+#define\tMAE_MPORT_SELECTOR_TYPE_WIDTH 8\n+/* enum: The MPORT connected to a given physical port */\n+#define\tMAE_MPORT_SELECTOR_TYPE_PPORT 0x2\n+/* enum: The MPORT assigned to a given PCIe function */\n+#define\tMAE_MPORT_SELECTOR_TYPE_FUNC 0x3\n+/* enum: An mport_id */\n+#define\tMAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4\n+#define\tMAE_MPORT_SELECTOR_MPORT_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_MPORT_ID_LBN 0\n+#define\tMAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24\n+#define\tMAE_MPORT_SELECTOR_PPORT_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_PPORT_ID_LBN 0\n+#define\tMAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4\n+#define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16\n+#define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8\n+#define\tMAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0\n+#define\tMAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0\n+#define\tMAE_MPORT_SELECTOR_FUNC_VF_ID_WIDTH 16\n+/* enum: Used for VF_ID to indicate a physical function. */\n+#define\tMAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff\n+/* enum: Used for PF_ID to indicate the physical function of the calling\n+ * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector\n+ * relates to the calling function. (For clarity, it is recommended that\n+ * clients use ASSIGNED to achieve this behaviour). - When used by a PF with\n+ * VF_ID != VF_ID_NULL, the mport selector relates to a VF child of the calling\n+ * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector\n+ * relates to the PF owning the calling function. - When used by a VF with\n+ * VF_ID != VF_ID_NULL, the mport selector relates to a sibling VF of the\n+ * calling function. - Not meaningful used by a client that is not a PCIe\n+ * function.\n+ */\n+#define\tMAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff\n+#define\tMAE_MPORT_SELECTOR_FLAT_LBN 0\n+#define\tMAE_MPORT_SELECTOR_FLAT_WIDTH 32\n+\n #endif /* _SIENA_MC_DRIVER_PCOL_H */\ndiff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\nindex f15c7b2064..aa03e8015a 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_aoe.h\n@@ -7,7 +7,7 @@\n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n  * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n- * rebuild this file with \"make -C doc mcdiheaders\".\n+ * rebuild this file with \"make mcdi_headers_v5\".\n  */\n \n #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H\n@@ -25,6 +25,7 @@\n #define\tMC_CMD_FC_IN_LEN 4\n #define\tMC_CMD_FC_IN_OP_HDR_OFST 0\n #define\tMC_CMD_FC_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_FC_IN_OP_OFST 0\n #define\tMC_CMD_FC_IN_OP_LBN 0\n #define\tMC_CMD_FC_IN_OP_WIDTH 8\n /* enum: NULL MCDI command to FC. */\n@@ -152,6 +153,7 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_MAC_HEADER_OFST 4\n #define\tMC_CMD_FC_IN_MAC_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_OP_OFST 4\n #define\tMC_CMD_FC_IN_MAC_OP_LBN 0\n #define\tMC_CMD_FC_IN_MAC_OP_WIDTH 8\n /* enum: MAC reconfigure handler */\n@@ -166,14 +168,17 @@\n #define\tMC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7\n /* enum: MAC Read status */\n #define\tMC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8\n+#define\tMC_CMD_FC_IN_MAC_PORT_TYPE_OFST 4\n #define\tMC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8\n #define\tMC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8\n /* enum: External FPGA port. */\n #define\tMC_CMD_FC_PORT_EXT 0x0\n /* enum: Internal Siena-facing FPGA ports. */\n #define\tMC_CMD_FC_PORT_INT 0x1\n+#define\tMC_CMD_FC_IN_MAC_PORT_IDX_OFST 4\n #define\tMC_CMD_FC_IN_MAC_PORT_IDX_LBN 16\n #define\tMC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_OFST 4\n #define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24\n #define\tMC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8\n /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n@@ -210,8 +215,10 @@\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_OFST 24\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1\n #define\tMC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28\n@@ -249,10 +256,13 @@\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_OFST 12\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_OFST 12\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_OFST 12\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2\n #define\tMC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1\n /* Number of statistics to read */\n@@ -370,6 +380,7 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4\n #define\tMC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_OP_OFST 4\n #define\tMC_CMD_FC_IN_DDR_TEST_OP_LBN 0\n #define\tMC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8\n /* enum: DRAM Test Start */\n@@ -385,12 +396,16 @@\n /*            MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */\n #define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8\n #define\tMC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T0_OFST 8\n #define\tMC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0\n #define\tMC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_T1_OFST 8\n #define\tMC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1\n #define\tMC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B0_OFST 8\n #define\tMC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2\n #define\tMC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1\n+#define\tMC_CMD_FC_IN_DDR_TEST_START_B1_OFST 8\n #define\tMC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3\n #define\tMC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1\n \n@@ -433,6 +448,7 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_READ_MAP_HEADER_OFST 4\n #define\tMC_CMD_FC_IN_READ_MAP_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_READ_MAP_OP_OFST 4\n #define\tMC_CMD_FC_IN_READ_MAP_OP_LBN 0\n #define\tMC_CMD_FC_IN_READ_MAP_OP_WIDTH 8\n /* enum: Get the number of map regions */\n@@ -467,16 +483,22 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_OFST 4\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5\n #define\tMC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1\n \n@@ -486,6 +508,7 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_IO_REL_HEADER_OFST 4\n #define\tMC_CMD_FC_IN_IO_REL_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_IO_REL_OP_OFST 4\n #define\tMC_CMD_FC_IN_IO_REL_OP_LBN 0\n #define\tMC_CMD_FC_IN_IO_REL_OP_WIDTH 8\n /* enum: Get the base address that the FC applies to relative commands */\n@@ -494,6 +517,7 @@\n #define\tMC_CMD_FC_IN_IO_REL_READ32 0x2\n /* enum: Write data */\n #define\tMC_CMD_FC_IN_IO_REL_WRITE32 0x3\n+#define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_OFST 4\n #define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8\n #define\tMC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8\n /* enum: Application address space */\n@@ -547,6 +571,7 @@\n /*            MC_CMD_FC_IN_CMD_LEN 4 */\n #define\tMC_CMD_FC_IN_UHLINK_HEADER_OFST 4\n #define\tMC_CMD_FC_IN_UHLINK_HEADER_LEN 4\n+#define\tMC_CMD_FC_IN_UHLINK_OP_OFST 4\n #define\tMC_CMD_FC_IN_UHLINK_OP_LBN 0\n #define\tMC_CMD_FC_IN_UHLINK_OP_WIDTH 8\n /* enum: Get PHY configuration info */\n@@ -565,10 +590,13 @@\n #define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7\n /* enum: Get loopback mode config state on fpga port */\n #define\tMC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_OFST 4\n #define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8\n #define\tMC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_OFST 4\n #define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16\n #define\tMC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8\n+#define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_OFST 4\n #define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24\n #define\tMC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8\n /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are\n@@ -668,10 +696,13 @@\n #define\tMC_CMD_FC_IN_SET_LINK_SPEED_LEN 4\n #define\tMC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12\n #define\tMC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_OFST 12\n #define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0\n #define\tMC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_OFST 12\n #define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1\n #define\tMC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1\n+#define\tMC_CMD_FC_IN_SET_LINK_TXDIS_OFST 12\n #define\tMC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2\n #define\tMC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1\n \n@@ -773,12 +804,16 @@\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_OFST 44\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_OFST 44\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_OFST 44\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1\n+#define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_OFST 44\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2\n #define\tMC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */\n@@ -1396,6 +1431,7 @@\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8\n /* enum: Test not yet initiated */\n@@ -1406,31 +1442,43 @@\n #define\tMC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2\n /* enum: Test did not complete in specified time */\n #define\tMC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1\n /* Test result from FPGA */\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5\n+#define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_OFST 4\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5\n #define\tMC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */\n@@ -1447,6 +1495,7 @@\n /* Assertion status flag. */\n #define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0\n #define\tMC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_OFST 0\n #define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8\n #define\tMC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8\n /* enum: No crash data available */\n@@ -1455,6 +1504,7 @@\n #define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1\n /* enum: Crash data has been sent */\n #define\tMC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2\n+#define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_OFST 0\n #define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0\n #define\tMC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8\n /* enum: No crash has been recorded. */\n@@ -1484,16 +1534,22 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_LEN 32\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4\n /* Build timestamp (seconds since epoch) */\n@@ -1501,58 +1557,80 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8\n #define\tMC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */\n #define\tMC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1\n #define\tMC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */\n #define\tMC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16\n@@ -1563,6 +1641,7 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16\n \n@@ -1570,16 +1649,22 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4\n /* Build timestamp (seconds since epoch) */\n@@ -1587,66 +1672,94 @@\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4\n #define\tMC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */\n@@ -1659,28 +1772,35 @@\n #define\tMC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1\n /*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n /*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16\n \n@@ -1688,16 +1808,22 @@\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_LEN 32\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4\n /* Build timestamp (seconds since epoch) */\n@@ -1705,40 +1831,53 @@\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_OFST 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_OFST 20\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16\n \n@@ -1746,16 +1885,22 @@\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_OFST 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4\n /* Build timestamp (seconds since epoch) */\n@@ -1763,14 +1908,18 @@\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_OFST 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_OFST 12\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1\n /*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */\n@@ -1779,6 +1928,7 @@\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4\n+#define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_OFST 28\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0\n #define\tMC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16\n \n@@ -1787,10 +1937,13 @@\n /* Qsys system ID */\n #define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0\n #define\tMC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_OFST 0\n #define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12\n #define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_OFST 0\n #define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4\n #define\tMC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8\n+#define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_OFST 0\n #define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0\n #define\tMC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4\n \n@@ -1888,29 +2041,37 @@\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LEN 48\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_OFST 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_OFST 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16\n /* Transceiver Transmit settings */\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_OFST 4\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_OFST 4\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16\n /* Transceiver Receive settings */\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_OFST 8\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_OFST 8\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16\n /* Rx eye opening */\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_OFST 12\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_OFST 12\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16\n /* PCS status word */\n@@ -1919,8 +2080,10 @@\n /* Link status word */\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_OFST 20\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_OFST 20\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1\n /* Current SFp parameters applied */\n@@ -1944,10 +2107,13 @@\n /* PHY config flags */\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_OFST 44\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_OFST 44\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1\n+#define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_OFST 44\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2\n #define\tMC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1\n \n@@ -2024,6 +2190,7 @@\n /* Capabilities of the FPGA/FC */\n #define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0\n #define\tMC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4\n+#define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_OFST 0\n #define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0\n #define\tMC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1\n \n@@ -2117,8 +2284,10 @@\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_OFST 0\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1\n #define\tMC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1\n \n@@ -2185,14 +2354,19 @@\n /* DDR soak test status word; bits [4:0] are relevant. */\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1\n+#define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_OFST 0\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4\n #define\tMC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1\n /* DDR soak test error count */\n@@ -2222,6 +2396,7 @@\n #define\tMC_CMD_AOE_IN_LEN 4\n #define\tMC_CMD_AOE_IN_OP_HDR_OFST 0\n #define\tMC_CMD_AOE_IN_OP_HDR_LEN 4\n+#define\tMC_CMD_AOE_IN_OP_OFST 0\n #define\tMC_CMD_AOE_IN_OP_LBN 0\n #define\tMC_CMD_AOE_IN_OP_WIDTH 8\n /* enum: FPGA and CPLD information */\n@@ -2408,18 +2583,25 @@\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12\n #define\tMC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4\n+#define\tMC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0\n #define\tMC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1\n #define\tMC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1\n+#define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_OFST 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16\n #define\tMC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16\n /* Length of DMA data (optional) */\n@@ -2485,6 +2667,7 @@\n /*            MC_CMD_AOE_IN_CMD_LEN 4 */\n #define\tMC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4\n #define\tMC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4\n+#define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_OFST 4\n #define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0\n #define\tMC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8\n /* enum: AOE and associated external port */\n@@ -2495,6 +2678,7 @@\n #define\tMC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2\n /* enum: Configure link state mode on given AOE port */\n #define\tMC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3\n+#define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_OFST 4\n #define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8\n #define\tMC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8\n /* enum: No-op */\n@@ -2503,6 +2687,7 @@\n #define\tMC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1\n /* enum: logical AND of all SFP ports link status */\n #define\tMC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2\n+#define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_OFST 4\n #define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16\n #define\tMC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16\n \n@@ -2605,6 +2790,7 @@\n /* FC boot control flags */\n #define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4\n #define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4\n+#define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_OFST 4\n #define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0\n #define\tMC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1\n \n@@ -2624,6 +2810,7 @@\n /* Assertion status flag. */\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_OFST 0\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8\n /* enum: No crash data available */\n@@ -2632,6 +2819,7 @@\n /*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */\n /* enum: Crash data has been sent */\n /*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */\n+#define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_OFST 0\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0\n #define\tMC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8\n /* enum: No crash has been recorded. */\n@@ -2884,12 +3072,16 @@\n /* Information on the module. */\n #define\tMC_CMD_AOE_OUT_DDR_FLAGS_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_PRESENT_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_PRESENT_LBN 0\n #define\tMC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_POWERED_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_POWERED_LBN 1\n #define\tMC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2\n #define\tMC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3\n #define\tMC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1\n /* Memory size, in MB. */\n@@ -2934,21 +3126,28 @@\n /* Flags describing status info on the module. */\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_OFST 0\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1\n /* DDR ECC status on the module. */\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8\n+#define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_OFST 4\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24\n #define\tMC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8\n \ndiff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\nindex 5209b43ace..8276cfcdb6 100644\n--- a/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\n+++ b/drivers/common/sfc_efx/base/efx_regs_mcdi_strs.h\n@@ -7,7 +7,7 @@\n /*\n  * This file is automatically generated. DO NOT EDIT IT.\n  * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and\n- * rebuild this file with \"make -C doc mcdiheaders\".\n+ * rebuild this file with \"make mcdi_headers_v5\".\n  *\n  * The version of this file has MCDI strings really used in the libefx.\n  */\n",
    "prefixes": [
        "v3",
        "02/60"
    ]
}