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GET /api/patches/78705/?format=api
{ "id": 78705, "url": "https://patches.dpdk.org/api/patches/78705/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-35-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600949555-28043-35-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600949555-28043-35-git-send-email-arybchenko@solarflare.com", "date": "2020-09-24T12:12:09", "name": "[v3,34/60] common/sfc_efx/base: fix Tx descriptor DMA sync on Riverhead", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "82a4f604f70a9016bf0470874247c82a548a4042", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-35-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12473, "url": "https://patches.dpdk.org/api/series/12473/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12473", "date": "2020-09-24T12:11:40", "name": "common/sfc_efx: support Riverhead NIC family", "version": 3, "mbox": "https://patches.dpdk.org/series/12473/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/78705/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/78705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A317DA04B1;\n\tThu, 24 Sep 2020 14:17:54 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AD0F01DEB4;\n\tThu, 24 Sep 2020 14:13:46 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 1A4F01DDE9\n for <dev@dpdk.org>; Thu, 24 Sep 2020 14:13:00 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.60])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 9DE2A60080 for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:59 +0000 (UTC)", "from us4-mdac16-27.ut7.mdlocal (unknown [10.7.66.59])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 9C71C2009A\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:59 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.174])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 0741B1C0053\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:59 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n B1D111C006E\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:58 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Thu, 24 Sep 2020 13:12:47 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:47 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCClFc026010\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:47 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 7692E1613AB\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:47 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Thu, 24 Sep 2020 13:12:09 +0100", "Message-ID": "<1600949555-28043-35-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>\n <1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-4.697000-8.000000-10", "X-TMASE-MatchedRID": "0pxx+/g/BD+39BLh6Bkc7jIjK23O9D33iK5qg1cmsr98Tu6cvkQQvKEG\n Khm9baaN2XHJ0L4jOIQs/31GzKkTsQihmwiXCMoGPwKTD1v8YV5MkOX0UoduuUXdikJnBDss6+3\n 41imwtEUvXg8b+phJFmOoqp5MGQKzGm91h6WPksYovbifIQL7GlBijjE0XjY+MTkWY9HYyZE4Cu\n qwY18cov0g2ay/3atluewO5rBHdH4fE8yM4pjsDwtuKBGekqUpnH7sbImOEBSwUgGq48Acxi36L\n DbK+BiWkEw6gK6BLxzC5v+NGA9CzKfk5FJQ7AN0RumpyZBuN/jEZGlPJHZyVTv3SaSWNZQKnhj7\n AbDzKkovOSq+nxEQtagePGmIEwXO/4UC4n7D3uWJl6tigvYfL0uFvzEYSdV+", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--4.697000-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600949579-ILI3PCILiU-Z", "Subject": "[dpdk-dev] [PATCH v3 34/60] common/sfc_efx/base: fix Tx descriptor\n\tDMA sync on Riverhead", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rx/Tx queue DMA sync should not assume descriptor size to be the same\nfor all NIC familties since it Tx descritor size is 16 on Riverhead.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/ef10_rx.c | 2 +-\n drivers/common/sfc_efx/base/ef10_tx.c | 4 ++--\n drivers/common/sfc_efx/base/efx_impl.h | 9 +++++----\n drivers/common/sfc_efx/base/efx_rx.c | 2 +-\n drivers/common/sfc_efx/base/efx_tx.c | 2 +-\n 5 files changed, 10 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/ef10_rx.c b/drivers/common/sfc_efx/base/ef10_rx.c\nindex 61e0dab5b9..2f0d2d2f5b 100644\n--- a/drivers/common/sfc_efx/base/ef10_rx.c\n+++ b/drivers/common/sfc_efx/base/ef10_rx.c\n@@ -693,7 +693,7 @@ ef10_rx_qpush(\n \n \t/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */\n \tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,\n-\t wptr, pushed & erp->er_mask);\n+\t EF10_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);\n \tEFSYS_PIO_WRITE_BARRIER();\n \tEFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,\n \t erp->er_index, &dword, B_FALSE);\ndiff --git a/drivers/common/sfc_efx/base/ef10_tx.c b/drivers/common/sfc_efx/base/ef10_tx.c\nindex 61c7e49fe8..7cc9324b4b 100644\n--- a/drivers/common/sfc_efx/base/ef10_tx.c\n+++ b/drivers/common/sfc_efx/base/ef10_tx.c\n@@ -375,7 +375,7 @@ ef10_tx_qpush(\n \n \t\t/* Ensure ordering of memory (descriptors) and PIO (doorbell) */\n \t\tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,\n-\t\t\t\t\t wptr, id);\n+\t\t EF10_TXQ_DESC_SIZE, wptr, id);\n \t\tEFSYS_PIO_WRITE_BARRIER();\n \t\tEFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,\n \t\t etp->et_index, &oword);\n@@ -391,7 +391,7 @@ ef10_tx_qpush(\n \n \t\t/* Ensure ordering of memory (descriptors) and PIO (doorbell) */\n \t\tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,\n-\t\t\t\t\t wptr, id);\n+\t\t EF10_TXQ_DESC_SIZE, wptr, id);\n \t\tEFSYS_PIO_WRITE_BARRIER();\n \t\tEFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,\n \t\t etp->et_index, &dword, B_FALSE);\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex d7e11c6323..52f974073f 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -1292,15 +1292,16 @@ struct efx_txq_s {\n \t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n \t} while (B_FALSE)\n \n-#define\tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)\t\\\n+#define\tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,\t\\\n+\t\t\t\t _wptr, _owptr)\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tunsigned int _new = (_wptr);\t\t\t\t\\\n \t\tunsigned int _old = (_owptr);\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t\tif ((_new) >= (_old))\t\t\t\t\t\\\n \t\t\tEFSYS_DMA_SYNC_FOR_DEVICE((_esmp),\t\t\\\n-\t\t\t (_old) * sizeof (efx_desc_t),\t\t\\\n-\t\t\t ((_new) - (_old)) * sizeof (efx_desc_t));\t\\\n+\t\t\t (_old) * (_desc_size),\t\t\t\\\n+\t\t\t ((_new) - (_old)) * (_desc_size));\t\t\\\n \t\telse\t\t\t\t\t\t\t\\\n \t\t\t/*\t\t\t\t\t\t\\\n \t\t\t * It is cheaper to sync entire map than sync\t\\\n@@ -1309,7 +1310,7 @@ struct efx_txq_s {\n \t\t\t */\t\t\t\t\t\t\\\n \t\t\tEFSYS_DMA_SYNC_FOR_DEVICE((_esmp),\t\t\\\n \t\t\t 0,\t\t\t\t\t\t\\\n-\t\t\t (_entries) * sizeof (efx_desc_t));\t\t\\\n+\t\t\t (_entries) * (_desc_size));\t\t\t\\\n \t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n \t} while (B_FALSE)\n \ndiff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c\nindex 5f17bf3afe..14eda45f4a 100644\n--- a/drivers/common/sfc_efx/base/efx_rx.c\n+++ b/drivers/common/sfc_efx/base/efx_rx.c\n@@ -1581,7 +1581,7 @@ siena_rx_qpush(\n \n \t/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */\n \tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,\n-\t wptr, pushed & erp->er_mask);\n+\t SIENA_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);\n \tEFSYS_PIO_WRITE_BARRIER();\n \tEFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,\n \t\t\t erp->er_index, &dword, B_FALSE);\ndiff --git a/drivers/common/sfc_efx/base/efx_tx.c b/drivers/common/sfc_efx/base/efx_tx.c\nindex d7f31fd46d..d9568bf4a6 100644\n--- a/drivers/common/sfc_efx/base/efx_tx.c\n+++ b/drivers/common/sfc_efx/base/efx_tx.c\n@@ -866,7 +866,7 @@ siena_tx_qpush(\n \n \t/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */\n \tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,\n-\t wptr, pushed & etp->et_mask);\n+\t SIENA_TXQ_DESC_SIZE, wptr, pushed & etp->et_mask);\n \tEFSYS_PIO_WRITE_BARRIER();\n \tEFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,\n \t\t\t etp->et_index, &dword, B_FALSE);\n", "prefixes": [ "v3", "34/60" ] }