Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/78698/?format=api
{ "id": 78698, "url": "https://patches.dpdk.org/api/patches/78698/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-24-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600949555-28043-24-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600949555-28043-24-git-send-email-arybchenko@solarflare.com", "date": "2020-09-24T12:11:58", "name": "[v3,23/60] common/sfc_efx/base: add event queue module for Riverhead", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bbc6461f31579d483d741e5a0901ee0b05bf3cff", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-24-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12473, "url": "https://patches.dpdk.org/api/series/12473/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12473", "date": "2020-09-24T12:11:40", "name": "common/sfc_efx: support Riverhead NIC family", "version": 3, "mbox": "https://patches.dpdk.org/series/12473/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/78698/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/78698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 12000A04B1;\n\tThu, 24 Sep 2020 14:16:35 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B802D1DE95;\n\tThu, 24 Sep 2020 14:13:37 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 2DDF41DE16\n for <dev@dpdk.org>; Thu, 24 Sep 2020 14:12:58 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.61])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 993A1600AB for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:57 +0000 (UTC)", "from us4-mdac16-9.ut7.mdlocal (unknown [10.7.65.177])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 97D9E800A4\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:57 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.174])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 1119480052\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:57 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n BB30F1C006E\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:56 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Thu, 24 Sep 2020 13:12:47 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:46 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCCkdT025957\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:46 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id DD46B1613A9\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:46 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Thu, 24 Sep 2020 13:11:58 +0100", "Message-ID": "<1600949555-28043-24-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>\n <1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-2.782700-8.000000-10", "X-TMASE-MatchedRID": "2nX43281tfLxS+DKaBymNNm6V9lyTcKhJGh48zigYxUm3tlnC/E6VOZ5\n Gn23AeDZuA9fFHhyLzywgcHDNo5AtPI1YbpS1+avPwKTD1v8YV5MkOX0UoduuVVkJxysad/IJGZ\n 0d4KSzVJEj+W35/xeanyAzXnKF8SjhMgg0NxeFawqsMfMfrOZRUcA1Ouvduu8ddaBGkyiPh23Wj\n IVml7BRzQ41nj8u/2a+saxFRK561NJxzdMxVoC9g97mDMXdNW3ce/io1zKJlVrpD6YHU4QOuw1g\n mAhG2GAM4hLs4cdh7GQ74bS+K8hS7MywGOaB4QQUIJW4+Og/QJKgIbix5+XxB1rVWTdGrE4SPxT\n RJaTawxCgxT/GGibYSO0knbdm9tXMGg+wgnY/ellpwNsTvdlKf79kuWeDe6KclEZ0EDaOYjeaXa\n qx8P4MkzMGb6zS1tZjTE+m11oKuAeBRC8fzEM9CyKzJY7d2nbpxoLgv7S3sAHWPn2mj7oRIU5i7\n 0LbWcciYudapQzIa+/0KHo86FaOv5VZrGTCJG/bWsCUkrA4EmtggmrIZxcdc288EjhWgdoo0YGr\n aGLZ0BXG1puYu9iTSwPha7vXEnJs1dXYh6zp8fiHyvyXeXh5hfNah8m7SiNRjNrjV0arFKRvCTB\n x6I65SBj027VCXoAq9J6dPzwLxKvvxILmKK/HBRFJJyf5BJe3QfwsVk0UbsIoUKaF27lxQCvAdu\n 6XkiNNecfeclMFjvtmioV/te8SjBa687SM1pezXtDAqAweJfv+et2ehg1xYoNnxdT4Yu+029wcB\n u4jeULw344u45zBwDlJLZdGMoUz5pk4iF6iVS+9SjSFk+GXMz/jdQvUwlHnqg/VrSZEiM=", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--2.782700-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600949577-8uCTOT09s463", "Subject": "[dpdk-dev] [PATCH v3 23/60] common/sfc_efx/base: add event queue\n\tmodule for Riverhead", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Events are significantly reworked on Riverhead, so it is better\nto implement own set of callbacks to simplify future development\nand avoid inheritance of legacy code.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx_ev.c | 22 ++\n drivers/common/sfc_efx/base/efx_impl.h | 4 +-\n drivers/common/sfc_efx/base/efx_mcdi.c | 19 +-\n drivers/common/sfc_efx/base/meson.build | 1 +\n drivers/common/sfc_efx/base/rhead_ev.c | 265 +++++++++++++++++++++++\n drivers/common/sfc_efx/base/rhead_impl.h | 73 +++++++\n 6 files changed, 379 insertions(+), 5 deletions(-)\n create mode 100644 drivers/common/sfc_efx/base/rhead_ev.c", "diff": "diff --git a/drivers/common/sfc_efx/base/efx_ev.c b/drivers/common/sfc_efx/base/efx_ev.c\nindex 4d11c531ce..edc1b182c9 100644\n--- a/drivers/common/sfc_efx/base/efx_ev.c\n+++ b/drivers/common/sfc_efx/base/efx_ev.c\n@@ -109,6 +109,22 @@ static const efx_ev_ops_t\t__efx_ev_ef10_ops = {\n };\n #endif /* EFX_OPTS_EF10() */\n \n+#if EFSYS_OPT_RIVERHEAD\n+static const efx_ev_ops_t\t__efx_ev_rhead_ops = {\n+\trhead_ev_init,\t\t\t\t/* eevo_init */\n+\trhead_ev_fini,\t\t\t\t/* eevo_fini */\n+\trhead_ev_qcreate,\t\t\t/* eevo_qcreate */\n+\trhead_ev_qdestroy,\t\t\t/* eevo_qdestroy */\n+\trhead_ev_qprime,\t\t\t/* eevo_qprime */\n+\trhead_ev_qpost,\t\t\t\t/* eevo_qpost */\n+\trhead_ev_qpoll,\t\t\t\t/* eevo_qpoll */\n+\trhead_ev_qmoderate,\t\t\t/* eevo_qmoderate */\n+#if EFSYS_OPT_QSTATS\n+\trhead_ev_qstats_update,\t\t\t/* eevo_qstats_update */\n+#endif\n+};\n+#endif /* EFSYS_OPT_RIVERHEAD */\n+\n \n \t__checkReturn\tefx_rc_t\n efx_ev_init(\n@@ -150,6 +166,12 @@ efx_ev_init(\n \t\tbreak;\n #endif /* EFSYS_OPT_MEDFORD2 */\n \n+#if EFSYS_OPT_RIVERHEAD\n+\tcase EFX_FAMILY_RIVERHEAD:\n+\t\teevop = &__efx_ev_rhead_ops;\n+\t\tbreak;\n+#endif /* EFSYS_OPT_RIVERHEAD */\n+\n \tdefault:\n \t\tEFSYS_ASSERT(0);\n \t\trc = ENOTSUP;\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex 47e4dcb01f..f6b0850a65 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -1408,7 +1408,7 @@ efx_mcdi_get_workarounds(\n \t__out_opt\t\tuint32_t *implementedp,\n \t__out_opt\t\tuint32_t *enabledp);\n \n-#if EFX_OPTS_EF10()\n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n \n LIBEFX_INTERNAL\n extern\t__checkReturn\tefx_rc_t\n@@ -1428,7 +1428,7 @@ efx_mcdi_fini_evq(\n \t__in\t\tefx_nic_t *enp,\n \t__in\t\tuint32_t instance);\n \n-#endif\t/* EFX_OPTS_EF10() */\n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n \n #endif /* EFSYS_OPT_MCDI */\n \ndiff --git a/drivers/common/sfc_efx/base/efx_mcdi.c b/drivers/common/sfc_efx/base/efx_mcdi.c\nindex 69d2327839..841dacc1c8 100644\n--- a/drivers/common/sfc_efx/base/efx_mcdi.c\n+++ b/drivers/common/sfc_efx/base/efx_mcdi.c\n@@ -2443,7 +2443,20 @@ efx_mcdi_phy_module_get_info(\n \treturn (rc);\n }\n \n+#if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()\n+\n+#define\tINIT_EVQ_MAXNBUFS\tMC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM\n+\n #if EFX_OPTS_EF10()\n+# if (INIT_EVQ_MAXNBUFS < EF10_EVQ_MAXNBUFS)\n+# error \"INIT_EVQ_MAXNBUFS too small\"\n+# endif\n+#endif /* EFX_OPTS_EF10 */\n+#if EFSYS_OPT_RIVERHEAD\n+# if (INIT_EVQ_MAXNBUFS < RHEAD_EVQ_MAXNBUFS)\n+# error \"INIT_EVQ_MAXNBUFS too small\"\n+# endif\n+#endif /* EFSYS_OPT_RIVERHEAD */\n \n \t__checkReturn\tefx_rc_t\n efx_mcdi_init_evq(\n@@ -2459,7 +2472,7 @@ efx_mcdi_init_evq(\n \tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n \tefx_mcdi_req_t req;\n \tEFX_MCDI_DECLARE_BUF(payload,\n-\t\tMC_CMD_INIT_EVQ_V2_IN_LEN(EF10_EVQ_MAXNBUFS),\n+\t\tMC_CMD_INIT_EVQ_V2_IN_LEN(INIT_EVQ_MAXNBUFS),\n \t\tMC_CMD_INIT_EVQ_V2_OUT_LEN);\n \tboolean_t interrupting;\n \tint ev_cut_through;\n@@ -2472,7 +2485,7 @@ efx_mcdi_init_evq(\n \tefx_rc_t rc;\n \n \tnpages = efx_evq_nbufs(enp, nevs);\n-\tif (npages > EF10_EVQ_MAXNBUFS) {\n+\tif (npages > INIT_EVQ_MAXNBUFS) {\n \t\trc = EINVAL;\n \t\tgoto fail1;\n \t}\n@@ -2667,6 +2680,6 @@ efx_mcdi_fini_evq(\n \treturn (rc);\n }\n \n-#endif\t/* EFX_OPTS_EF10() */\n+#endif\t/* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */\n \n #endif\t/* EFSYS_OPT_MCDI */\ndiff --git a/drivers/common/sfc_efx/base/meson.build b/drivers/common/sfc_efx/base/meson.build\nindex ea2517ba26..8e50f82154 100644\n--- a/drivers/common/sfc_efx/base/meson.build\n+++ b/drivers/common/sfc_efx/base/meson.build\n@@ -52,6 +52,7 @@ sources = [\n \t'hunt_nic.c',\n \t'medford_nic.c',\n \t'medford2_nic.c',\n+\t'rhead_ev.c',\n \t'rhead_intr.c',\n \t'rhead_nic.c',\n ]\ndiff --git a/drivers/common/sfc_efx/base/rhead_ev.c b/drivers/common/sfc_efx/base/rhead_ev.c\nnew file mode 100644\nindex 0000000000..36e355f209\n--- /dev/null\n+++ b/drivers/common/sfc_efx/base/rhead_ev.c\n@@ -0,0 +1,265 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2018-2019 Solarflare Communications Inc.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+#if EFSYS_OPT_RIVERHEAD\n+\n+/*\n+ * Non-interrupting event queue requires interrupting event queue to\n+ * refer to for wake-up events even if wake ups are never used.\n+ * It could be even non-allocated event queue.\n+ */\n+#define\tEFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX\t(0)\n+\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_ev_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\t_NOTE(ARGUNUSED(enp))\n+\n+\treturn (0);\n+}\n+\n+\t\t\tvoid\n+rhead_ev_fini(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\t_NOTE(ARGUNUSED(enp))\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_ev_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t ndescs,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint32_t us,\n+\t__in\t\tuint32_t flags,\n+\t__in\t\tefx_evq_t *eep)\n+{\n+\tuint32_t irq;\n+\tefx_rc_t rc;\n+\n+\t_NOTE(ARGUNUSED(id))\t/* buftbl id managed by MC */\n+\n+\t/* Set up the handler table */\n+\teep->ee_rx\t= NULL; /* FIXME */\n+\teep->ee_tx\t= NULL; /* FIXME */\n+\teep->ee_driver\t= NULL; /* FIXME */\n+\teep->ee_drv_gen\t= NULL; /* FIXME */\n+\teep->ee_mcdi\t= NULL; /* FIXME */\n+\n+\t/* Set up the event queue */\n+\t/* INIT_EVQ expects function-relative vector number */\n+\tif ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==\n+\t EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {\n+\t\tirq = index;\n+\t} else if (index == EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX) {\n+\t\tirq = index;\n+\t\tflags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |\n+\t\t EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;\n+\t} else {\n+\t\tirq = EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX;\n+\t}\n+\n+\t/*\n+\t * Interrupts may be raised for events immediately after the queue is\n+\t * created. See bug58606.\n+\t */\n+\trc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,\n+\t B_FALSE);\n+\tif (rc != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+rhead_ev_qdestroy(\n+\t__in\t\tefx_evq_t *eep)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\n+\tEFSYS_ASSERT(enp->en_family == EFX_FAMILY_RIVERHEAD);\n+\n+\t(void) efx_mcdi_fini_evq(enp, eep->ee_index);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_ev_qprime(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tuint32_t rptr;\n+\tefx_dword_t dword;\n+\n+\trptr = count & eep->ee_mask;\n+\n+\tEFX_POPULATE_DWORD_2(dword, ERF_GZ_EVQ_ID, eep->ee_index,\n+\t ERF_GZ_IDX, rptr);\n+\t/* EVQ_INT_PRIME lives function control window only on Riverhead */\n+\tEFX_BAR_WRITED(enp, ER_GZ_EVQ_INT_PRIME, &dword, B_FALSE);\n+\n+\treturn (0);\n+}\n+\n+\t\t\tvoid\n+rhead_ev_qpost(\n+\t__in\tefx_evq_t *eep,\n+\t__in\tuint16_t data)\n+{\n+\t_NOTE(ARGUNUSED(eep, data))\n+\n+\t/* Not implemented yet */\n+\tEFSYS_ASSERT(B_FALSE);\n+}\n+\n+/*\n+ * Poll event queue in batches. Size of the batch is equal to cache line\n+ * size divided by event size.\n+ *\n+ * Event queue is written by NIC and read by CPU. If CPU starts reading\n+ * of events on the cache line, read all remaining events in a tight\n+ * loop while event is present.\n+ */\n+#define\tEF100_EV_BATCH\t8\n+\n+/*\n+ * Check if event is present.\n+ *\n+ * Riverhead EvQs use a phase bit to indicate the presence of valid events,\n+ * by flipping the phase bit on each wrap of the write index.\n+ */\n+#define\tEF100_EV_PRESENT(_qword, _phase_bit)\t\t\t\t\\\n+\t(EFX_QWORD_FIELD((_qword), ESF_GZ_EV_EVQ_PHASE) == _phase_bit)\n+\n+\t\t\tvoid\n+rhead_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg)\n+{\n+\tefx_qword_t ev[EF100_EV_BATCH];\n+\tunsigned int batch;\n+\tunsigned int phase_bit;\n+\tunsigned int total;\n+\tunsigned int count;\n+\tunsigned int index;\n+\tsize_t offset;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\tEFSYS_ASSERT(countp != NULL);\n+\tEFSYS_ASSERT(eecp != NULL);\n+\n+\tcount = *countp;\n+\tdo {\n+\t\t/* Read up until the end of the batch period */\n+\t\tbatch = EF100_EV_BATCH - (count & (EF100_EV_BATCH - 1));\n+\t\tphase_bit = (count & (eep->ee_mask + 1)) != 0;\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\t\tfor (total = 0; total < batch; ++total) {\n+\t\t\tEFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));\n+\n+\t\t\tif (!EF100_EV_PRESENT(ev[total], phase_bit))\n+\t\t\t\tbreak;\n+\n+\t\t\tEFSYS_PROBE3(event, unsigned int, eep->ee_index,\n+\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),\n+\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));\n+\n+\t\t\toffset += sizeof (efx_qword_t);\n+\t\t}\n+\n+\t\t/* Process the batch of events */\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tboolean_t should_abort;\n+\t\t\tuint32_t code;\n+\n+\t\t\tEFX_EV_QSTAT_INCR(eep, EV_ALL);\n+\n+\t\t\tcode = EFX_QWORD_FIELD(ev[index], ESF_GZ_E_TYPE);\n+\t\t\tswitch (code) {\n+\t\t\tdefault:\n+\t\t\t\tEFSYS_PROBE3(bad_event,\n+\t\t\t\t unsigned int, eep->ee_index,\n+\t\t\t\t uint32_t,\n+\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),\n+\t\t\t\t uint32_t,\n+\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));\n+\n+\t\t\t\tEFSYS_ASSERT(eecp->eec_exception != NULL);\n+\t\t\t\t(void) eecp->eec_exception(arg,\n+\t\t\t\t\tEFX_EXCEPTION_EV_ERROR, code);\n+\t\t\t\tshould_abort = B_TRUE;\n+\t\t\t}\n+\t\t\tif (should_abort) {\n+\t\t\t\t/* Ignore subsequent events */\n+\t\t\t\ttotal = index + 1;\n+\n+\t\t\t\t/*\n+\t\t\t\t * Poison batch to ensure the outer\n+\t\t\t\t * loop is broken out of.\n+\t\t\t\t */\n+\t\t\t\tEFSYS_ASSERT(batch <= EF100_EV_BATCH);\n+\t\t\t\tbatch += (EF100_EV_BATCH << 1);\n+\t\t\t\tEFSYS_ASSERT(total != batch);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * There is no necessity to clear processed events since\n+\t\t * phase bit which is flipping on each write index wrap\n+\t\t * is used for event presence indication.\n+\t\t */\n+\n+\t\tcount += total;\n+\n+\t} while (total == batch);\n+\n+\t*countp = count;\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+rhead_ev_qmoderate(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int us)\n+{\n+\t_NOTE(ARGUNUSED(eep, us))\n+\n+\treturn (ENOTSUP);\n+}\n+\n+\n+#if EFSYS_OPT_QSTATS\n+\t\t\tvoid\n+rhead_ev_qstats_update(\n+\t__in\t\t\t\tefx_evq_t *eep,\n+\t__inout_ecount(EV_NQSTATS)\tefsys_stat_t *stat)\n+{\n+\tunsigned int id;\n+\n+\tfor (id = 0; id < EV_NQSTATS; id++) {\n+\t\tefsys_stat_t *essp = &stat[id];\n+\n+\t\tEFSYS_STAT_INCR(essp, eep->ee_stat[id]);\n+\t\teep->ee_stat[id] = 0;\n+\t}\n+}\n+#endif /* EFSYS_OPT_QSTATS */\n+\n+#endif\t/* EFSYS_OPT_RIVERHEAD */\ndiff --git a/drivers/common/sfc_efx/base/rhead_impl.h b/drivers/common/sfc_efx/base/rhead_impl.h\nindex b95302a13f..47885b28dc 100644\n--- a/drivers/common/sfc_efx/base/rhead_impl.h\n+++ b/drivers/common/sfc_efx/base/rhead_impl.h\n@@ -12,6 +12,13 @@ extern \"C\" {\n #endif\n \n \n+/*\n+ * Riverhead requires physically contiguous event rings (so, just one\n+ * DMA address is sufficient to represent it), but MCDI interface is still\n+ * in terms of 4k size 4k-aligned DMA buffers.\n+ */\n+#define\tRHEAD_EVQ_MAXNBUFS\t32\n+\n #define\tRHEAD_EVQ_MAXNEVS\t16384\n #define\tRHEAD_EVQ_MINNEVS\t256\n \n@@ -98,6 +105,72 @@ rhead_nic_unprobe(\n \t__in\t\tefx_nic_t *enp);\n \n \n+/* EV */\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_ev_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_ev_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_ev_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t ndescs,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint32_t us,\n+\t__in\t\tuint32_t flags,\n+\t__in\t\tefx_evq_t *eep);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_ev_qdestroy(\n+\t__in\t\tefx_evq_t *eep);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_ev_qprime(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_ev_qpost(\n+\t__in\tefx_evq_t *eep,\n+\t__in\tuint16_t data);\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg);\n+\n+LIBEFX_INTERNAL\n+extern\t__checkReturn\tefx_rc_t\n+rhead_ev_qmoderate(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int us);\n+\n+#if EFSYS_OPT_QSTATS\n+\n+LIBEFX_INTERNAL\n+extern\t\t\tvoid\n+rhead_ev_qstats_update(\n+\t__in\t\t\t\tefx_evq_t *eep,\n+\t__inout_ecount(EV_NQSTATS)\tefsys_stat_t *stat);\n+\n+#endif /* EFSYS_OPT_QSTATS */\n+\n+\n /* INTR */\n \n LIBEFX_INTERNAL\n", "prefixes": [ "v3", "23/60" ] }