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GET /api/patches/78685/?format=api
{ "id": 78685, "url": "https://patches.dpdk.org/api/patches/78685/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-4-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600949555-28043-4-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600949555-28043-4-git-send-email-arybchenko@solarflare.com", "date": "2020-09-24T12:11:38", "name": "[v3,03/60] common/sfc_efx/base: add event queue operation to do polling", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "347ab36fd11f62282370948441863d63245af409", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-4-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12473, "url": "https://patches.dpdk.org/api/series/12473/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12473", "date": "2020-09-24T12:11:40", "name": "common/sfc_efx: support Riverhead NIC family", "version": 3, "mbox": "https://patches.dpdk.org/series/12473/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/78685/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/78685/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 10D9AA04B1;\n\tThu, 24 Sep 2020 14:14:05 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CF62C1DE37;\n\tThu, 24 Sep 2020 14:13:06 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id CE5761DE05\n for <dev@dpdk.org>; Thu, 24 Sep 2020 14:12:53 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.62])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 572DB6008B for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:53 +0000 (UTC)", "from us4-mdac16-30.ut7.mdlocal (unknown [10.7.66.140])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 560788009E\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:53 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.175])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n CC29D280050\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:52 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 83985700080\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:12:52 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Thu, 24 Sep 2020 13:12:46 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:45 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCCj1p025856\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:45 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id D2EA11613CB\n for <dev@dpdk.org>; Thu, 24 Sep 2020 13:12:45 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Thu, 24 Sep 2020 13:11:38 +0100", "Message-ID": "<1600949555-28043-4-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>\n <1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-0.593400-8.000000-10", "X-TMASE-MatchedRID": "ODoBVYkg5ew5s4xK97Sm/y2416nc3bQleouvej40T4iOSVCvVHWJJ3Io\n zGa69omdrdoLblq9S5ppXb8sy/poSXgz4aOScPlwrSAIWhdbeu/YuVu0X/rOkHQWhLVqLFM1L9s\n LsKTPVsdLppfJBfUpsB1WgSKhcF9mO5sXKty63LOYHemjphKeG0ewdu9S21aiTuMthH6Q7+axhF\n PYXnMHTTxKBm/JHgg6PVl7l1/G8qhOP86VSsrMrCyKzJY7d2nb9oVAKMBioqcOkJQR4QWbsIaxU\n TVLPuXrRGLtePI1ArxUgpn09r97XhmNqsUuotRsKrDHzH6zmUU1byNCHOgAtWA8lgItGhROIhkP\n ISqGf1zjHA7psXrHJVixjdsX+oPcLHYzuCshKgieAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8ifEzJ\n 5hPndGVinvXXlRB70tOUL3OUSzITZOAcPZFIlbS088my88Cn2XG+uKPLjRvJaDmWVQIAYx5Gubb\n jGCH9piJRo85ODGlwFrlMGI5VhVRySoBCeolQDq8uPJC94SFgR06l6KId4N3r0M0SKNnXWVlxr1\n FJij9s=", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--0.593400-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600949573-bfAcTz3tLfgI", "Subject": "[dpdk-dev] [PATCH v3 03/60] common/sfc_efx/base: add event queue\n\toperation to do polling", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Event queue host interface differ on Riverhead and implementation\nwill be different.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx_ev.c | 325 ++++++++++++++-----------\n drivers/common/sfc_efx/base/efx_impl.h | 2 +\n 2 files changed, 182 insertions(+), 145 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx_ev.c b/drivers/common/sfc_efx/base/efx_ev.c\nindex e6a8d4ca1a..21fddfb64d 100644\n--- a/drivers/common/sfc_efx/base/efx_ev.c\n+++ b/drivers/common/sfc_efx/base/efx_ev.c\n@@ -66,6 +66,17 @@ siena_ev_qstats_update(\n \n #endif /* EFSYS_OPT_SIENA */\n \n+#if EFX_OPTS_EF10() || EFSYS_OPT_SIENA\n+\n+static\t\t\tvoid\n+siena_ef10_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg);\n+\n+#endif\t/* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */\n+\n #if EFSYS_OPT_SIENA\n static const efx_ev_ops_t\t__efx_ev_siena_ops = {\n \tsiena_ev_init,\t\t\t\t/* eevo_init */\n@@ -74,6 +85,7 @@ static const efx_ev_ops_t\t__efx_ev_siena_ops = {\n \tsiena_ev_qdestroy,\t\t\t/* eevo_qdestroy */\n \tsiena_ev_qprime,\t\t\t/* eevo_qprime */\n \tsiena_ev_qpost,\t\t\t\t/* eevo_qpost */\n+\tsiena_ef10_ev_qpoll,\t\t\t/* eevo_qpoll */\n \tsiena_ev_qmoderate,\t\t\t/* eevo_qmoderate */\n #if EFSYS_OPT_QSTATS\n \tsiena_ev_qstats_update,\t\t\t/* eevo_qstats_update */\n@@ -89,6 +101,7 @@ static const efx_ev_ops_t\t__efx_ev_ef10_ops = {\n \tef10_ev_qdestroy,\t\t\t/* eevo_qdestroy */\n \tef10_ev_qprime,\t\t\t\t/* eevo_qprime */\n \tef10_ev_qpost,\t\t\t\t/* eevo_qpost */\n+\tsiena_ef10_ev_qpoll,\t\t\t/* eevo_qpoll */\n \tef10_ev_qmoderate,\t\t\t/* eevo_qmoderate */\n #if EFSYS_OPT_QSTATS\n \tef10_ev_qstats_update,\t\t\t/* eevo_qstats_update */\n@@ -374,8 +387,6 @@ efx_ev_qprefetch(\n \n #endif\t/* EFSYS_OPT_EV_PREFETCH */\n \n-#define\tEFX_EV_BATCH\t8\n-\n \t\t\tvoid\n efx_ev_qpoll(\n \t__in\t\tefx_evq_t *eep,\n@@ -383,153 +394,15 @@ efx_ev_qpoll(\n \t__in\t\tconst efx_ev_callbacks_t *eecp,\n \t__in_opt\tvoid *arg)\n {\n-\tefx_qword_t ev[EFX_EV_BATCH];\n-\tunsigned int batch;\n-\tunsigned int total;\n-\tunsigned int count;\n-\tunsigned int index;\n-\tsize_t offset;\n-\n-\t/* Ensure events codes match for EF10 (Huntington/Medford) and Siena */\n-\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);\n-\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);\n-\n-\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);\n-\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);\n-\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);\n-\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==\n-\t FSE_AZ_EV_CODE_DRV_GEN_EV);\n-#if EFSYS_OPT_MCDI\n-\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==\n-\t FSE_AZ_EV_CODE_MCDI_EVRESPONSE);\n-#endif\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n \n \tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n-\tEFSYS_ASSERT(countp != NULL);\n-\tEFSYS_ASSERT(eecp != NULL);\n-\n-\tcount = *countp;\n-\tdo {\n-\t\t/* Read up until the end of the batch period */\n-\t\tbatch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));\n-\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n-\t\tfor (total = 0; total < batch; ++total) {\n-\t\t\tEFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));\n-\n-\t\t\tif (!EFX_EV_PRESENT(ev[total]))\n-\t\t\t\tbreak;\n-\n-\t\t\tEFSYS_PROBE3(event, unsigned int, eep->ee_index,\n-\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),\n-\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));\n-\n-\t\t\toffset += sizeof (efx_qword_t);\n-\t\t}\n-\n-#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)\n-\t\t/*\n-\t\t * Prefetch the next batch when we get within PREFETCH_PERIOD\n-\t\t * of a completed batch. If the batch is smaller, then prefetch\n-\t\t * immediately.\n-\t\t */\n-\t\tif (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)\n-\t\t\tEFSYS_MEM_PREFETCH(eep->ee_esmp, offset);\n-#endif\t/* EFSYS_OPT_EV_PREFETCH */\n-\n-\t\t/* Process the batch of events */\n-\t\tfor (index = 0; index < total; ++index) {\n-\t\t\tboolean_t should_abort;\n-\t\t\tuint32_t code;\n-\n-#if EFSYS_OPT_EV_PREFETCH\n-\t\t\t/* Prefetch if we've now reached the batch period */\n-\t\t\tif (total == batch &&\n-\t\t\t index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {\n-\t\t\t\toffset = (count + batch) & eep->ee_mask;\n-\t\t\t\toffset *= sizeof (efx_qword_t);\n-\n-\t\t\t\tEFSYS_MEM_PREFETCH(eep->ee_esmp, offset);\n-\t\t\t}\n-#endif\t/* EFSYS_OPT_EV_PREFETCH */\n-\n-\t\t\tEFX_EV_QSTAT_INCR(eep, EV_ALL);\n \n-\t\t\tcode = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);\n-\t\t\tswitch (code) {\n-\t\t\tcase FSE_AZ_EV_CODE_RX_EV:\n-\t\t\t\tshould_abort = eep->ee_rx(eep,\n-\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\tbreak;\n-\t\t\tcase FSE_AZ_EV_CODE_TX_EV:\n-\t\t\t\tshould_abort = eep->ee_tx(eep,\n-\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\tbreak;\n-\t\t\tcase FSE_AZ_EV_CODE_DRIVER_EV:\n-\t\t\t\tshould_abort = eep->ee_driver(eep,\n-\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\tbreak;\n-\t\t\tcase FSE_AZ_EV_CODE_DRV_GEN_EV:\n-\t\t\t\tshould_abort = eep->ee_drv_gen(eep,\n-\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\tbreak;\n-#if EFSYS_OPT_MCDI\n-\t\t\tcase FSE_AZ_EV_CODE_MCDI_EVRESPONSE:\n-\t\t\t\tshould_abort = eep->ee_mcdi(eep,\n-\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\tbreak;\n-#endif\n-\t\t\tcase FSE_AZ_EV_CODE_GLOBAL_EV:\n-\t\t\t\tif (eep->ee_global) {\n-\t\t\t\t\tshould_abort = eep->ee_global(eep,\n-\t\t\t\t\t &(ev[index]), eecp, arg);\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\t/* else fallthrough */\n-\t\t\tdefault:\n-\t\t\t\tEFSYS_PROBE3(bad_event,\n-\t\t\t\t unsigned int, eep->ee_index,\n-\t\t\t\t uint32_t,\n-\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),\n-\t\t\t\t uint32_t,\n-\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));\n-\n-\t\t\t\tEFSYS_ASSERT(eecp->eec_exception != NULL);\n-\t\t\t\t(void) eecp->eec_exception(arg,\n-\t\t\t\t\tEFX_EXCEPTION_EV_ERROR, code);\n-\t\t\t\tshould_abort = B_TRUE;\n-\t\t\t}\n-\t\t\tif (should_abort) {\n-\t\t\t\t/* Ignore subsequent events */\n-\t\t\t\ttotal = index + 1;\n-\n-\t\t\t\t/*\n-\t\t\t\t * Poison batch to ensure the outer\n-\t\t\t\t * loop is broken out of.\n-\t\t\t\t */\n-\t\t\t\tEFSYS_ASSERT(batch <= EFX_EV_BATCH);\n-\t\t\t\tbatch += (EFX_EV_BATCH << 1);\n-\t\t\t\tEFSYS_ASSERT(total != batch);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\t/*\n-\t\t * Now that the hardware has most likely moved onto dma'ing\n-\t\t * into the next cache line, clear the processed events. Take\n-\t\t * care to only clear out events that we've processed\n-\t\t */\n-\t\tEFX_SET_QWORD(ev[0]);\n-\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n-\t\tfor (index = 0; index < total; ++index) {\n-\t\t\tEFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));\n-\t\t\toffset += sizeof (efx_qword_t);\n-\t\t}\n-\n-\t\tcount += total;\n-\n-\t} while (total == batch);\n+\tEFSYS_ASSERT(eevop != NULL &&\n+\t eevop->eevo_qpoll != NULL);\n \n-\t*countp = count;\n+\teevop->eevo_qpoll(eep, countp, eecp, arg);\n }\n \n \t\t\tvoid\n@@ -1484,3 +1357,165 @@ siena_ev_fini(\n }\n \n #endif /* EFSYS_OPT_SIENA */\n+\n+#if EFX_OPTS_EF10() || EFSYS_OPT_SIENA\n+\n+#define\tEFX_EV_BATCH\t8\n+\n+static\t\t\tvoid\n+siena_ef10_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg)\n+{\n+\tefx_qword_t ev[EFX_EV_BATCH];\n+\tunsigned int batch;\n+\tunsigned int total;\n+\tunsigned int count;\n+\tunsigned int index;\n+\tsize_t offset;\n+\n+\t/* Ensure events codes match for EF10 (Huntington/Medford) and Siena */\n+\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);\n+\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);\n+\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==\n+\t FSE_AZ_EV_CODE_DRV_GEN_EV);\n+#if EFSYS_OPT_MCDI\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==\n+\t FSE_AZ_EV_CODE_MCDI_EVRESPONSE);\n+#endif\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\tEFSYS_ASSERT(countp != NULL);\n+\tEFSYS_ASSERT(eecp != NULL);\n+\n+\tcount = *countp;\n+\tdo {\n+\t\t/* Read up until the end of the batch period */\n+\t\tbatch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\t\tfor (total = 0; total < batch; ++total) {\n+\t\t\tEFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));\n+\n+\t\t\tif (!EFX_EV_PRESENT(ev[total]))\n+\t\t\t\tbreak;\n+\n+\t\t\tEFSYS_PROBE3(event, unsigned int, eep->ee_index,\n+\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),\n+\t\t\t uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));\n+\n+\t\t\toffset += sizeof (efx_qword_t);\n+\t\t}\n+\n+#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)\n+\t\t/*\n+\t\t * Prefetch the next batch when we get within PREFETCH_PERIOD\n+\t\t * of a completed batch. If the batch is smaller, then prefetch\n+\t\t * immediately.\n+\t\t */\n+\t\tif (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)\n+\t\t\tEFSYS_MEM_PREFETCH(eep->ee_esmp, offset);\n+#endif\t/* EFSYS_OPT_EV_PREFETCH */\n+\n+\t\t/* Process the batch of events */\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tboolean_t should_abort;\n+\t\t\tuint32_t code;\n+\n+#if EFSYS_OPT_EV_PREFETCH\n+\t\t\t/* Prefetch if we've now reached the batch period */\n+\t\t\tif (total == batch &&\n+\t\t\t index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {\n+\t\t\t\toffset = (count + batch) & eep->ee_mask;\n+\t\t\t\toffset *= sizeof (efx_qword_t);\n+\n+\t\t\t\tEFSYS_MEM_PREFETCH(eep->ee_esmp, offset);\n+\t\t\t}\n+#endif\t/* EFSYS_OPT_EV_PREFETCH */\n+\n+\t\t\tEFX_EV_QSTAT_INCR(eep, EV_ALL);\n+\n+\t\t\tcode = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);\n+\t\t\tswitch (code) {\n+\t\t\tcase FSE_AZ_EV_CODE_RX_EV:\n+\t\t\t\tshould_abort = eep->ee_rx(eep,\n+\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_TX_EV:\n+\t\t\t\tshould_abort = eep->ee_tx(eep,\n+\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_DRIVER_EV:\n+\t\t\t\tshould_abort = eep->ee_driver(eep,\n+\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_DRV_GEN_EV:\n+\t\t\t\tshould_abort = eep->ee_drv_gen(eep,\n+\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+#if EFSYS_OPT_MCDI\n+\t\t\tcase FSE_AZ_EV_CODE_MCDI_EVRESPONSE:\n+\t\t\t\tshould_abort = eep->ee_mcdi(eep,\n+\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+#endif\n+\t\t\tcase FSE_AZ_EV_CODE_GLOBAL_EV:\n+\t\t\t\tif (eep->ee_global) {\n+\t\t\t\t\tshould_abort = eep->ee_global(eep,\n+\t\t\t\t\t &(ev[index]), eecp, arg);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\t/* else fallthrough */\n+\t\t\tdefault:\n+\t\t\t\tEFSYS_PROBE3(bad_event,\n+\t\t\t\t unsigned int, eep->ee_index,\n+\t\t\t\t uint32_t,\n+\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),\n+\t\t\t\t uint32_t,\n+\t\t\t\t EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));\n+\n+\t\t\t\tEFSYS_ASSERT(eecp->eec_exception != NULL);\n+\t\t\t\t(void) eecp->eec_exception(arg,\n+\t\t\t\t\tEFX_EXCEPTION_EV_ERROR, code);\n+\t\t\t\tshould_abort = B_TRUE;\n+\t\t\t}\n+\t\t\tif (should_abort) {\n+\t\t\t\t/* Ignore subsequent events */\n+\t\t\t\ttotal = index + 1;\n+\n+\t\t\t\t/*\n+\t\t\t\t * Poison batch to ensure the outer\n+\t\t\t\t * loop is broken out of.\n+\t\t\t\t */\n+\t\t\t\tEFSYS_ASSERT(batch <= EFX_EV_BATCH);\n+\t\t\t\tbatch += (EFX_EV_BATCH << 1);\n+\t\t\t\tEFSYS_ASSERT(total != batch);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Now that the hardware has most likely moved onto dma'ing\n+\t\t * into the next cache line, clear the processed events. Take\n+\t\t * care to only clear out events that we've processed\n+\t\t */\n+\t\tEFX_SET_QWORD(ev[0]);\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tEFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));\n+\t\t\toffset += sizeof (efx_qword_t);\n+\t\t}\n+\n+\t\tcount += total;\n+\n+\t} while (total == batch);\n+\n+\t*countp = count;\n+}\n+\n+#endif\t/* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */\ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex 87c7d5df52..1ef68e2d3a 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -85,6 +85,8 @@ typedef struct efx_ev_ops_s {\n \tvoid\t\t(*eevo_qdestroy)(efx_evq_t *);\n \tefx_rc_t\t(*eevo_qprime)(efx_evq_t *, unsigned int);\n \tvoid\t\t(*eevo_qpost)(efx_evq_t *, uint16_t);\n+\tvoid\t\t(*eevo_qpoll)(efx_evq_t *, unsigned int *,\n+\t\t\t\t\tconst efx_ev_callbacks_t *, void *);\n \tefx_rc_t\t(*eevo_qmoderate)(efx_evq_t *, unsigned int);\n #if EFSYS_OPT_QSTATS\n \tvoid\t\t(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);\n", "prefixes": [ "v3", "03/60" ] }