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{
    "id": 78253,
    "url": "https://patches.dpdk.org/api/patches/78253/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600764594-14752-2-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1600764594-14752-2-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1600764594-14752-2-git-send-email-arybchenko@solarflare.com",
    "date": "2020-09-22T08:48:55",
    "name": "[01/60] common/sfc_efx/base: add EF100 registers definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "93c3f2ed310b2c3b70c4e248854a536770d7cb56",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600764594-14752-2-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [
        {
            "id": 12400,
            "url": "https://patches.dpdk.org/api/series/12400/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12400",
            "date": "2020-09-22T08:48:59",
            "name": "common/sfc_efx: support Riverhead NIC family",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/12400/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/78253/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/78253/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
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        ],
        "X-Virus-Scanned": "Proofpoint Essentials engine",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Tue, 22 Sep 2020 09:48:55 +0100",
        "Message-ID": "<1600764594-14752-2-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>",
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        "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003",
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        "X-MDID": "1600764613-xtDCpRf2B3Xm",
        "Subject": "[dpdk-dev] [PATCH 01/60] common/sfc_efx/base: add EF100 registers\n\tdefinitions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
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    },
    "content": "Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/common/sfc_efx/base/efx_impl.h       |   1 +\n drivers/common/sfc_efx/base/efx_regs_ef100.h | 934 +++++++++++++++++++\n 2 files changed, 935 insertions(+)\n create mode 100644 drivers/common/sfc_efx/base/efx_regs_ef100.h",
    "diff": "diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex 7d6a31d298..87c7d5df52 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -10,6 +10,7 @@\n #include \"efx.h\"\n #include \"efx_regs.h\"\n #include \"efx_regs_ef10.h\"\n+#include \"efx_regs_ef100.h\"\n #if EFSYS_OPT_MCDI\n #include \"efx_mcdi.h\"\n #endif\t/* EFSYS_OPT_MCDI */\ndiff --git a/drivers/common/sfc_efx/base/efx_regs_ef100.h b/drivers/common/sfc_efx/base/efx_regs_ef100.h\nnew file mode 100644\nindex 0000000000..1842150737\n--- /dev/null\n+++ b/drivers/common/sfc_efx/base/efx_regs_ef100.h\n@@ -0,0 +1,934 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ *\n+ * Copyright(c) 2019-2020 Xilinx, Inc.\n+ * Copyright(c) 2018-2019 Solarflare Communications Inc.\n+ */\n+\n+#ifndef\t_SYS_EFX_EF100_REGS_H\n+#define\t_SYS_EFX_EF100_REGS_H\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**************************************************************************\n+ * NOTE: the line below marks the start of the autogenerated section\n+ * EF100 registers and descriptors\n+ *\n+ **************************************************************************\n+ */\n+\n+/*\n+ * HW_REV_ID_REG(32bit):\n+ * Hardware revision info register\n+ */\n+\n+#define\tER_GZ_HW_REV_ID_REG_OFST 0x00000000\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_HW_REV_ID_REG_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * NIC_REV_ID(32bit):\n+ * SoftNIC revision info register\n+ */\n+\n+#define\tER_GZ_NIC_REV_ID_OFST 0x00000004\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_NIC_REV_ID_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * NIC_MAGIC(32bit):\n+ * Signature register that should contain a well-known value\n+ */\n+\n+#define\tER_GZ_NIC_MAGIC_OFST 0x00000008\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_NIC_MAGIC_RESET 0x0\n+\n+\n+#define\tERF_GZ_NIC_MAGIC_LBN 0\n+#define\tERF_GZ_NIC_MAGIC_WIDTH 32\n+#define\tEFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB\n+\n+\n+/*\n+ * MC_SFT_STATUS(32bit):\n+ * MC soft status\n+ */\n+\n+#define\tER_GZ_MC_SFT_STATUS_OFST 0x00000010\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_MC_SFT_STATUS_STEP 4\n+#define\tER_GZ_MC_SFT_STATUS_ROWS 2\n+#define\tER_GZ_MC_SFT_STATUS_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * MC_DB_LWRD_REG(32bit):\n+ * MC doorbell register, low word\n+ */\n+\n+#define\tER_GZ_MC_DB_LWRD_REG_OFST 0x00000020\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_MC_DB_LWRD_REG_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * MC_DB_HWRD_REG(32bit):\n+ * MC doorbell register, high word\n+ */\n+\n+#define\tER_GZ_MC_DB_HWRD_REG_OFST 0x00000024\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_MC_DB_HWRD_REG_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * EVQ_INT_PRIME(32bit):\n+ * Prime EVQ\n+ */\n+\n+#define\tER_GZ_EVQ_INT_PRIME_OFST 0x00000040\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_EVQ_INT_PRIME_RESET 0x0\n+\n+\n+#define\tERF_GZ_IDX_LBN 16\n+#define\tERF_GZ_IDX_WIDTH 16\n+#define\tERF_GZ_EVQ_ID_LBN 0\n+#define\tERF_GZ_EVQ_ID_WIDTH 16\n+\n+\n+/*\n+ * INT_AGG_RING_PRIME(32bit):\n+ * Prime interrupt aggregation ring.\n+ */\n+\n+#define\tER_GZ_INT_AGG_RING_PRIME_OFST 0x00000048\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_INT_AGG_RING_PRIME_RESET 0x0\n+\n+\n+/* defined as ERF_GZ_IDX_LBN 16; */\n+/* defined as ERF_GZ_IDX_WIDTH 16 */\n+#define\tERF_GZ_RING_ID_LBN 0\n+#define\tERF_GZ_RING_ID_WIDTH 16\n+\n+\n+/*\n+ * EVQ_TMR(32bit):\n+ * EVQ timer control\n+ */\n+\n+#define\tER_GZ_EVQ_TMR_OFST 0x00000104\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_EVQ_TMR_STEP 65536\n+#define\tER_GZ_EVQ_TMR_ROWS 1024\n+#define\tER_GZ_EVQ_TMR_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * EVQ_UNSOL_CREDIT_GRANT_SEQ(32bit):\n+ * Grant credits for unsolicited events.\n+ */\n+\n+#define\tER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_OFST 0x00000108\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536\n+#define\tER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024\n+#define\tER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * EVQ_DESC_CREDIT_GRANT_SEQ(32bit):\n+ * Grant credits for descriptor proxy events.\n+ */\n+\n+#define\tER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_OFST 0x00000110\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536\n+#define\tER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024\n+#define\tER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * RX_RING_DOORBELL(32bit):\n+ * Ring Rx doorbell.\n+ */\n+\n+#define\tER_GZ_RX_RING_DOORBELL_OFST 0x00000180\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_RX_RING_DOORBELL_STEP 65536\n+#define\tER_GZ_RX_RING_DOORBELL_ROWS 1024\n+#define\tER_GZ_RX_RING_DOORBELL_RESET 0x0\n+\n+\n+#define\tERF_GZ_RX_RING_PIDX_LBN 16\n+#define\tERF_GZ_RX_RING_PIDX_WIDTH 16\n+\n+\n+/*\n+ * TX_RING_DOORBELL(32bit):\n+ * Ring Tx doorbell.\n+ */\n+\n+#define\tER_GZ_TX_RING_DOORBELL_OFST 0x00000200\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_TX_RING_DOORBELL_STEP 65536\n+#define\tER_GZ_TX_RING_DOORBELL_ROWS 1024\n+#define\tER_GZ_TX_RING_DOORBELL_RESET 0x0\n+\n+\n+#define\tERF_GZ_TX_RING_PIDX_LBN 16\n+#define\tERF_GZ_TX_RING_PIDX_WIDTH 16\n+\n+\n+/*\n+ * TX_DESC_PUSH(128bit):\n+ * Tx ring descriptor push. Reserved for future use.\n+ */\n+\n+#define\tER_GZ_TX_DESC_PUSH_OFST 0x00000210\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_TX_DESC_PUSH_STEP 65536\n+#define\tER_GZ_TX_DESC_PUSH_ROWS 1024\n+#define\tER_GZ_TX_DESC_PUSH_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * THE_TIME(64bit):\n+ * NIC hardware time\n+ */\n+\n+#define\tER_GZ_THE_TIME_OFST 0x00000280\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_THE_TIME_STEP 65536\n+#define\tER_GZ_THE_TIME_ROWS 1024\n+#define\tER_GZ_THE_TIME_RESET 0x0\n+\n+\n+#define\tERF_GZ_THE_TIME_SECS_LBN 32\n+#define\tERF_GZ_THE_TIME_SECS_WIDTH 32\n+#define\tERF_GZ_THE_TIME_NANOS_LBN 2\n+#define\tERF_GZ_THE_TIME_NANOS_WIDTH 30\n+#define\tERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1\n+#define\tERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1\n+#define\tERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0\n+#define\tERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1\n+\n+\n+/*\n+ * PARAMS_TLV_LEN(32bit):\n+ * Size of design parameters area in bytes\n+ */\n+\n+#define\tER_GZ_PARAMS_TLV_LEN_OFST 0x00000c00\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_PARAMS_TLV_LEN_STEP 65536\n+#define\tER_GZ_PARAMS_TLV_LEN_ROWS 1024\n+#define\tER_GZ_PARAMS_TLV_LEN_RESET 0x0\n+\n+\n+\n+\n+/*\n+ * PARAMS_TLV(8160bit):\n+ * Design parameters\n+ */\n+\n+#define\tER_GZ_PARAMS_TLV_OFST 0x00000c04\n+/* rhead=rhead_host_regs */\n+#define\tER_GZ_PARAMS_TLV_STEP 65536\n+#define\tER_GZ_PARAMS_TLV_ROWS 1024\n+#define\tER_GZ_PARAMS_TLV_RESET 0x0\n+\n+\n+\n+\n+/* ES_EW_EMBEDDED_EVENT */\n+#define\tESF_GZ_EV_256_EVENT_DW0_LBN 0\n+#define\tESF_GZ_EV_256_EVENT_DW0_WIDTH 32\n+#define\tESF_GZ_EV_256_EVENT_DW1_LBN 32\n+#define\tESF_GZ_EV_256_EVENT_DW1_WIDTH 32\n+#define\tESF_GZ_EV_256_EVENT_LBN 0\n+#define\tESF_GZ_EV_256_EVENT_WIDTH 64\n+#define\tESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64\n+\n+\n+/* ES_NMMU_PAGESZ_2M_ADDR */\n+#define\tESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59\n+#define\tESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5\n+#define\tESE_GZ_NMMU_PAGE_SIZE_2M 9\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_DW0_LBN 21\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_DW0_WIDTH 32\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_DW1_LBN 53\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_DW1_WIDTH 6\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_LBN 21\n+#define\tESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38\n+#define\tESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0\n+#define\tESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21\n+#define\tESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64\n+\n+\n+/* ES_PARAM_TLV */\n+#define\tESF_GZ_TLV_VALUE_LBN 16\n+#define\tESF_GZ_TLV_VALUE_WIDTH 8\n+#define\tESE_GZ_TLV_VALUE_LENMIN 8\n+#define\tESE_GZ_TLV_VALUE_LENMAX 2040\n+#define\tESF_GZ_TLV_LEN_LBN 8\n+#define\tESF_GZ_TLV_LEN_WIDTH 8\n+#define\tESF_GZ_TLV_TYPE_LBN 0\n+#define\tESF_GZ_TLV_TYPE_WIDTH 8\n+#define\tESE_GZ_DP_NMMU_GROUP_SIZE 5\n+#define\tESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4\n+#define\tESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3\n+#define\tESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2\n+#define\tESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1\n+#define\tESE_GZ_DP_PAD 0\n+#define\tESE_GZ_PARAM_TLV_STRUCT_SIZE 24\n+\n+\n+/* ES_PCI_EXPRESS_XCAP_HDR */\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4\n+#define\tESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0\n+#define\tESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16\n+#define\tESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb\n+#define\tESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32\n+\n+\n+/* ES_RHEAD_BASE_EVENT */\n+#define\tESF_GZ_E_TYPE_LBN 60\n+#define\tESF_GZ_E_TYPE_WIDTH 4\n+#define\tESE_GZ_EF100_EV_DRIVER 5\n+#define\tESE_GZ_EF100_EV_MCDI 4\n+#define\tESE_GZ_EF100_EV_CONTROL 3\n+#define\tESE_GZ_EF100_EV_TX_TIMESTAMP 2\n+#define\tESE_GZ_EF100_EV_TX_COMPLETION 1\n+#define\tESE_GZ_EF100_EV_RX_PKTS 0\n+#define\tESF_GZ_EV_EVQ_PHASE_LBN 59\n+#define\tESF_GZ_EV_EVQ_PHASE_WIDTH 1\n+#define\tESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64\n+\n+\n+/* ES_RHEAD_EW_EVENT */\n+#define\tESF_GZ_EV_256_EV32_PHASE_LBN 255\n+#define\tESF_GZ_EV_256_EV32_PHASE_WIDTH 1\n+#define\tESF_GZ_EV_256_EV32_TYPE_LBN 251\n+#define\tESF_GZ_EV_256_EV32_TYPE_WIDTH 4\n+#define\tESE_GZ_EF100_EVEW_VIRTQ_DESC 2\n+#define\tESE_GZ_EF100_EVEW_TXQ_DESC 1\n+#define\tESE_GZ_EF100_EVEW_64BIT 0\n+#define\tESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256\n+\n+\n+/* ES_RX_DESC */\n+#define\tESF_GZ_RX_BUF_ADDR_DW0_LBN 0\n+#define\tESF_GZ_RX_BUF_ADDR_DW0_WIDTH 32\n+#define\tESF_GZ_RX_BUF_ADDR_DW1_LBN 32\n+#define\tESF_GZ_RX_BUF_ADDR_DW1_WIDTH 32\n+#define\tESF_GZ_RX_BUF_ADDR_LBN 0\n+#define\tESF_GZ_RX_BUF_ADDR_WIDTH 64\n+#define\tESE_GZ_RX_DESC_STRUCT_SIZE 64\n+\n+\n+/* ES_TXQ_DESC_PROXY_EVENT */\n+#define\tESF_GZ_EV_TXQ_DP_VI_ID_LBN 128\n+#define\tESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_LBN 0\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_WIDTH 32\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_LBN 32\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_WIDTH 32\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_LBN 64\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_WIDTH 32\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_LBN 96\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_WIDTH 32\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0\n+#define\tESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128\n+#define\tESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144\n+\n+\n+/* ES_TX_DESC_TYPE */\n+#define\tESF_GZ_TX_DESC_TYPE_LBN 124\n+#define\tESF_GZ_TX_DESC_TYPE_WIDTH 4\n+#define\tESE_GZ_TX_DESC_TYPE_DESC2CMPT 7\n+#define\tESE_GZ_TX_DESC_TYPE_MEM2MEM 4\n+#define\tESE_GZ_TX_DESC_TYPE_SEG 3\n+#define\tESE_GZ_TX_DESC_TYPE_TSO 2\n+#define\tESE_GZ_TX_DESC_TYPE_PREFIX 1\n+#define\tESE_GZ_TX_DESC_TYPE_SEND 0\n+#define\tESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128\n+\n+\n+/* ES_VIRTQ_DESC_PROXY_EVENT */\n+#define\tESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144\n+#define\tESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16\n+#define\tESF_GZ_EV_VQ_DP_VI_ID_LBN 128\n+#define\tESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_LBN 0\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_WIDTH 32\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_LBN 32\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_WIDTH 32\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_LBN 64\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_WIDTH 32\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_LBN 96\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_WIDTH 32\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0\n+#define\tESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128\n+#define\tESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160\n+\n+\n+/* ES_XIL_CFGBAR_TBL_ENTRY */\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_LBN 68\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_WIDTH 32\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_LBN 100\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_WIDTH 28\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60\n+#define\tESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4\n+#define\tESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67\n+#define\tESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29\n+#define\tESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68\n+#define\tESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28\n+#define\tESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67\n+#define\tESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1\n+#define\tESF_GZ_CFGBAR_EF100_BAR_LBN 64\n+#define\tESF_GZ_CFGBAR_EF100_BAR_WIDTH 3\n+#define\tESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7\n+#define\tESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6\n+#define\tESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64\n+#define\tESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3\n+#define\tESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7\n+#define\tESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6\n+#define\tESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32\n+#define\tESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32\n+#define\tESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12\n+#define\tESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8\n+#define\tESF_GZ_CFGBAR_ENTRY_LAST_LBN 28\n+#define\tESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1\n+#define\tESF_GZ_CFGBAR_ENTRY_REV_LBN 20\n+#define\tESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8\n+#define\tESE_GZ_CFGBAR_ENTRY_REV_EF100 0\n+#define\tESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0\n+#define\tESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20\n+#define\tESE_GZ_CFGBAR_ENTRY_LAST 0xfffff\n+#define\tESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe\n+#define\tESE_GZ_CFGBAR_ENTRY_EF100 0xef100\n+#define\tESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128\n+\n+\n+/* ES_XIL_CFGBAR_VSEC */\n+#define\tESF_GZ_VSEC_TBL_OFF_HI_LBN 64\n+#define\tESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32\n+#define\tESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32\n+#define\tESF_GZ_VSEC_TBL_OFF_LO_LBN 36\n+#define\tESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28\n+#define\tESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4\n+#define\tESF_GZ_VSEC_TBL_BAR_LBN 32\n+#define\tESF_GZ_VSEC_TBL_BAR_WIDTH 4\n+#define\tESE_GZ_VSEC_BAR_NUM_INVALID 7\n+#define\tESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6\n+#define\tESF_GZ_VSEC_LEN_LBN 20\n+#define\tESF_GZ_VSEC_LEN_WIDTH 12\n+#define\tESE_GZ_VSEC_LEN_HIGH_OFFT 16\n+#define\tESE_GZ_VSEC_LEN_MIN 12\n+#define\tESF_GZ_VSEC_VER_LBN 16\n+#define\tESF_GZ_VSEC_VER_WIDTH 4\n+#define\tESE_GZ_VSEC_VER_XIL_CFGBAR 0\n+#define\tESF_GZ_VSEC_ID_LBN 0\n+#define\tESF_GZ_VSEC_ID_WIDTH 16\n+#define\tESE_GZ_XILINX_VSEC_ID 0x20\n+#define\tESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96\n+\n+\n+/* ES_rh_egres_hclass */\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8\n+#define\tESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5\n+#define\tESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0\n+#define\tESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2\n+#define\tESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16\n+\n+\n+/* ES_sf_driver */\n+#define\tESF_GZ_DRIVER_E_TYPE_LBN 60\n+#define\tESF_GZ_DRIVER_E_TYPE_WIDTH 4\n+#define\tESF_GZ_DRIVER_PHASE_LBN 59\n+#define\tESF_GZ_DRIVER_PHASE_WIDTH 1\n+#define\tESF_GZ_DRIVER_DATA_DW0_LBN 0\n+#define\tESF_GZ_DRIVER_DATA_DW0_WIDTH 32\n+#define\tESF_GZ_DRIVER_DATA_DW1_LBN 32\n+#define\tESF_GZ_DRIVER_DATA_DW1_WIDTH 27\n+#define\tESF_GZ_DRIVER_DATA_LBN 0\n+#define\tESF_GZ_DRIVER_DATA_WIDTH 59\n+#define\tESE_GZ_SF_DRIVER_STRUCT_SIZE 64\n+\n+\n+/* ES_sf_ev_rsvd */\n+#define\tESF_GZ_EV_RSVD_TBD_NEXT_LBN 34\n+#define\tESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3\n+#define\tESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30\n+#define\tESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4\n+#define\tESF_GZ_EV_RSVD_SRC_QID_LBN 18\n+#define\tESF_GZ_EV_RSVD_SRC_QID_WIDTH 12\n+#define\tESF_GZ_EV_RSVD_SEQ_NUM_LBN 2\n+#define\tESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16\n+#define\tESF_GZ_EV_RSVD_TBD_LBN 0\n+#define\tESF_GZ_EV_RSVD_TBD_WIDTH 2\n+#define\tESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37\n+\n+\n+/* ES_sf_flush_evnt */\n+#define\tESF_GZ_EV_FLSH_E_TYPE_LBN 60\n+#define\tESF_GZ_EV_FLSH_E_TYPE_WIDTH 4\n+#define\tESF_GZ_EV_FLSH_PHASE_LBN 59\n+#define\tESF_GZ_EV_FLSH_PHASE_WIDTH 1\n+#define\tESF_GZ_EV_FLSH_SUB_TYPE_LBN 53\n+#define\tESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6\n+#define\tESF_GZ_EV_FLSH_RSVD_DW0_LBN 10\n+#define\tESF_GZ_EV_FLSH_RSVD_DW0_WIDTH 32\n+#define\tESF_GZ_EV_FLSH_RSVD_DW1_LBN 42\n+#define\tESF_GZ_EV_FLSH_RSVD_DW1_WIDTH 11\n+#define\tESF_GZ_EV_FLSH_RSVD_LBN 10\n+#define\tESF_GZ_EV_FLSH_RSVD_WIDTH 43\n+#define\tESF_GZ_EV_FLSH_LABEL_LBN 4\n+#define\tESF_GZ_EV_FLSH_LABEL_WIDTH 6\n+#define\tESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0\n+#define\tESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4\n+#define\tESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64\n+\n+\n+/* ES_sf_rx_pkts */\n+#define\tESF_GZ_EV_RXPKTS_E_TYPE_LBN 60\n+#define\tESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4\n+#define\tESF_GZ_EV_RXPKTS_PHASE_LBN 59\n+#define\tESF_GZ_EV_RXPKTS_PHASE_WIDTH 1\n+#define\tESF_GZ_EV_RXPKTS_RSVD_DW0_LBN 22\n+#define\tESF_GZ_EV_RXPKTS_RSVD_DW0_WIDTH 32\n+#define\tESF_GZ_EV_RXPKTS_RSVD_DW1_LBN 54\n+#define\tESF_GZ_EV_RXPKTS_RSVD_DW1_WIDTH 5\n+#define\tESF_GZ_EV_RXPKTS_RSVD_LBN 22\n+#define\tESF_GZ_EV_RXPKTS_RSVD_WIDTH 37\n+#define\tESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16\n+#define\tESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6\n+#define\tESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0\n+#define\tESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16\n+#define\tESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64\n+\n+\n+/* ES_sf_rx_prefix */\n+#define\tESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160\n+#define\tESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16\n+#define\tESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144\n+#define\tESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16\n+#define\tESF_GZ_RX_PREFIX_INGRESS_VPORT_LBN 128\n+#define\tESF_GZ_RX_PREFIX_INGRESS_VPORT_WIDTH 16\n+#define\tESF_GZ_RX_PREFIX_USER_MARK_LBN 96\n+#define\tESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32\n+#define\tESF_GZ_RX_PREFIX_RSS_HASH_LBN 64\n+#define\tESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32\n+#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 32\n+#define\tESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 32\n+#define\tESF_GZ_RX_PREFIX_CLASS_LBN 16\n+#define\tESF_GZ_RX_PREFIX_CLASS_WIDTH 16\n+#define\tESF_GZ_RX_PREFIX_USER_FLAG_LBN 15\n+#define\tESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14\n+#define\tESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1\n+#define\tESF_GZ_RX_PREFIX_LENGTH_LBN 0\n+#define\tESF_GZ_RX_PREFIX_LENGTH_WIDTH 14\n+#define\tESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176\n+\n+\n+/* ES_sf_rxtx_generic */\n+#define\tESF_GZ_EV_BARRIER_LBN 167\n+#define\tESF_GZ_EV_BARRIER_WIDTH 1\n+#define\tESF_GZ_EV_RSVD_DW0_LBN 130\n+#define\tESF_GZ_EV_RSVD_DW0_WIDTH 32\n+#define\tESF_GZ_EV_RSVD_DW1_LBN 162\n+#define\tESF_GZ_EV_RSVD_DW1_WIDTH 5\n+#define\tESF_GZ_EV_RSVD_LBN 130\n+#define\tESF_GZ_EV_RSVD_WIDTH 37\n+#define\tESF_GZ_EV_DPRXY_LBN 129\n+#define\tESF_GZ_EV_DPRXY_WIDTH 1\n+#define\tESF_GZ_EV_VIRTIO_LBN 128\n+#define\tESF_GZ_EV_VIRTIO_WIDTH 1\n+#define\tESF_GZ_EV_COUNT_DW0_LBN 0\n+#define\tESF_GZ_EV_COUNT_DW0_WIDTH 32\n+#define\tESF_GZ_EV_COUNT_DW1_LBN 32\n+#define\tESF_GZ_EV_COUNT_DW1_WIDTH 32\n+#define\tESF_GZ_EV_COUNT_DW2_LBN 64\n+#define\tESF_GZ_EV_COUNT_DW2_WIDTH 32\n+#define\tESF_GZ_EV_COUNT_DW3_LBN 96\n+#define\tESF_GZ_EV_COUNT_DW3_WIDTH 32\n+#define\tESF_GZ_EV_COUNT_LBN 0\n+#define\tESF_GZ_EV_COUNT_WIDTH 128\n+#define\tESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168\n+\n+\n+/* ES_sf_ts_stamp */\n+#define\tESF_GZ_EV_TS_E_TYPE_LBN 60\n+#define\tESF_GZ_EV_TS_E_TYPE_WIDTH 4\n+#define\tESF_GZ_EV_TS_PHASE_LBN 59\n+#define\tESF_GZ_EV_TS_PHASE_WIDTH 1\n+#define\tESF_GZ_EV_TS_RSVD_LBN 56\n+#define\tESF_GZ_EV_TS_RSVD_WIDTH 3\n+#define\tESF_GZ_EV_TS_STATUS_LBN 54\n+#define\tESF_GZ_EV_TS_STATUS_WIDTH 2\n+#define\tESF_GZ_EV_TS_Q_LABEL_LBN 48\n+#define\tESF_GZ_EV_TS_Q_LABEL_WIDTH 6\n+#define\tESF_GZ_EV_TS_DESC_ID_LBN 32\n+#define\tESF_GZ_EV_TS_DESC_ID_WIDTH 16\n+#define\tESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0\n+#define\tESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32\n+#define\tESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64\n+\n+\n+/* ES_sf_tx_cmplt */\n+#define\tESF_GZ_EV_TXCMPL_E_TYPE_LBN 60\n+#define\tESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4\n+#define\tESF_GZ_EV_TXCMPL_PHASE_LBN 59\n+#define\tESF_GZ_EV_TXCMPL_PHASE_WIDTH 1\n+#define\tESF_GZ_EV_TXCMPL_RSVD_DW0_LBN 22\n+#define\tESF_GZ_EV_TXCMPL_RSVD_DW0_WIDTH 32\n+#define\tESF_GZ_EV_TXCMPL_RSVD_DW1_LBN 54\n+#define\tESF_GZ_EV_TXCMPL_RSVD_DW1_WIDTH 5\n+#define\tESF_GZ_EV_TXCMPL_RSVD_LBN 22\n+#define\tESF_GZ_EV_TXCMPL_RSVD_WIDTH 37\n+#define\tESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16\n+#define\tESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6\n+#define\tESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0\n+#define\tESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16\n+#define\tESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64\n+\n+\n+/* ES_sf_tx_desc2cmpt_dsc_fmt */\n+#define\tESF_GZ_D2C_TGT_VI_ID_LBN 108\n+#define\tESF_GZ_D2C_TGT_VI_ID_WIDTH 16\n+#define\tESF_GZ_D2C_CMPT2_LBN 107\n+#define\tESF_GZ_D2C_CMPT2_WIDTH 1\n+#define\tESF_GZ_D2C_ABS_VI_ID_LBN 106\n+#define\tESF_GZ_D2C_ABS_VI_ID_WIDTH 1\n+#define\tESF_GZ_D2C_ORDERED_LBN 105\n+#define\tESF_GZ_D2C_ORDERED_WIDTH 1\n+#define\tESF_GZ_D2C_SKIP_N_LBN 97\n+#define\tESF_GZ_D2C_SKIP_N_WIDTH 8\n+#define\tESF_GZ_D2C_RSVD_DW0_LBN 64\n+#define\tESF_GZ_D2C_RSVD_DW0_WIDTH 32\n+#define\tESF_GZ_D2C_RSVD_DW1_LBN 96\n+#define\tESF_GZ_D2C_RSVD_DW1_WIDTH 1\n+#define\tESF_GZ_D2C_RSVD_LBN 64\n+#define\tESF_GZ_D2C_RSVD_WIDTH 33\n+#define\tESF_GZ_D2C_COMPLETION_DW0_LBN 0\n+#define\tESF_GZ_D2C_COMPLETION_DW0_WIDTH 32\n+#define\tESF_GZ_D2C_COMPLETION_DW1_LBN 32\n+#define\tESF_GZ_D2C_COMPLETION_DW1_WIDTH 32\n+#define\tESF_GZ_D2C_COMPLETION_LBN 0\n+#define\tESF_GZ_D2C_COMPLETION_WIDTH 64\n+#define\tESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+/* ES_sf_tx_mem2mem_dsc_fmt */\n+#define\tESF_GZ_M2M_ADDR_SPC_EN_LBN 123\n+#define\tESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1\n+#define\tESF_GZ_M2M_TRANSLATE_ADDR_LBN 122\n+#define\tESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1\n+#define\tESF_GZ_M2M_RSVD_LBN 120\n+#define\tESF_GZ_M2M_RSVD_WIDTH 2\n+#define\tESF_GZ_M2M_ADDR_SPC_LBN 108\n+#define\tESF_GZ_M2M_ADDR_SPC_WIDTH 12\n+#define\tESF_GZ_M2M_ADDR_SPC_PASID_LBN 86\n+#define\tESF_GZ_M2M_ADDR_SPC_PASID_WIDTH 22\n+#define\tESF_GZ_M2M_ADDR_SPC_MODE_LBN 84\n+#define\tESF_GZ_M2M_ADDR_SPC_MODE_WIDTH 2\n+#define\tESF_GZ_M2M_LEN_MINUS_1_LBN 64\n+#define\tESF_GZ_M2M_LEN_MINUS_1_WIDTH 20\n+#define\tESF_GZ_M2M_ADDR_DW0_LBN 0\n+#define\tESF_GZ_M2M_ADDR_DW0_WIDTH 32\n+#define\tESF_GZ_M2M_ADDR_DW1_LBN 32\n+#define\tESF_GZ_M2M_ADDR_DW1_WIDTH 32\n+#define\tESF_GZ_M2M_ADDR_LBN 0\n+#define\tESF_GZ_M2M_ADDR_WIDTH 64\n+#define\tESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+/* ES_sf_tx_ovr_dsc_fmt */\n+#define\tESF_GZ_TX_PREFIX_MARK_EN_LBN 123\n+#define\tESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1\n+#define\tESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122\n+#define\tESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1\n+#define\tESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121\n+#define\tESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1\n+#define\tESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120\n+#define\tESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1\n+#define\tESF_GZ_TX_PREFIX_RSRVD_DW0_LBN 64\n+#define\tESF_GZ_TX_PREFIX_RSRVD_DW0_WIDTH 32\n+#define\tESF_GZ_TX_PREFIX_RSRVD_DW1_LBN 96\n+#define\tESF_GZ_TX_PREFIX_RSRVD_DW1_WIDTH 24\n+#define\tESF_GZ_TX_PREFIX_RSRVD_LBN 64\n+#define\tESF_GZ_TX_PREFIX_RSRVD_WIDTH 56\n+#define\tESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48\n+#define\tESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16\n+#define\tESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32\n+#define\tESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16\n+#define\tESF_GZ_TX_PREFIX_MARK_LBN 0\n+#define\tESF_GZ_TX_PREFIX_MARK_WIDTH 32\n+#define\tESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+/* ES_sf_tx_seg_dsc_fmt */\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1\n+#define\tESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122\n+#define\tESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1\n+#define\tESF_GZ_TX_SEG_RSVD2_LBN 120\n+#define\tESF_GZ_TX_SEG_RSVD2_WIDTH 2\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_LBN 108\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_WIDTH 12\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_PASID_LBN 86\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_PASID_WIDTH 22\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_MODE_LBN 84\n+#define\tESF_GZ_TX_SEG_ADDR_SPC_MODE_WIDTH 2\n+#define\tESF_GZ_TX_SEG_RSVD_LBN 80\n+#define\tESF_GZ_TX_SEG_RSVD_WIDTH 4\n+#define\tESF_GZ_TX_SEG_LEN_LBN 64\n+#define\tESF_GZ_TX_SEG_LEN_WIDTH 16\n+#define\tESF_GZ_TX_SEG_ADDR_DW0_LBN 0\n+#define\tESF_GZ_TX_SEG_ADDR_DW0_WIDTH 32\n+#define\tESF_GZ_TX_SEG_ADDR_DW1_LBN 32\n+#define\tESF_GZ_TX_SEG_ADDR_DW1_WIDTH 32\n+#define\tESF_GZ_TX_SEG_ADDR_LBN 0\n+#define\tESF_GZ_TX_SEG_ADDR_WIDTH 64\n+#define\tESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+/* ES_sf_tx_std_dsc_fmt */\n+#define\tESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108\n+#define\tESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16\n+#define\tESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107\n+#define\tESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1\n+#define\tESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106\n+#define\tESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1\n+#define\tESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105\n+#define\tESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1\n+#define\tESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104\n+#define\tESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1\n+#define\tESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101\n+#define\tESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3\n+#define\tESF_GZ_TX_SEND_RSVD_LBN 99\n+#define\tESF_GZ_TX_SEND_RSVD_WIDTH 2\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83\n+#define\tESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9\n+#define\tESF_GZ_TX_SEND_NUM_SEGS_LBN 78\n+#define\tESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5\n+#define\tESF_GZ_TX_SEND_LEN_LBN 64\n+#define\tESF_GZ_TX_SEND_LEN_WIDTH 14\n+#define\tESF_GZ_TX_SEND_ADDR_DW0_LBN 0\n+#define\tESF_GZ_TX_SEND_ADDR_DW0_WIDTH 32\n+#define\tESF_GZ_TX_SEND_ADDR_DW1_LBN 32\n+#define\tESF_GZ_TX_SEND_ADDR_DW1_WIDTH 32\n+#define\tESF_GZ_TX_SEND_ADDR_LBN 0\n+#define\tESF_GZ_TX_SEND_ADDR_WIDTH 64\n+#define\tESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+/* ES_sf_tx_tso_dsc_fmt */\n+#define\tESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108\n+#define\tESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16\n+#define\tESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107\n+#define\tESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1\n+#define\tESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106\n+#define\tESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1\n+#define\tESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105\n+#define\tESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1\n+#define\tESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104\n+#define\tESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1\n+#define\tESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101\n+#define\tESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3\n+#define\tESF_GZ_TX_TSO_RSVD_LBN 94\n+#define\tESF_GZ_TX_TSO_RSVD_WIDTH 7\n+#define\tESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93\n+#define\tESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1\n+#define\tESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85\n+#define\tESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8\n+#define\tESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77\n+#define\tESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8\n+#define\tESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69\n+#define\tESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8\n+#define\tESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64\n+#define\tESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5\n+#define\tESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42\n+#define\tESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22\n+#define\tESF_GZ_TX_TSO_HDR_LEN_W_LBN 34\n+#define\tESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8\n+#define\tESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33\n+#define\tESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1\n+#define\tESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32\n+#define\tESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1\n+#define\tESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31\n+#define\tESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1\n+#define\tESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29\n+#define\tESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2\n+#define\tESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27\n+#define\tESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2\n+#define\tESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17\n+#define\tESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10\n+#define\tESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14\n+#define\tESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3\n+#define\tESF_GZ_TX_TSO_MSS_LBN 0\n+#define\tESF_GZ_TX_TSO_MSS_WIDTH 14\n+#define\tESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124\n+\n+\n+\n+/* Enum DESIGN_PARAMS */\n+#define\tESE_EF100_DP_GZ_RX_MAX_RUNT 17\n+#define\tESE_EF100_DP_GZ_VI_STRIDES 16\n+#define\tESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15\n+#define\tESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14\n+#define\tESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13\n+#define\tESE_EF100_DP_GZ_COMPAT 12\n+#define\tESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11\n+#define\tESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10\n+#define\tESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9\n+#define\tESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8\n+#define\tESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7\n+#define\tESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6\n+#define\tESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5\n+#define\tESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4\n+#define\tESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3\n+#define\tESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2\n+#define\tESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1\n+#define\tESE_EF100_DP_GZ_PAD 0\n+\n+/* Enum DESIGN_PARAM_DEFAULTS */\n+#define\tESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff\n+#define\tESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192\n+#define\tESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192\n+#define\tESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106\n+#define\tESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff\n+#define\tESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640\n+#define\tESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512\n+#define\tESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512\n+#define\tESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192\n+#define\tESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64\n+#define\tESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64\n+#define\tESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32\n+#define\tESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16\n+#define\tESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7\n+#define\tESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4\n+#define\tESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2\n+#define\tESE_EF100_DP_GZ_COMPAT_DEFAULT 0\n+\n+/* Enum HOST_IF_CONSTANTS */\n+#define\tESE_GZ_FCW_LEN 0x4C\n+#define\tESE_GZ_RX_PKT_PREFIX_LEN 22\n+\n+/* Enum PCI_CONSTANTS */\n+#define\tESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256\n+#define\tESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4\n+\n+/* Enum RH_HCLASS_L2_CLASS */\n+#define\tESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1\n+#define\tESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0\n+\n+/* Enum RH_HCLASS_L2_STATUS */\n+#define\tESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3\n+#define\tESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2\n+#define\tESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1\n+#define\tESE_GZ_RH_HCLASS_L2_STATUS_OK 0\n+\n+/* Enum RH_HCLASS_L3_CLASS */\n+#define\tESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3\n+#define\tESE_GZ_RH_HCLASS_L3_CLASS_IP6 2\n+#define\tESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1\n+#define\tESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0\n+\n+/* Enum RH_HCLASS_L4_CLASS */\n+#define\tESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3\n+#define\tESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2\n+#define\tESE_GZ_RH_HCLASS_L4_CLASS_UDP 1\n+#define\tESE_GZ_RH_HCLASS_L4_CLASS_TCP 0\n+\n+/* Enum RH_HCLASS_L4_CSUM */\n+#define\tESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1\n+#define\tESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0\n+\n+/* Enum RH_HCLASS_TUNNEL_CLASS */\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1\n+#define\tESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0\n+\n+/* Enum TX_DESC_CSO_PARTIAL_EN */\n+#define\tESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2\n+#define\tESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1\n+#define\tESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0\n+\n+/* Enum TX_DESC_CS_INNER_L3 */\n+#define\tESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3\n+#define\tESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2\n+#define\tESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1\n+#define\tESE_GZ_TX_DESC_CS_INNER_L3_OFF 0\n+\n+/* Enum TX_DESC_IP4_ID */\n+#define\tESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2\n+#define\tESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1\n+#define\tESE_GZ_TX_DESC_IP4_ID_NO_OP 0\n+/*************************************************************************\n+ * NOTE: the comment line above marks the end of the autogenerated section\n+ */\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif /* _SYS_EFX_EF100_REGS_H */\n",
    "prefixes": [
        "01/60"
    ]
}