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GET /api/patches/77823/?format=api
{ "id": 77823, "url": "https://patches.dpdk.org/api/patches/77823/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200916031002.42122-2-junyux.jiang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200916031002.42122-2-junyux.jiang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200916031002.42122-2-junyux.jiang@intel.com", "date": "2020-09-16T03:09:58", "name": "[v3,1/5] net/ice: support flex Rx descriptor RxDID #22", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fcaad903080c5908e9e1654ae1c0e5d527ac24ce", "submitter": { "id": 1408, "url": "https://patches.dpdk.org/api/people/1408/?format=api", "name": "Junyu Jiang", "email": "junyux.jiang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200916031002.42122-2-junyux.jiang@intel.com/mbox/", "series": [ { "id": 12253, "url": "https://patches.dpdk.org/api/series/12253/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12253", "date": "2020-09-16T03:09:57", "name": "supports RxDID #22 and FDID", "version": 3, "mbox": "https://patches.dpdk.org/series/12253/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/77823/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/77823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2D915A04C7;\n\tWed, 16 Sep 2020 05:27:28 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 349FD1C115;\n\tWed, 16 Sep 2020 05:27:27 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 06B731C115\n for <dev@dpdk.org>; Wed, 16 Sep 2020 05:27:23 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Sep 2020 20:27:23 -0700", "from unknown (HELO intel.sh.intel.com) ([10.239.255.60])\n by orsmga002.jf.intel.com with ESMTP; 15 Sep 2020 20:27:19 -0700" ], "IronPort-SDR": [ "\n tceVrreBYRFuT4G7iwD6HFUbEwUYComf2AIqIUuVDX0aE/aRuJ2DjuTCXo43XdcVFVQK6JrNmO\n iPbH6j8N7DKw==", "\n aP55yzy+yGDoxKU+Bycn7yMaXj30AsHQ7dW+u4RVEbyt8CW9bHb3EncJA32rmsm4ZL/9Iira/7\n 5KvvN1ycAu2A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9745\"; a=\"147143644\"", "E=Sophos;i=\"5.76,431,1592895600\"; d=\"scan'208\";a=\"147143644\"", "E=Sophos;i=\"5.76,431,1592895600\"; d=\"scan'208\";a=\"319692310\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Junyu Jiang <junyux.jiang@intel.com>", "To": "dev@dpdk.org", "Cc": "Leyi Rong <leyi.rong@intel.com>, Qi Zhang <qi.z.zhang@intel.com>,\n Qiming Yang <qiming.yang@intel.com>, Guinan Sun <guinanx.sun@intel.com>,\n Junyu Jiang <junyux.jiang@intel.com>", "Date": "Wed, 16 Sep 2020 03:09:58 +0000", "Message-Id": "<20200916031002.42122-2-junyux.jiang@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200916031002.42122-1-junyux.jiang@intel.com>", "References": "<20200826075501.50052-1-guinanx.sun@intel.com>\n <20200916031002.42122-1-junyux.jiang@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/5] net/ice: support flex Rx descriptor RxDID\n\t#22", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch supports RxDID #22 by the following changes:\n-add structure and macro definition for RxDID #22.\n-support RxDID #22 format in normal path.\n-change RSS hash parsing from RxDID #22 in AVX/SSE data path.\n\nSigned-off-by: Junyu Jiang <junyux.jiang@intel.com>\n---\n drivers/net/ice/ice_ethdev.c | 20 ++++++\n drivers/net/ice/ice_ethdev.h | 4 ++\n drivers/net/ice/ice_rxtx.c | 23 ++++---\n drivers/net/ice/ice_rxtx.h | 42 +++++++++++++\n drivers/net/ice/ice_rxtx_vec_avx2.c | 98 +++++++++++++++++++++++++++--\n drivers/net/ice/ice_rxtx_vec_sse.c | 89 +++++++++++++++++++++-----\n 6 files changed, 249 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex c42581ea7..097b72023 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2147,6 +2147,24 @@ ice_rss_ctx_init(struct ice_pf *pf)\n \tICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);\n }\n \n+static uint64_t\n+ice_get_supported_rxdid(struct ice_hw *hw)\n+{\n+\tuint64_t supported_rxdid = 0; /* bitmap for supported RXDID */\n+\tuint32_t regval;\n+\tint i;\n+\n+\tsupported_rxdid |= BIT(ICE_RXDID_LEGACY_1);\n+\n+\tfor (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {\n+\t\tregval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));\n+\t\tif ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)\n+\t\t\t& GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)\n+\t\t\tsupported_rxdid |= BIT(i);\n+\t}\n+\treturn supported_rxdid;\n+}\n+\n static int\n ice_dev_init(struct rte_eth_dev *dev)\n {\n@@ -2298,6 +2316,8 @@ ice_dev_init(struct rte_eth_dev *dev)\n \t\treturn ret;\n \t}\n \n+\tpf->supported_rxdid = ice_get_supported_rxdid(hw);\n+\n \treturn 0;\n \n err_pf_setup:\ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 243a023e6..e8c9971fb 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -136,6 +136,9 @@\n #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)\n #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)\n \n+/* Max number of flexible descriptor rxdid */\n+#define ICE_FLEX_DESC_RXDID_MAX_NUM 64\n+\n /* DDP package type */\n enum ice_pkg_type {\n \tICE_PKG_TYPE_UNKNOWN,\n@@ -435,6 +438,7 @@ struct ice_pf {\n \tbool init_link_up;\n \tuint64_t old_rx_bytes;\n \tuint64_t old_tx_bytes;\n+\tuint64_t supported_rxdid; /* bitmap for supported RXDID */\n };\n \n #define ICE_MAX_QUEUE_NUM 2048\ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex fecb13459..fef6ad454 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -63,7 +63,7 @@ static inline uint8_t\n ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)\n {\n \tstatic uint8_t rxdid_map[] = {\n-\t\t[PROTO_XTR_NONE] = ICE_RXDID_COMMS_GENERIC,\n+\t\t[PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,\n \t\t[PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,\n \t\t[PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,\n \t\t[PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,\n@@ -73,7 +73,7 @@ ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)\n \t};\n \n \treturn xtr_type < RTE_DIM(rxdid_map) ?\n-\t\t\t\trxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;\n+\t\t\t\trxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;\n }\n \n static enum ice_status\n@@ -81,12 +81,13 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq)\n {\n \tstruct ice_vsi *vsi = rxq->vsi;\n \tstruct ice_hw *hw = ICE_VSI_TO_HW(vsi);\n+\tstruct ice_pf *pf = ICE_VSI_TO_PF(vsi);\n \tstruct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);\n \tstruct ice_rlan_ctx rx_ctx;\n \tenum ice_status err;\n \tuint16_t buf_size, len;\n \tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n-\tuint32_t rxdid = ICE_RXDID_COMMS_GENERIC;\n+\tuint32_t rxdid = ICE_RXDID_COMMS_OVS;\n \tuint32_t regval;\n \n \t/* Set buffer size as the head split is disabled. */\n@@ -151,6 +152,12 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq)\n \tPMD_DRV_LOG(DEBUG, \"Port (%u) - Rx queue (%u) is set with RXDID : %u\",\n \t\t rxq->port_id, rxq->queue_id, rxdid);\n \n+\tif (!(pf->supported_rxdid & BIT(rxdid))) {\n+\t\tPMD_DRV_LOG(ERR, \"currently package doesn't support RXDID (%u)\",\n+\t\t\t rxdid);\n+\t\treturn -EINVAL;\n+\t}\n+\n \t/* Enable Flexible Descriptors in the queue context which\n \t * allows this driver to select a specific receive descriptor format\n \t */\n@@ -1338,7 +1345,7 @@ ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)\n \n static void\n ice_rxd_to_proto_xtr(struct rte_mbuf *mb,\n-\t\t volatile struct ice_32b_rx_flex_desc_comms *desc)\n+\t\t volatile struct ice_32b_rx_flex_desc_comms_ovs *desc)\n {\n \tuint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);\n \tuint32_t metadata = 0;\n@@ -1376,8 +1383,9 @@ static inline void\n ice_rxd_to_pkt_fields(struct rte_mbuf *mb,\n \t\t volatile union ice_rx_flex_desc *rxdp)\n {\n-\tvolatile struct ice_32b_rx_flex_desc_comms *desc =\n-\t\t\t(volatile struct ice_32b_rx_flex_desc_comms *)rxdp;\n+\tvolatile struct ice_32b_rx_flex_desc_comms_ovs *desc =\n+\t\t\t(volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n \tuint16_t stat_err;\n \n \tstat_err = rte_le_to_cpu_16(desc->status_error0);\n@@ -1385,13 +1393,14 @@ ice_rxd_to_pkt_fields(struct rte_mbuf *mb,\n \t\tmb->ol_flags |= PKT_RX_RSS_HASH;\n \t\tmb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);\n \t}\n+#endif\n \n-#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n \tif (desc->flow_id != 0xFFFFFFFF) {\n \t\tmb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;\n \t\tmb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);\n \t}\n \n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n \tif (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))\n \t\tice_rxd_to_proto_xtr(mb, desc);\n #endif\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nindex 2fdcfb7d0..e21ba152d 100644\n--- a/drivers/net/ice/ice_rxtx.h\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -38,6 +38,8 @@\n \n #define ICE_FDIR_PKT_LEN\t512\n \n+#define ICE_RXDID_COMMS_OVS\t22\n+\n typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);\n typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq);\n \n@@ -135,6 +137,46 @@ union ice_tx_offload {\n \t};\n };\n \n+/* Rx Flex Descriptor for Comms Package Profile\n+ * RxDID Profile ID 22 (swap Hash and FlowID)\n+ * Flex-field 0: Flow ID lower 16-bits\n+ * Flex-field 1: Flow ID upper 16-bits\n+ * Flex-field 2: RSS hash lower 16-bits\n+ * Flex-field 3: RSS hash upper 16-bits\n+ * Flex-field 4: AUX0\n+ * Flex-field 5: AUX1\n+ */\n+struct ice_32b_rx_flex_desc_comms_ovs {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le32 flow_id;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flexi_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 rss_hash;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 aux0;\n+\t\t\t__le16 aux1;\n+\t\t} flex;\n+\t\t__le32 ts_high;\n+\t} flex_ts;\n+};\n+\n int ice_rx_queue_setup(struct rte_eth_dev *dev,\n \t\t uint16_t queue_idx,\n \t\t uint16_t nb_desc,\ndiff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c\nindex be50677c2..07d129e3f 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx2.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c\n@@ -191,8 +191,8 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \tconst __m256i shuf_msk =\n \t\t_mm256_set_epi8\n \t\t\t(/* first descriptor */\n-\t\t\t 15, 14,\n-\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n \t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n \t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n \t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n@@ -200,8 +200,8 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n \t\t\t 0xFF, 0xFF,\t/*pkt_type set as unknown */\n \t\t\t /* second descriptor */\n-\t\t\t 15, 14,\n-\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n \t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n \t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n \t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n@@ -461,6 +461,96 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* merge flags */\n \t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n \t\t\t\trss_vlan_flags);\n+\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\t\t/**\n+\t\t * needs to load 2nd 16B of each desc for RSS hash parsing,\n+\t\t * will cause performance drop to get into this context.\n+\t\t */\n+\t\tif (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &\n+\t\t\t\tDEV_RX_OFFLOAD_RSS_HASH) {\n+\t\t\t/* load bottom half of every 32B desc */\n+\t\t\tconst __m128i raw_desc_bh7 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[7].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh6 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[6].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh5 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[5].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh4 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[4].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh3 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[3].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh2 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[2].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh1 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[1].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh0 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[0].wb.status_error1));\n+\n+\t\t\t__m256i raw_desc_bh6_7 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh6),\n+\t\t\t\t\traw_desc_bh7, 1);\n+\t\t\t__m256i raw_desc_bh4_5 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh4),\n+\t\t\t\t\traw_desc_bh5, 1);\n+\t\t\t__m256i raw_desc_bh2_3 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh2),\n+\t\t\t\t\traw_desc_bh3, 1);\n+\t\t\t__m256i raw_desc_bh0_1 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh0),\n+\t\t\t\t\traw_desc_bh1, 1);\n+\n+\t\t\t/**\n+\t\t\t * to shift the 32b RSS hash value to the\n+\t\t\t * highest 32b of each 128b before mask\n+\t\t\t */\n+\t\t\t__m256i rss_hash6_7 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh6_7, 32);\n+\t\t\t__m256i rss_hash4_5 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh4_5, 32);\n+\t\t\t__m256i rss_hash2_3 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh2_3, 32);\n+\t\t\t__m256i rss_hash0_1 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh0_1, 32);\n+\n+\t\t\t__m256i rss_hash_msk =\n+\t\t\t\t_mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,\n+\t\t\t\t\t\t 0xFFFFFFFF, 0, 0, 0);\n+\n+\t\t\trss_hash6_7 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash6_7, rss_hash_msk);\n+\t\t\trss_hash4_5 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash4_5, rss_hash_msk);\n+\t\t\trss_hash2_3 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash2_3, rss_hash_msk);\n+\t\t\trss_hash0_1 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash0_1, rss_hash_msk);\n+\n+\t\t\tmb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);\n+\t\t\tmb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);\n+\t\t\tmb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);\n+\t\t\tmb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);\n+\t\t} /* if() on RSS hash parsing */\n+#endif\n \t\t/**\n \t\t * At this point, we have the 8 sets of flags in the low 16-bits\n \t\t * of each 32-bit value in vlan0.\ndiff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c\nindex 382ef31f3..fffb27138 100644\n--- a/drivers/net/ice/ice_rxtx_vec_sse.c\n+++ b/drivers/net/ice/ice_rxtx_vec_sse.c\n@@ -230,7 +230,8 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \tconst __m128i zero = _mm_setzero_si128();\n \t/* mask to shuffle from desc. to mbuf */\n \tconst __m128i shuf_msk = _mm_set_epi8\n-\t\t\t(15, 14, 13, 12, /* octet 12~15, 32 bits rss */\n+\t\t\t(0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF, /* rss hash parsed separately */\n \t\t\t 11, 10, /* octet 10~11, 16 bits vlan_macip */\n \t\t\t 5, 4, /* octet 4~5, 16 bits data_len */\n \t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n@@ -321,7 +322,7 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t pos += ICE_DESCS_PER_LOOP,\n \t rxdp += ICE_DESCS_PER_LOOP) {\n \t\t__m128i descs[ICE_DESCS_PER_LOOP];\n-\t\t__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;\n+\t\t__m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;\n \t\t__m128i staterr, sterr_tmp1, sterr_tmp2;\n \t\t/* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */\n \t\t__m128i mbp1;\n@@ -367,8 +368,12 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\trte_compiler_barrier();\n \n \t\t/* D.1 pkt 3,4 convert format from desc to pktmbuf */\n-\t\tpkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);\n-\t\tpkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);\n+\t\tpkt_mb3 = _mm_shuffle_epi8(descs[3], shuf_msk);\n+\t\tpkt_mb2 = _mm_shuffle_epi8(descs[2], shuf_msk);\n+\n+\t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\n+\t\tpkt_mb1 = _mm_shuffle_epi8(descs[1], shuf_msk);\n+\t\tpkt_mb0 = _mm_shuffle_epi8(descs[0], shuf_msk);\n \n \t\t/* C.1 4=>2 filter staterr info only */\n \t\tsterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);\n@@ -378,12 +383,68 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\tice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);\n \n \t\t/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */\n-\t\tpkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);\n \t\tpkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);\n+\t\tpkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);\n \n-\t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\n-\t\tpkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);\n-\t\tpkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);\n+\t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n+\t\tpkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);\n+\t\tpkt_mb0 = _mm_add_epi16(pkt_mb0, crc_adjust);\n+\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\t\t/**\n+\t\t * needs to load 2nd 16B of each desc for RSS hash parsing,\n+\t\t * will cause performance drop to get into this context.\n+\t\t */\n+\t\tif (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &\n+\t\t\t\tDEV_RX_OFFLOAD_RSS_HASH) {\n+\t\t\t/* load bottom half of every 32B desc */\n+\t\t\tconst __m128i raw_desc_bh3 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[3].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh2 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[2].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh1 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[1].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh0 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[0].wb.status_error1));\n+\n+\t\t\t/**\n+\t\t\t * to shift the 32b RSS hash value to the\n+\t\t\t * highest 32b of each 128b before mask\n+\t\t\t */\n+\t\t\t__m128i rss_hash3 =\n+\t\t\t\t_mm_slli_epi64(raw_desc_bh3, 32);\n+\t\t\t__m128i rss_hash2 =\n+\t\t\t\t_mm_slli_epi64(raw_desc_bh2, 32);\n+\t\t\t__m128i rss_hash1 =\n+\t\t\t\t_mm_slli_epi64(raw_desc_bh1, 32);\n+\t\t\t__m128i rss_hash0 =\n+\t\t\t\t_mm_slli_epi64(raw_desc_bh0, 32);\n+\n+\t\t\t__m128i rss_hash_msk =\n+\t\t\t\t_mm_set_epi32(0xFFFFFFFF, 0, 0, 0);\n+\n+\t\t\trss_hash3 = _mm_and_si128\n+\t\t\t\t\t(rss_hash3, rss_hash_msk);\n+\t\t\trss_hash2 = _mm_and_si128\n+\t\t\t\t\t(rss_hash2, rss_hash_msk);\n+\t\t\trss_hash1 = _mm_and_si128\n+\t\t\t\t\t(rss_hash1, rss_hash_msk);\n+\t\t\trss_hash0 = _mm_and_si128\n+\t\t\t\t\t(rss_hash0, rss_hash_msk);\n+\n+\t\t\tpkt_mb3 = _mm_or_si128(pkt_mb3, rss_hash3);\n+\t\t\tpkt_mb2 = _mm_or_si128(pkt_mb2, rss_hash2);\n+\t\t\tpkt_mb1 = _mm_or_si128(pkt_mb1, rss_hash1);\n+\t\t\tpkt_mb0 = _mm_or_si128(pkt_mb0, rss_hash0);\n+\t\t} /* if() on RSS hash parsing */\n+#endif\n \n \t\t/* C.2 get 4 pkts staterr value */\n \t\tstaterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);\n@@ -391,14 +452,10 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* D.3 copy final 3,4 data to rx_pkts */\n \t\t_mm_storeu_si128\n \t\t\t((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,\n-\t\t\t pkt_mb4);\n+\t\t\t pkt_mb3);\n \t\t_mm_storeu_si128\n \t\t\t((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,\n-\t\t\t pkt_mb3);\n-\n-\t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n-\t\tpkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);\n-\t\tpkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);\n+\t\t\t pkt_mb2);\n \n \t\t/* C* extract and record EOP bit */\n \t\tif (split_packet) {\n@@ -422,9 +479,9 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* D.3 copy final 1,2 data to rx_pkts */\n \t\t_mm_storeu_si128\n \t\t\t((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,\n-\t\t\t pkt_mb2);\n+\t\t\t pkt_mb1);\n \t\t_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n-\t\t\t\t pkt_mb1);\n+\t\t\t\t pkt_mb0);\n \t\tice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \t\t/* C.4 calc avaialbe number of desc */\n \t\tvar = __builtin_popcountll(_mm_cvtsi128_si64(staterr));\n", "prefixes": [ "v3", "1/5" ] }