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GET /api/patches/77769/?format=api
{ "id": 77769, "url": "https://patches.dpdk.org/api/patches/77769/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200915165025.543-8-konstantin.ananyev@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200915165025.543-8-konstantin.ananyev@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200915165025.543-8-konstantin.ananyev@intel.com", "date": "2020-09-15T16:50:20", "name": "[v2,07/12] acl: add infrastructure to support AVX512 classify", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bc91086839f4124536b3c1868c01123e2ecc4267", "submitter": { "id": 33, "url": "https://patches.dpdk.org/api/people/33/?format=api", "name": "Ananyev, Konstantin", "email": "konstantin.ananyev@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200915165025.543-8-konstantin.ananyev@intel.com/mbox/", "series": [ { "id": 12241, "url": "https://patches.dpdk.org/api/series/12241/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12241", "date": "2020-09-15T16:50:13", "name": "acl: introduce AVX512 classify method", "version": 2, "mbox": "https://patches.dpdk.org/series/12241/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/77769/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/77769/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0B5CBA04C7;\n\tTue, 15 Sep 2020 18:52:04 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 03F501C1A8;\n\tTue, 15 Sep 2020 18:51:13 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 535BC1C1A0\n for <dev@dpdk.org>; Tue, 15 Sep 2020 18:51:11 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Sep 2020 09:51:10 -0700", "from sivswdev08.ir.intel.com ([10.237.217.47])\n by orsmga006.jf.intel.com with ESMTP; 15 Sep 2020 09:51:09 -0700" ], "IronPort-SDR": [ "\n bWo8IzCot8JTPu4n4u12MLVulQalTRB0aQdAjVFmDGjFH9MKVPUS63y3a9+mj1ZukVYASugnvO\n u3BGSqinegTA==", "\n PlgVQtPV52o/7RXMrkaVIzfUL6MWk4jXrO2r52h3ZPd3h726kqALs2qWiJ04oM9zme3A0oNr19\n wm0chjuTNcAA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9745\"; a=\"139311001\"", "E=Sophos;i=\"5.76,430,1592895600\"; d=\"scan'208\";a=\"139311001\"", "E=Sophos;i=\"5.76,430,1592895600\"; d=\"scan'208\";a=\"306709448\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Konstantin Ananyev <konstantin.ananyev@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, ruifeng.wang@arm.com, vladimir.medvedkin@intel.com,\n Konstantin Ananyev <konstantin.ananyev@intel.com>", "Date": "Tue, 15 Sep 2020 17:50:20 +0100", "Message-Id": "<20200915165025.543-8-konstantin.ananyev@intel.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20200915165025.543-1-konstantin.ananyev@intel.com>", "References": "<20200807162829.11690-1-konstantin.ananyev@intel.com>\n <20200915165025.543-1-konstantin.ananyev@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 07/12] acl: add infrastructure to support\n\tAVX512 classify", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add necessary changes to support new AVX512 specific ACL classify\nalgorithm:\n - changes in meson.build to check that build tools\n (compiler, assembler, etc.) do properly support AVX512.\n - run-time checks to make sure target platform does support AVX512.\n - dummy rte_acl_classify_avx512() for targets where AVX512\n implementation couldn't be properly supported.\n\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n config/x86/meson.build | 3 ++-\n lib/librte_acl/acl.h | 4 ++++\n lib/librte_acl/acl_run_avx512.c | 17 ++++++++++++++\n lib/librte_acl/meson.build | 39 +++++++++++++++++++++++++++++++++\n lib/librte_acl/rte_acl.c | 29 ++++++++++++++++++++++++\n lib/librte_acl/rte_acl.h | 1 +\n 6 files changed, 92 insertions(+), 1 deletion(-)\n create mode 100644 lib/librte_acl/acl_run_avx512.c", "diff": "diff --git a/config/x86/meson.build b/config/x86/meson.build\nindex 6ec020ef6..c5626e914 100644\n--- a/config/x86/meson.build\n+++ b/config/x86/meson.build\n@@ -23,7 +23,8 @@ foreach f:base_flags\n endforeach\n \n optional_flags = ['AES', 'PCLMUL',\n-\t\t'AVX', 'AVX2', 'AVX512F',\n+\t\t'AVX', 'AVX2',\n+\t\t'AVX512F', 'AVX512VL', 'AVX512CD', 'AVX512BW',\n \t\t'RDRND', 'RDSEED']\n foreach f:optional_flags\n \tif cc.get_define('__@0@__'.format(f), args: machine_args) == '1'\ndiff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h\nindex 39d45a0c2..2022cf253 100644\n--- a/lib/librte_acl/acl.h\n+++ b/lib/librte_acl/acl.h\n@@ -201,6 +201,10 @@ int\n rte_acl_classify_avx2(const struct rte_acl_ctx *ctx, const uint8_t **data,\n \tuint32_t *results, uint32_t num, uint32_t categories);\n \n+int\n+rte_acl_classify_avx512(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\tuint32_t *results, uint32_t num, uint32_t categories);\n+\n int\n rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,\n \tuint32_t *results, uint32_t num, uint32_t categories);\ndiff --git a/lib/librte_acl/acl_run_avx512.c b/lib/librte_acl/acl_run_avx512.c\nnew file mode 100644\nindex 000000000..67274989d\n--- /dev/null\n+++ b/lib/librte_acl/acl_run_avx512.c\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include \"acl_run_sse.h\"\n+\n+int\n+rte_acl_classify_avx512(const struct rte_acl_ctx *ctx, const uint8_t **data,\n+\tuint32_t *results, uint32_t num, uint32_t categories)\n+{\n+\tif (num >= MAX_SEARCHES_SSE8)\n+\t\treturn search_sse_8(ctx, data, results, num, categories);\n+\tif (num >= MAX_SEARCHES_SSE4)\n+\t\treturn search_sse_4(ctx, data, results, num, categories);\n+\n+\treturn rte_acl_classify_scalar(ctx, data, results, num, categories);\n+}\ndiff --git a/lib/librte_acl/meson.build b/lib/librte_acl/meson.build\nindex d1e2c184c..b2fd61cad 100644\n--- a/lib/librte_acl/meson.build\n+++ b/lib/librte_acl/meson.build\n@@ -27,6 +27,45 @@ if dpdk_conf.has('RTE_ARCH_X86')\n \t\tcflags += '-DCC_AVX2_SUPPORT'\n \tendif\n \n+\t# compile AVX512 version if:\n+\t# we are building 64-bit binary AND binutils can generate proper code\n+\n+\tif dpdk_conf.has('RTE_ARCH_X86_64') and binutils_ok.returncode() == 0\n+\n+\t\t# compile AVX512 version if either:\n+\t\t# a. we have AVX512 supported in minimum instruction set\n+\t\t# baseline\n+\t\t# b. it's not minimum instruction set, but supported by\n+\t\t# compiler\n+\t\t#\n+\t\t# in former case, just add avx512 C file to files list\n+\t\t# in latter case, compile c file to static lib, using correct\n+\t\t# compiler flags, and then have the .o file from static lib\n+\t\t# linked into main lib.\n+\n+\t\tif dpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512F') and \\\n+\t\t\tdpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512VL') and \\\n+\t\t\tdpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512CD') and \\\n+\t\t\tdpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512BW')\n+\n+\t\t\tsources += files('acl_run_avx512.c')\n+\t\t\tcflags += '-DCC_AVX512_SUPPORT'\n+\n+\t\telif cc.has_multi_arguments('-mavx512f', '-mavx512vl',\n+\t\t\t\t\t'-mavx512cd', '-mavx512bw')\n+\n+\t\t\tavx512_tmplib = static_library('avx512_tmp',\n+\t\t\t\t'acl_run_avx512.c',\n+\t\t\t\tdependencies: static_rte_eal,\n+\t\t\t\tc_args: cflags +\n+\t\t\t\t\t['-mavx512f', '-mavx512vl',\n+\t\t\t\t\t '-mavx512cd', '-mavx512bw'])\n+\t\t\tobjs += avx512_tmplib.extract_objects(\n+\t\t\t\t\t'acl_run_avx512.c')\n+\t\t\tcflags += '-DCC_AVX512_SUPPORT'\n+\t\tendif\n+\tendif\n+\n elif dpdk_conf.has('RTE_ARCH_ARM') or dpdk_conf.has('RTE_ARCH_ARM64')\n \tcflags += '-flax-vector-conversions'\n \tsources += files('acl_run_neon.c')\ndiff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex fbcf45fdc..fdcb7a798 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -16,6 +16,22 @@ static struct rte_tailq_elem rte_acl_tailq = {\n };\n EAL_REGISTER_TAILQ(rte_acl_tailq)\n \n+#ifndef CC_AVX512_SUPPORT\n+/*\n+ * If the compiler doesn't support AVX512 instructions,\n+ * then the dummy one would be used instead for AVX512 classify method.\n+ */\n+int\n+rte_acl_classify_avx512(__rte_unused const struct rte_acl_ctx *ctx,\n+\t__rte_unused const uint8_t **data,\n+\t__rte_unused uint32_t *results,\n+\t__rte_unused uint32_t num,\n+\t__rte_unused uint32_t categories)\n+{\n+\treturn -ENOTSUP;\n+}\n+#endif\n+\n #ifndef CC_AVX2_SUPPORT\n /*\n * If the compiler doesn't support AVX2 instructions,\n@@ -77,6 +93,7 @@ static const rte_acl_classify_t classify_fns[] = {\n \t[RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,\n \t[RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,\n \t[RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,\n+\t[RTE_ACL_CLASSIFY_AVX512] = rte_acl_classify_avx512,\n };\n \n /*\n@@ -126,6 +143,17 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n static int\n acl_check_alg_x86(enum rte_acl_classify_alg alg)\n {\n+\tif (alg == RTE_ACL_CLASSIFY_AVX512) {\n+#ifdef CC_AVX512_SUPPORT\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW))\n+\t\t\treturn 0;\n+#endif\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif (alg == RTE_ACL_CLASSIFY_AVX2) {\n #ifdef CC_AVX2_SUPPORT\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n@@ -159,6 +187,7 @@ acl_check_alg(enum rte_acl_classify_alg alg)\n \t\treturn acl_check_alg_arm(alg);\n \tcase RTE_ACL_CLASSIFY_ALTIVEC:\n \t\treturn acl_check_alg_ppc(alg);\n+\tcase RTE_ACL_CLASSIFY_AVX512:\n \tcase RTE_ACL_CLASSIFY_AVX2:\n \tcase RTE_ACL_CLASSIFY_SSE:\n \t\treturn acl_check_alg_x86(alg);\ndiff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h\nindex 3999f15de..d243a1c84 100644\n--- a/lib/librte_acl/rte_acl.h\n+++ b/lib/librte_acl/rte_acl.h\n@@ -241,6 +241,7 @@ enum rte_acl_classify_alg {\n \tRTE_ACL_CLASSIFY_AVX2 = 3, /**< requires AVX2 support. */\n \tRTE_ACL_CLASSIFY_NEON = 4, /**< requires NEON support. */\n \tRTE_ACL_CLASSIFY_ALTIVEC = 5, /**< requires ALTIVEC support. */\n+\tRTE_ACL_CLASSIFY_AVX512 = 6, /**< requires AVX512 support. */\n };\n \n /**\n", "prefixes": [ "v2", "07/12" ] }