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{
    "id": 7758,
    "url": "https://patches.dpdk.org/api/patches/7758/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1445321912-1484-2-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1445321912-1484-2-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1445321912-1484-2-git-send-email-helin.zhang@intel.com",
    "date": "2015-10-20T06:18:31",
    "name": "[dpdk-dev,v2,1/2] i40e: add selecting GRE key length",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "9c6d11af65122434b40330358a7bef0ec1cba46b",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1445321912-1484-2-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/7758/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/7758/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id A0E088E8B;\n\tTue, 20 Oct 2015 08:18:46 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id CBD5A8E80\n\tfor <dev@dpdk.org>; Tue, 20 Oct 2015 08:18:43 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 19 Oct 2015 23:18:44 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 19 Oct 2015 23:18:41 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9K6Idtc029251;\n\tTue, 20 Oct 2015 14:18:39 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9K6IaGi001526; Tue, 20 Oct 2015 14:18:38 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9K6IZqI001521; \n\tTue, 20 Oct 2015 14:18:35 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.17,706,1437462000\"; d=\"scan'208\";a=\"797700540\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue, 20 Oct 2015 14:18:31 +0800",
        "Message-Id": "<1445321912-1484-2-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1445321912-1484-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1443078979-20774-1-git-send-email-helin.zhang@intel.com>\n\t<1445321912-1484-1-git-send-email-helin.zhang@intel.com>",
        "Cc": "yulong.pei@intel.com",
        "Subject": "[dpdk-dev] [PATCH v2 1/2] i40e: add selecting GRE key length",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "By default, only first 3 bytes of GRE key will be used for hash or\nFD calculation. With these changes, it can select 3 or 4 bytes of\nGRE key for hash or FD calculation.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nSigned-off-by: Andrey Chilikin <andrey.chilikin@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c  | 87 +++++++++++++++++++++++++++++++++++++++--\n lib/librte_ether/rte_eth_ctrl.h | 20 ++++++++++\n 2 files changed, 104 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 9bf7898..8cca74b 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -5333,7 +5333,7 @@ i40e_pf_config_rss(struct i40e_pf *pf)\n \n static int\n i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n-\t\t\tstruct rte_eth_tunnel_filter_conf *filter)\n+\t\t\t       struct rte_eth_tunnel_filter_conf *filter)\n {\n \tif (pf == NULL || filter == NULL) {\n \t\tPMD_DRV_LOG(ERR, \"Invalid parameter\");\n@@ -5365,9 +5365,85 @@ i40e_tunnel_filter_param_check(struct i40e_pf *pf,\n \treturn 0;\n }\n \n+#define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000\n+#define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))\n static int\n-i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n-\t\t\tvoid *arg)\n+i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)\n+{\n+\tuint32_t val, reg;\n+\tint ret = -EINVAL;\n+\n+\tval = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));\n+\tPMD_DRV_LOG(DEBUG, \"Read original GL_PRS_FVBM with 0x%08x\\n\", val);\n+\n+\tif (len == 3) {\n+\t\treg = val | I40E_GL_PRS_FVBM_MSK_ENA;\n+\t} else if (len == 4) {\n+\t\treg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported GRE key length of %u\", len);\n+\t\treturn ret;\n+\t}\n+\n+\tif (reg != val) {\n+\t\tret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),\n+\t\t\t\t\t\t   reg, NULL);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t} else {\n+\t\tret = 0;\n+\t}\n+\tPMD_DRV_LOG(DEBUG, \"Read modified GL_PRS_FVBM with 0x%08x\\n\",\n+\t\t    I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)\n+{\n+\tint ret = -EINVAL;\n+\n+\tif (!hw || !cfg)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cfg->cfg_type) {\n+\tcase RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:\n+\t\tret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Unknown config type %u\", cfg->cfg_type);\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,\n+\t\t\t       enum rte_filter_op filter_op,\n+\t\t\t       void *arg)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret = I40E_ERR_PARAM;\n+\n+\tswitch (filter_op) {\n+\tcase RTE_ETH_FILTER_SET:\n+\t\tret = i40e_dev_global_config_set(hw,\n+\t\t\t(struct rte_eth_global_cfg *)arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown operation %u\", filter_op);\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_tunnel_filter_handle(struct rte_eth_dev *dev,\n+\t\t\t  enum rte_filter_op filter_op,\n+\t\t\t  void *arg)\n {\n \tstruct rte_eth_tunnel_filter_conf *filter;\n \tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n@@ -5382,6 +5458,7 @@ i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n \tcase RTE_ETH_FILTER_NOP:\n \t\tif (!(pf->flags & I40E_FLAG_VXLAN))\n \t\t\tret = I40E_NOT_SUPPORTED;\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_ADD:\n \t\tret = i40e_dev_tunnel_filter_set(pf, filter, 1);\n \t\tbreak;\n@@ -6392,6 +6469,10 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \n \tswitch (filter_type) {\n+\tcase RTE_ETH_FILTER_NONE:\n+\t\t/* For global configuration */\n+\t\tret = i40e_filter_ctrl_global_config(dev, filter_op, arg);\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_HASH:\n \t\tret = i40e_hash_filter_ctrl(dev, filter_op, arg);\n \t\tbreak;\ndiff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h\nindex 4ba86ee..d02a68e 100644\n--- a/lib/librte_ether/rte_eth_ctrl.h\n+++ b/lib/librte_ether/rte_eth_ctrl.h\n@@ -295,6 +295,26 @@ struct rte_eth_tunnel_filter_conf {\n \tuint16_t queue_id;      /** < queue number. */\n };\n \n+/**\n+ * Global eth device configuration type.\n+ */\n+enum rte_eth_global_cfg_type {\n+\tRTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,\n+\tRTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,\n+\tRTE_ETH_GLOBAL_CFG_TYPE_MAX,\n+};\n+\n+/**\n+ * Global eth device configuration.\n+ */\n+struct rte_eth_global_cfg {\n+\tenum rte_eth_global_cfg_type cfg_type; /**< Global config type. */\n+\tunion {\n+\t\tuint8_t gre_key_len; /**< Valid GRE key length in byte. */\n+\t\tuint64_t reserved; /**< Reserve space for future use. */\n+\t} cfg;\n+};\n+\n #define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */\n #define RTE_ETH_INSET_SIZE_MAX   128 /** < Max length of input set. */\n \n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "1/2"
    ]
}