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GET /api/patches/7708/?format=api
{ "id": 7708, "url": "https://patches.dpdk.org/api/patches/7708/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1445000741-12799-2-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1445000741-12799-2-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1445000741-12799-2-git-send-email-wenzhuo.lu@intel.com", "date": "2015-10-16T13:05:38", "name": "[dpdk-dev,v2,1/4] ixgbe: 512 entries RSS table on x550", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "307b0755edece8c0904c8a471ffd8677c9402480", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1445000741-12799-2-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7708/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7708/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 30B488E56;\n\tFri, 16 Oct 2015 15:05:53 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 9C6148DAE\n\tfor <dev@dpdk.org>; Fri, 16 Oct 2015 15:05:51 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga103.jf.intel.com with ESMTP; 16 Oct 2015 06:05:50 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 16 Oct 2015 06:05:50 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9GD5m5S026105;\n\tFri, 16 Oct 2015 21:05:48 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9GD5js1012841; Fri, 16 Oct 2015 21:05:47 +0800", "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9GD5j4n012837; \n\tFri, 16 Oct 2015 21:05:45 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,689,1437462000\"; d=\"scan'208\";a=\"665699042\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 16 Oct 2015 21:05:38 +0800", "Message-Id": "<1445000741-12799-2-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1445000741-12799-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1443426751-4906-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1445000741-12799-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 1/4] ixgbe: 512 entries RSS table on x550", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Comparing with the older NICs, x550's RSS redirection table is enlarged to 512\nentries. As the original code is for the NICs which have a 128 entries RSS table,\nit means only part of the RSS table is set on x550. So, RSS cannot work as\nexpected on x550, it doesn't redirect the packets evenly.\nThis patch configs the entries beyond 128 on x550 to let RSS work well, and also\nupdate the query and update functions to support 512 entries.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 57 +++++++++++++++++++++++++++++++++-------\n drivers/net/ixgbe/ixgbe_ethdev.h | 4 +++\n drivers/net/ixgbe/ixgbe_rxtx.c | 10 +++++--\n 3 files changed, 60 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex ec2918c..480891d 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -2397,7 +2397,7 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n \t};\n \tdev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);\n-\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n+\tdev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);\n \tdev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;\n }\n \n@@ -3203,12 +3203,15 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \tuint32_t reta, r;\n \tuint16_t idx, shift;\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t sp_reta_size;\n+\tuint32_t reta_reg;\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\tsp_reta_size = ixgbe_reta_size_get(hw->mac.type);\n+\tif (reta_size != sp_reta_size) {\n \t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n \t\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\t\t\"(%d)\\n\", reta_size, sp_reta_size);\n \t\treturn -EINVAL;\n \t}\n \n@@ -3219,10 +3222,11 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \t\t\t\t\t\tIXGBE_4_BIT_MASK);\n \t\tif (!mask)\n \t\t\tcontinue;\n+\t\treta_reg = ixgbe_reta_reg_get(hw->mac.type, i);\n \t\tif (mask == IXGBE_4_BIT_MASK)\n \t\t\tr = 0;\n \t\telse\n-\t\t\tr = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n+\t\t\tr = IXGBE_READ_REG(hw, reta_reg);\n \t\tfor (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n \t\t\tif (mask & (0x1 << j))\n \t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n@@ -3231,7 +3235,7 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \t\t\t\treta |= r & (IXGBE_8_BIT_MASK <<\n \t\t\t\t\t\t(CHAR_BIT * j));\n \t\t}\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);\n+\t\tIXGBE_WRITE_REG(hw, reta_reg, reta);\n \t}\n \n \treturn 0;\n@@ -3246,16 +3250,19 @@ ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n \tuint32_t reta;\n \tuint16_t idx, shift;\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t sp_reta_size;\n+\tuint32_t reta_reg;\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\tsp_reta_size = ixgbe_reta_size_get(hw->mac.type);\n+\tif (reta_size != sp_reta_size) {\n \t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n \t\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\t\t\"(%d)\\n\", reta_size, sp_reta_size);\n \t\treturn -EINVAL;\n \t}\n \n-\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {\n+\tfor (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {\n \t\tidx = i / RTE_RETA_GROUP_SIZE;\n \t\tshift = i % RTE_RETA_GROUP_SIZE;\n \t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n@@ -3263,7 +3270,8 @@ ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n \t\tif (!mask)\n \t\t\tcontinue;\n \n-\t\treta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n+\t\treta_reg = ixgbe_reta_reg_get(hw->mac.type, i);\n+\t\treta = IXGBE_READ_REG(hw, reta_reg);\n \t\tfor (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n \t\t\tif (mask & (0x1 << j))\n \t\t\t\treta_conf[idx].reta[shift + j] =\n@@ -5473,6 +5481,37 @@ ixgbe_set_eeprom(struct rte_eth_dev *dev,\n \treturn eeprom->ops.write_buffer(hw, first, length, data);\n }\n \n+uint16_t\n+ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {\n+\tswitch (mac_type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\treturn ETH_RSS_RETA_SIZE_512;\n+\tcase ixgbe_mac_X550_vf:\n+\tcase ixgbe_mac_X550EM_x_vf:\n+\t\treturn ETH_RSS_RETA_SIZE_64;\n+\tdefault:\n+\t\treturn ETH_RSS_RETA_SIZE_128;\n+\t}\n+}\n+\n+uint32_t\n+ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {\n+\tswitch (mac_type) {\n+\tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_X550EM_x:\n+\t\tif (reta_idx < ETH_RSS_RETA_SIZE_128)\n+\t\t\treturn IXGBE_RETA(reta_idx >> 2);\n+\t\telse\n+\t\t\treturn IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);\n+\tcase ixgbe_mac_X550_vf:\n+\tcase ixgbe_mac_X550EM_x_vf:\n+\t\treturn IXGBE_VFRETA(reta_idx >> 2);\n+\tdefault:\n+\t\treturn IXGBE_RETA(reta_idx >> 2);\n+\t}\n+}\n+\n static struct rte_driver rte_ixgbe_driver = {\n \t.type = PMD_PDEV,\n \t.init = rte_ixgbe_pmd_init,\ndiff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h\nindex c3d4f4f..0c669cd 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.h\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.h\n@@ -377,6 +377,10 @@ int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,\n int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n \n+uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);\n+\n+uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);\n+\n /*\n * Flow director function prototypes\n */\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex a598a72..494a6be 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2793,22 +2793,28 @@ ixgbe_rss_configure(struct rte_eth_dev *dev)\n \tuint32_t reta;\n \tuint16_t i;\n \tuint16_t j;\n+\tuint16_t sp_reta_size;\n+\tuint32_t reta_reg;\n \n \tPMD_INIT_FUNC_TRACE();\n \thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n+\tsp_reta_size = ixgbe_reta_size_get(hw->mac.type);\n+\n \t/*\n \t * Fill in redirection table\n \t * The byte-swap is needed because NIC registers are in\n \t * little-endian order.\n \t */\n \treta = 0;\n-\tfor (i = 0, j = 0; i < 128; i++, j++) {\n+\tfor (i = 0, j = 0; i < sp_reta_size; i++, j++) {\n+\t\treta_reg = ixgbe_reta_reg_get(hw->mac.type, i);\n+\n \t\tif (j == dev->data->nb_rx_queues)\n \t\t\tj = 0;\n \t\treta = (reta << 8) | j;\n \t\tif ((i & 3) == 3)\n-\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),\n+\t\t\tIXGBE_WRITE_REG(hw, reta_reg,\n \t\t\t\t\trte_bswap32(reta));\n \t}\n \n", "prefixes": [ "dpdk-dev", "v2", "1/4" ] }