get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/76113/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 76113,
    "url": "https://patches.dpdk.org/api/patches/76113/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200827161304.32300-18-ciara.power@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200827161304.32300-18-ciara.power@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200827161304.32300-18-ciara.power@intel.com",
    "date": "2020-08-27T16:13:04",
    "name": "[v2,17/17] net: add checks for max SIMD bitwidth",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "938e31c58adfee2cda6bfdca62afaf6f17ec1a93",
    "submitter": {
        "id": 978,
        "url": "https://patches.dpdk.org/api/people/978/?format=api",
        "name": "Power, Ciara",
        "email": "ciara.power@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200827161304.32300-18-ciara.power@intel.com/mbox/",
    "series": [
        {
            "id": 11831,
            "url": "https://patches.dpdk.org/api/series/11831/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11831",
            "date": "2020-08-27T16:12:47",
            "name": "add max SIMD bitwidth to EAL",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/11831/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/76113/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/76113/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C952A04B1;\n\tThu, 27 Aug 2020 18:16:42 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 47C2A1C1A5;\n\tThu, 27 Aug 2020 18:14:02 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 0E0451C0AF\n for <dev@dpdk.org>; Thu, 27 Aug 2020 18:13:43 +0200 (CEST)",
            "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Aug 2020 09:13:42 -0700",
            "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga007.fm.intel.com with ESMTP; 27 Aug 2020 09:13:41 -0700"
        ],
        "IronPort-SDR": [
            "\n 6ZriZ5tpS8y35gBVms1zB0tyNTqcgwV6rItNeiRQd11+P8tpY99yKjkTpZ+m/ojfqB4bAeWZah\n aiCj8erkPP5g==",
            "\n 6GlkRZUth5iAoXjjDeVVKZ5slXkZ7NHWovn+j9BYrgzWLMnAmpiPaZk0xKPIm2R/Qad+Y+EkAQ\n gs4nm6k8flIA=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9726\"; a=\"220767065\"",
            "E=Sophos;i=\"5.76,360,1592895600\"; d=\"scan'208\";a=\"220767065\"",
            "E=Sophos;i=\"5.76,360,1592895600\"; d=\"scan'208\";a=\"280681637\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Ciara Power <ciara.power@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Ciara Power <ciara.power@intel.com>,\n Jasvinder Singh <jasvinder.singh@intel.com>,\n Olivier Matz <olivier.matz@6wind.com>",
        "Date": "Thu, 27 Aug 2020 17:13:04 +0100",
        "Message-Id": "<20200827161304.32300-18-ciara.power@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200827161304.32300-1-ciara.power@intel.com>",
        "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20200827161304.32300-1-ciara.power@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 17/17] net: add checks for max SIMD bitwidth",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath. This check is done just before the handler is called, it cannot\nbe done when setting the handlers initially as the EAL max simd bitwidth\nvalue has not yet been set.\n\nCc: Jasvinder Singh <jasvinder.singh@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\n lib/librte_net/rte_net_crc.c | 8 ++++++++\n 1 file changed, 8 insertions(+)",
    "diff": "diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c\nindex 9fd4794a9d..d3d3206919 100644\n--- a/lib/librte_net/rte_net_crc.c\n+++ b/lib/librte_net/rte_net_crc.c\n@@ -9,6 +9,7 @@\n #include <rte_cpuflags.h>\n #include <rte_common.h>\n #include <rte_net_crc.h>\n+#include <rte_eal.h>\n \n #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)\n #define X86_64_SSE42_PCLMULQDQ     1\n@@ -60,6 +61,8 @@ static rte_net_crc_handler handlers_neon[] = {\n };\n #endif\n \n+static uint16_t max_simd_bitwidth;\n+\n /**\n  * Reflect the bits about the middle\n  *\n@@ -175,6 +178,11 @@ rte_net_crc_calc(const void *data,\n \tuint32_t ret;\n \trte_net_crc_handler f_handle;\n \n+\tif (max_simd_bitwidth == 0)\n+\t\tmax_simd_bitwidth = rte_get_max_simd_bitwidth();\n+\tif (max_simd_bitwidth < RTE_MAX_128_SIMD &&\n+\t\t\thandlers != handlers_scalar)\n+\t\trte_net_crc_set_alg(RTE_NET_CRC_SCALAR);\n \tf_handle = handlers[type];\n \tret = f_handle(data, data_len);\n \n",
    "prefixes": [
        "v2",
        "17/17"
    ]
}