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{
    "id": 74720,
    "url": "https://patches.dpdk.org/api/patches/74720/",
    "web_url": "https://patches.dpdk.org/patch/74720/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200724053235.71069-11-ajit.khaparde@broadcom.com>",
    "date": "2020-07-24T05:32:23",
    "name": "[v3,10/22] net/bnxt: add egress template with VLAN tag match",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b5760819f54bb7f25db08c70de02aa8920891962",
    "submitter": {
        "id": 501,
        "url": "https://patches.dpdk.org/api/people/501/",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/patch/74720/mbox/",
    "series": [
        {
            "id": 11269,
            "url": "https://patches.dpdk.org/api/series/11269/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11269",
            "date": "2020-07-24T05:32:13",
            "name": "bnxt patches",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/11269/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74720/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74720/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
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        "References": "<20200723115639.22357-1-somnath.kotur@broadcom.com>\n <20200724053235.71069-1-ajit.khaparde@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH v3 10/22] net/bnxt: add egress template with VLAN\n\ttag match",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3D746A0518;\n\tFri, 24 Jul 2020 07:34:40 +0200 (CEST)",
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        ],
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        "Date": "Thu, 23 Jul 2020 22:32:23 -0700",
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        "X-Received": "by 2002:a67:7002:: with SMTP id l2mr6557453vsc.67.1595568802336;\n Thu, 23 Jul 2020 22:33:22 -0700 (PDT)",
        "To": "dev@dpdk.org",
        "X-Relaying-Domain": "broadcom.com",
        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "In-Reply-To": "<20200724053235.71069-1-ajit.khaparde@broadcom.com>",
        "Cc": "ferruh.yigit@intel.com,\n Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Shahaji Bhosle <shahaji.bhosle@broadcom.com>",
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        "Message-Id": "<20200724053235.71069-11-ajit.khaparde@broadcom.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nAdded egress template with VLAN tag match\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nReviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>\n---\n .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 501 +++++++++++++++++-\n .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |  28 +-\n 2 files changed, 509 insertions(+), 20 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\nindex 330c5ecdd..41d1d8772 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n@@ -162,7 +162,31 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n \t[BNXT_ULP_CLASS_HID_01d1] = 151,\n \t[BNXT_ULP_CLASS_HID_0319] = 152,\n \t[BNXT_ULP_CLASS_HID_01cd] = 153,\n-\t[BNXT_ULP_CLASS_HID_0305] = 154\n+\t[BNXT_ULP_CLASS_HID_0305] = 154,\n+\t[BNXT_ULP_CLASS_HID_01e2] = 155,\n+\t[BNXT_ULP_CLASS_HID_032a] = 156,\n+\t[BNXT_ULP_CLASS_HID_0650] = 157,\n+\t[BNXT_ULP_CLASS_HID_0198] = 158,\n+\t[BNXT_ULP_CLASS_HID_01de] = 159,\n+\t[BNXT_ULP_CLASS_HID_0316] = 160,\n+\t[BNXT_ULP_CLASS_HID_066c] = 161,\n+\t[BNXT_ULP_CLASS_HID_01a4] = 162,\n+\t[BNXT_ULP_CLASS_HID_01c2] = 163,\n+\t[BNXT_ULP_CLASS_HID_030a] = 164,\n+\t[BNXT_ULP_CLASS_HID_0670] = 165,\n+\t[BNXT_ULP_CLASS_HID_01b8] = 166,\n+\t[BNXT_ULP_CLASS_HID_003e] = 167,\n+\t[BNXT_ULP_CLASS_HID_02f6] = 168,\n+\t[BNXT_ULP_CLASS_HID_078c] = 169,\n+\t[BNXT_ULP_CLASS_HID_0044] = 170,\n+\t[BNXT_ULP_CLASS_HID_01d2] = 171,\n+\t[BNXT_ULP_CLASS_HID_031a] = 172,\n+\t[BNXT_ULP_CLASS_HID_0660] = 173,\n+\t[BNXT_ULP_CLASS_HID_01a8] = 174,\n+\t[BNXT_ULP_CLASS_HID_01ce] = 175,\n+\t[BNXT_ULP_CLASS_HID_0306] = 176,\n+\t[BNXT_ULP_CLASS_HID_067c] = 177,\n+\t[BNXT_ULP_CLASS_HID_01b4] = 178\n };\n \n struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n@@ -2833,6 +2857,382 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t.class_tid = 21,\n \t.wc_pri = 11\n+\t},\n+\t[155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01e2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 12\n+\t},\n+\t[156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_032a,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 13\n+\t},\n+\t[157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0650,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 14\n+\t},\n+\t[158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0198,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 15\n+\t},\n+\t[159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01de,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 16\n+\t},\n+\t[160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0316,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 17\n+\t},\n+\t[161] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_066c,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 18\n+\t},\n+\t[162] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01a4,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 19\n+\t},\n+\t[163] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01c2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 20\n+\t},\n+\t[164] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_030a,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 21\n+\t},\n+\t[165] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0670,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 22\n+\t},\n+\t[166] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01b8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 23\n+\t},\n+\t[167] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_003e,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 24\n+\t},\n+\t[168] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02f6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 25\n+\t},\n+\t[169] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_078c,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 26\n+\t},\n+\t[170] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0044,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 27\n+\t},\n+\t[171] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01d2,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 28\n+\t},\n+\t[172] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_031a,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 29\n+\t},\n+\t[173] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0660,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 30\n+\t},\n+\t[174] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01a8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 31\n+\t},\n+\t[175] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01ce,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 32\n+\t},\n+\t[176] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0306,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 33\n+\t},\n+\t[177] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_067c,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 34\n+\t},\n+\t[178] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01b4,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_EGR },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_SMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF21_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t.class_tid = 21,\n+\t.wc_pri = 35\n \t}\n };\n \n@@ -3236,7 +3636,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {\n \t},\n \t{\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.priority = BNXT_ULP_PRIORITY_LEVEL_0,\n \t.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,\n@@ -3255,7 +3655,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {\n \t},\n \t{\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.priority = BNXT_ULP_PRIORITY_LEVEL_0,\n \t.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,\n@@ -3346,7 +3746,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {\n \t},\n \t{\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.priority = BNXT_ULP_PRIORITY_LEVEL_0,\n \t.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,\n@@ -12534,8 +12934,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 12,\n-\t.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,\n-\t.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO\n+\t.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,\n+\t.mask_operand = {\n+\t\t(BNXT_ULP_HF21_IDX_OO_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_HF21_IDX_OO_VLAN_VID & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,\n+\t.spec_operand = {\n+\t\t(BNXT_ULP_HF21_IDX_OO_VLAN_VID >> 8) & 0xff,\n+\t\tBNXT_ULP_HF21_IDX_OO_VLAN_VID & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 12,\n@@ -12594,8 +13004,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 2,\n-\t.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,\n-\t.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO\n+\t.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,\n+\t.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n+\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},\n+\t.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,\n+\t.spec_operand = {\n+\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 2,\n@@ -16307,11 +16724,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 4,\n-\t.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,\n+\t.result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF,\n \t.result_operand = {\n-\t\tBNXT_ULP_SYM_VF_FUNC_PARIF,\n+\t\t(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_true = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_false = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 8,\n@@ -16498,11 +16926,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 4,\n-\t.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,\n+\t.result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF,\n \t.result_operand = {\n-\t\tBNXT_ULP_SYM_VF_FUNC_PARIF,\n+\t\t(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_true = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_false = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 8,\n@@ -16689,7 +17128,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 4,\n-\t.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO\n+\t.result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF,\n+\t.result_operand = {\n+\t\t(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_true = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_false = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 8,\n@@ -16876,11 +17330,22 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {\n \t},\n \t{\n \t.field_bit_size = 4,\n-\t.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,\n+\t.result_opcode = BNXT_ULP_MAPPER_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF,\n \t.result_operand = {\n-\t\tBNXT_ULP_SYM_VF_FUNC_PARIF,\n+\t\t(BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP & 0xff,\n \t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_true = {\n+\t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n+\t.result_operand_false = {\n+\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n \t},\n \t{\n \t.field_bit_size = 8,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\nindex f08065b28..ac651f63f 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n@@ -11,7 +11,7 @@\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n #define BNXT_ULP_CACHE_TBL_MAX_SZ 4\n #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 155\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 179\n #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919\n #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907\n #define BNXT_ULP_CLASS_HID_SHFTR 32\n@@ -781,7 +781,31 @@ enum bnxt_ulp_class_hid {\n \tBNXT_ULP_CLASS_HID_01d1 = 0x01d1,\n \tBNXT_ULP_CLASS_HID_0319 = 0x0319,\n \tBNXT_ULP_CLASS_HID_01cd = 0x01cd,\n-\tBNXT_ULP_CLASS_HID_0305 = 0x0305\n+\tBNXT_ULP_CLASS_HID_0305 = 0x0305,\n+\tBNXT_ULP_CLASS_HID_01e2 = 0x01e2,\n+\tBNXT_ULP_CLASS_HID_032a = 0x032a,\n+\tBNXT_ULP_CLASS_HID_0650 = 0x0650,\n+\tBNXT_ULP_CLASS_HID_0198 = 0x0198,\n+\tBNXT_ULP_CLASS_HID_01de = 0x01de,\n+\tBNXT_ULP_CLASS_HID_0316 = 0x0316,\n+\tBNXT_ULP_CLASS_HID_066c = 0x066c,\n+\tBNXT_ULP_CLASS_HID_01a4 = 0x01a4,\n+\tBNXT_ULP_CLASS_HID_01c2 = 0x01c2,\n+\tBNXT_ULP_CLASS_HID_030a = 0x030a,\n+\tBNXT_ULP_CLASS_HID_0670 = 0x0670,\n+\tBNXT_ULP_CLASS_HID_01b8 = 0x01b8,\n+\tBNXT_ULP_CLASS_HID_003e = 0x003e,\n+\tBNXT_ULP_CLASS_HID_02f6 = 0x02f6,\n+\tBNXT_ULP_CLASS_HID_078c = 0x078c,\n+\tBNXT_ULP_CLASS_HID_0044 = 0x0044,\n+\tBNXT_ULP_CLASS_HID_01d2 = 0x01d2,\n+\tBNXT_ULP_CLASS_HID_031a = 0x031a,\n+\tBNXT_ULP_CLASS_HID_0660 = 0x0660,\n+\tBNXT_ULP_CLASS_HID_01a8 = 0x01a8,\n+\tBNXT_ULP_CLASS_HID_01ce = 0x01ce,\n+\tBNXT_ULP_CLASS_HID_0306 = 0x0306,\n+\tBNXT_ULP_CLASS_HID_067c = 0x067c,\n+\tBNXT_ULP_CLASS_HID_01b4 = 0x01b4\n };\n \n enum bnxt_ulp_act_hid {\n",
    "prefixes": [
        "v3",
        "10/22"
    ]
}