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{
    "id": 74595,
    "url": "https://patches.dpdk.org/api/patches/74595/",
    "web_url": "https://patches.dpdk.org/patch/74595/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200722021628.17194-1-ting.xu@intel.com>",
    "date": "2020-07-22T02:16:28",
    "name": "[v4] lib/table: fix cache alignment issue",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "4c8d9f8c788383769f9343a7edf135606053e091",
    "submitter": {
        "id": 1363,
        "url": "https://patches.dpdk.org/api/people/1363/",
        "name": "Xu, Ting",
        "email": "ting.xu@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/patch/74595/mbox/",
    "series": [
        {
            "id": 11223,
            "url": "https://patches.dpdk.org/api/series/11223/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11223",
            "date": "2020-07-22T02:16:28",
            "name": "[v4] lib/table: fix cache alignment issue",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/11223/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74595/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74595/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9689\"; a=\"148197055\"",
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            "E=Sophos;i=\"5.75,381,1589266800\"; d=\"scan'208\";a=\"310456302\""
        ],
        "IronPort-SDR": [
            "\n 0NrqmZEDWEj8nwAFGniJv/xx67MXAXwumW+NkxwvYJfSjIDvcV4vf9DuhLk9c6JbeSoOSJ+MzF\n 1nlQUmhXDnNw==",
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        ],
        "X-Amp-File-Uploaded": "False",
        "Precedence": "list",
        "X-Mailman-Version": "2.1.15",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<20200616162705.83575-1-ting.xu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4] lib/table: fix cache alignment issue",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96EFBA0526;\n\tWed, 22 Jul 2020 04:12:56 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5DAB41BFBA;\n\tWed, 22 Jul 2020 04:12:55 +0200 (CEST)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 5B7EC2C01;\n Wed, 22 Jul 2020 04:12:53 +0200 (CEST)",
            "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 19:12:52 -0700",
            "from dpdk-xuting-second.sh.intel.com ([10.67.116.154])\n by fmsmga004.fm.intel.com with ESMTP; 21 Jul 2020 19:12:50 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Mailer": "git-send-email 2.17.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-ExtLoop1": "1",
        "Date": "Wed, 22 Jul 2020 10:16:28 +0800",
        "To": "dev@dpdk.org",
        "From": "Ting Xu <ting.xu@intel.com>",
        "In-Reply-To": "<20200616162705.83575-1-ting.xu@intel.com>",
        "Cc": "cristian.dumitrescu@intel.com, Ting Xu <ting.xu@intel.com>,\n stable@dpdk.org",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<20200722021628.17194-1-ting.xu@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "When create softnic hash table with 16 keys, it failed on 32-bit\nenvironment, because the pointer field in structure rte_bucket_4_16\nis only 32 bits. Add a padding field in 32-bit environment to keep\nthe structure to a multiple of 64 bytes. Apply this to 8-byte and\n32-byte key hash function as well.\n\nFixes: 8aa327214c (\"table: hash\")\nCc: stable@dpdk.org\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\n\n---\nv3->v4: Change design based on comment\nv2->v3: Rebase\nv1->v2: Correct patch time\n---\n lib/librte_table/rte_table_hash_key16.c | 17 +++++++++++++++++\n lib/librte_table/rte_table_hash_key32.c | 17 +++++++++++++++++\n lib/librte_table/rte_table_hash_key8.c  | 16 ++++++++++++++++\n 3 files changed, 50 insertions(+)",
    "diff": "diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c\nindex 2cca1c924..c4384b114 100644\n--- a/lib/librte_table/rte_table_hash_key16.c\n+++ b/lib/librte_table/rte_table_hash_key16.c\n@@ -33,6 +33,7 @@\n \n #endif\n \n+#ifdef RTE_ARCH_64\n struct rte_bucket_4_16 {\n \t/* Cache line 0 */\n \tuint64_t signature[4 + 1];\n@@ -46,6 +47,22 @@ struct rte_bucket_4_16 {\n \t/* Cache line 2 */\n \tuint8_t data[0];\n };\n+#else\n+struct rte_bucket_4_16 {\n+\t/* Cache line 0 */\n+\tuint64_t signature[4 + 1];\n+\tuint64_t lru_list;\n+\tstruct rte_bucket_4_16 *next;\n+\tuint32_t pad;\n+\tuint64_t next_valid;\n+\n+\t/* Cache line 1 */\n+\tuint64_t key[4][2];\n+\n+\t/* Cache line 2 */\n+\tuint8_t data[0];\n+};\n+#endif\n \n struct rte_table_hash {\n \tstruct rte_table_stats stats;\ndiff --git a/lib/librte_table/rte_table_hash_key32.c b/lib/librte_table/rte_table_hash_key32.c\nindex a137c5028..3e0031fe1 100644\n--- a/lib/librte_table/rte_table_hash_key32.c\n+++ b/lib/librte_table/rte_table_hash_key32.c\n@@ -33,6 +33,7 @@\n \n #endif\n \n+#ifdef RTE_ARCH_64\n struct rte_bucket_4_32 {\n \t/* Cache line 0 */\n \tuint64_t signature[4 + 1];\n@@ -46,6 +47,22 @@ struct rte_bucket_4_32 {\n \t/* Cache line 3 */\n \tuint8_t data[0];\n };\n+#else\n+struct rte_bucket_4_32 {\n+\t/* Cache line 0 */\n+\tuint64_t signature[4 + 1];\n+\tuint64_t lru_list;\n+\tstruct rte_bucket_4_32 *next;\n+\tuint32_t pad;\n+\tuint64_t next_valid;\n+\n+\t/* Cache lines 1 and 2 */\n+\tuint64_t key[4][4];\n+\n+\t/* Cache line 3 */\n+\tuint8_t data[0];\n+};\n+#endif\n \n struct rte_table_hash {\n \tstruct rte_table_stats stats;\ndiff --git a/lib/librte_table/rte_table_hash_key8.c b/lib/librte_table/rte_table_hash_key8.c\nindex 1811ad8d0..34e3ed1af 100644\n--- a/lib/librte_table/rte_table_hash_key8.c\n+++ b/lib/librte_table/rte_table_hash_key8.c\n@@ -31,6 +31,7 @@\n \n #endif\n \n+#ifdef RTE_ARCH_64\n struct rte_bucket_4_8 {\n \t/* Cache line 0 */\n \tuint64_t signature;\n@@ -43,6 +44,21 @@ struct rte_bucket_4_8 {\n \t/* Cache line 1 */\n \tuint8_t data[0];\n };\n+#else\n+struct rte_bucket_4_8 {\n+\t/* Cache line 0 */\n+\tuint64_t signature;\n+\tuint64_t lru_list;\n+\tstruct rte_bucket_4_8 *next;\n+\tuint32_t pad;\n+\tuint64_t next_valid;\n+\n+\tuint64_t key[4];\n+\n+\t/* Cache line 1 */\n+\tuint8_t data[0];\n+};\n+#endif\n \n struct rte_table_hash {\n \tstruct rte_table_stats stats;\n",
    "prefixes": [
        "v4"
    ]
}