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GET /api/patches/74573/?format=api
{ "id": 74573, "url": "https://patches.dpdk.org/api/patches/74573/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1595333116-7238-1-git-send-email-michaelba@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1595333116-7238-1-git-send-email-michaelba@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1595333116-7238-1-git-send-email-michaelba@mellanox.com", "date": "2020-07-21T12:05:16", "name": "net/mlx5: optimize stuck memory in probe", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "71418ae49e7581e020447188506641b678e7da16", "submitter": { "id": 1582, "url": "https://patches.dpdk.org/api/people/1582/?format=api", "name": "Michael Baum", "email": "michaelba@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1595333116-7238-1-git-send-email-michaelba@mellanox.com/mbox/", "series": [ { "id": 11210, "url": "https://patches.dpdk.org/api/series/11210/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11210", "date": "2020-07-21T12:05:16", "name": "net/mlx5: optimize stuck memory in probe", "version": 1, "mbox": "https://patches.dpdk.org/series/11210/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/74573/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/74573/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7311FA0526;\n\tTue, 21 Jul 2020 14:05:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 54F861BFF9;\n\tTue, 21 Jul 2020 14:05:25 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 918A91BFEF\n for <dev@dpdk.org>; Tue, 21 Jul 2020 14:05:23 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@mellanox.com) with SMTP; 21 Jul 2020 15:05:19 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06LC5IwQ026497;\n Tue, 21 Jul 2020 15:05:18 +0300" ], "From": "Michael Baum <michaelba@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, viacheslavo@mellanox.com", "Date": "Tue, 21 Jul 2020 12:05:16 +0000", "Message-Id": "<1595333116-7238-1-git-send-email-michaelba@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH] net/mlx5: optimize stuck memory in probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The device configuration stuck is not small enough to be used as\nfunction argument by value.\n\nCall spawn function with device configuration by value.\n\nSigned-off-by: Michael Baum <michaelba@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 251 +++++++++++++++++++--------------------\n 1 file changed, 124 insertions(+), 127 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 2d6ddf0..f3e20b5 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -498,7 +498,7 @@\n static struct rte_eth_dev *\n mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t struct mlx5_dev_spawn_data *spawn,\n-\t struct mlx5_dev_config config)\n+\t struct mlx5_dev_config *config)\n {\n \tconst struct mlx5_switch_info *switch_info = &spawn->info;\n \tstruct mlx5_dev_ctx_shared *sh = NULL;\n@@ -616,20 +616,20 @@\n \t * devargs here to get ones, and later proceed devargs again\n \t * to override some hardware settings.\n \t */\n-\terr = mlx5_args(&config, dpdk_dev->devargs);\n+\terr = mlx5_args(config, dpdk_dev->devargs);\n \tif (err) {\n \t\terr = rte_errno;\n \t\tDRV_LOG(ERR, \"failed to process device arguments: %s\",\n \t\t\tstrerror(rte_errno));\n \t\tgoto error;\n \t}\n-\tmlx5_malloc_mem_select(config.sys_mem_en);\n-\tsh = mlx5_alloc_shared_dev_ctx(spawn, &config);\n+\tmlx5_malloc_mem_select(config->sys_mem_en);\n+\tsh = mlx5_alloc_shared_dev_ctx(spawn, config);\n \tif (!sh)\n \t\treturn NULL;\n-\tconfig.devx = sh->devx;\n+\tconfig->devx = sh->devx;\n #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR\n-\tconfig.dest_tir = 1;\n+\tconfig->dest_tir = 1;\n #endif\n #ifdef HAVE_IBV_MLX5_MOD_SWP\n \tdv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;\n@@ -662,7 +662,7 @@\n \t\tswp = dv_attr.sw_parsing_caps.sw_parsing_offloads;\n \tDRV_LOG(DEBUG, \"SWP support: %u\", swp);\n #endif\n-\tconfig.swp = !!swp;\n+\tconfig->swp = !!swp;\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n \tif (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {\n \t\tstruct mlx5dv_striding_rq_caps mprq_caps =\n@@ -695,7 +695,7 @@\n \t\tcqe_comp = 0;\n \telse\n \t\tcqe_comp = 1;\n-\tconfig.cqe_comp = cqe_comp;\n+\tconfig->cqe_comp = cqe_comp;\n #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n \t/* Whether device supports 128B Rx CQE padding. */\n \tcqe_pad = RTE_CACHE_LINE_SIZE == 128 &&\n@@ -716,7 +716,7 @@\n \tDRV_LOG(WARNING,\n \t\t\"tunnel offloading disabled due to old OFED/rdma-core version\");\n #endif\n-\tconfig.tunnel_en = tunnel_en;\n+\tconfig->tunnel_en = tunnel_en;\n #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT\n \tmpls_en = ((dv_attr.tunnel_offloads_caps &\n \t\t MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&\n@@ -728,7 +728,7 @@\n \tDRV_LOG(WARNING, \"MPLS over GRE/UDP tunnel offloading disabled due to\"\n \t\t\" old OFED/rdma-core version or firmware configuration\");\n #endif\n-\tconfig.mpls_en = mpls_en;\n+\tconfig->mpls_en = mpls_en;\n \t/* Check port status. */\n \terr = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr);\n \tif (err) {\n@@ -869,39 +869,39 @@\n \t\town_domain_id = 1;\n \t}\n \t/* Override some values set by hardware configuration. */\n-\tmlx5_args(&config, dpdk_dev->devargs);\n-\terr = mlx5_dev_check_sibling_config(priv, &config);\n+\tmlx5_args(config, dpdk_dev->devargs);\n+\terr = mlx5_dev_check_sibling_config(priv, config);\n \tif (err)\n \t\tgoto error;\n-\tconfig.hw_csum = !!(sh->device_attr.device_cap_flags_ex &\n+\tconfig->hw_csum = !!(sh->device_attr.device_cap_flags_ex &\n \t\t\t IBV_DEVICE_RAW_IP_CSUM);\n \tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n-\t\t(config.hw_csum ? \"\" : \"not \"));\n+\t\t(config->hw_csum ? \"\" : \"not \"));\n #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \\\n \t!defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)\n \tDRV_LOG(DEBUG, \"counters are not supported\");\n #endif\n #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)\n-\tif (config.dv_flow_en) {\n+\tif (config->dv_flow_en) {\n \t\tDRV_LOG(WARNING, \"DV flow is not supported\");\n-\t\tconfig.dv_flow_en = 0;\n+\t\tconfig->dv_flow_en = 0;\n \t}\n #endif\n-\tconfig.ind_table_max_size =\n+\tconfig->ind_table_max_size =\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n \t/*\n \t * Remove this check once DPDK supports larger/variable\n \t * indirection tables.\n \t */\n-\tif (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)\n-\t\tconfig.ind_table_max_size = ETH_RSS_RETA_SIZE_512;\n+\tif (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)\n+\t\tconfig->ind_table_max_size = ETH_RSS_RETA_SIZE_512;\n \tDRV_LOG(DEBUG, \"maximum Rx indirection table size is %u\",\n-\t\tconfig.ind_table_max_size);\n-\tconfig.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &\n+\t\tconfig->ind_table_max_size);\n+\tconfig->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &\n \t\t\t\t IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);\n \tDRV_LOG(DEBUG, \"VLAN stripping is %ssupported\",\n-\t\t(config.hw_vlan_strip ? \"\" : \"not \"));\n-\tconfig.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &\n+\t\t(config->hw_vlan_strip ? \"\" : \"not \"));\n+\tconfig->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &\n \t\t\t\t IBV_RAW_PACKET_CAP_SCATTER_FCS);\n #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)\n \thw_padding = !!sh->device_attr.rx_pad_end_addr_align;\n@@ -909,48 +909,48 @@\n \thw_padding = !!(sh->device_attr.device_cap_flags_ex &\n \t\t\tIBV_DEVICE_PCI_WRITE_END_PADDING);\n #endif\n-\tif (config.hw_padding && !hw_padding) {\n+\tif (config->hw_padding && !hw_padding) {\n \t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported\");\n-\t\tconfig.hw_padding = 0;\n-\t} else if (config.hw_padding) {\n+\t\tconfig->hw_padding = 0;\n+\t} else if (config->hw_padding) {\n \t\tDRV_LOG(DEBUG, \"Rx end alignment padding is enabled\");\n \t}\n-\tconfig.tso = (sh->device_attr.max_tso > 0 &&\n+\tconfig->tso = (sh->device_attr.max_tso > 0 &&\n \t\t (sh->device_attr.tso_supported_qpts &\n \t\t (1 << IBV_QPT_RAW_PACKET)));\n-\tif (config.tso)\n-\t\tconfig.tso_max_payload_sz = sh->device_attr.max_tso;\n+\tif (config->tso)\n+\t\tconfig->tso_max_payload_sz = sh->device_attr.max_tso;\n \t/*\n \t * MPW is disabled by default, while the Enhanced MPW is enabled\n \t * by default.\n \t */\n-\tif (config.mps == MLX5_ARG_UNSET)\n-\t\tconfig.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :\n+\tif (config->mps == MLX5_ARG_UNSET)\n+\t\tconfig->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :\n \t\t\t\t\t\t\t MLX5_MPW_DISABLED;\n \telse\n-\t\tconfig.mps = config.mps ? mps : MLX5_MPW_DISABLED;\n+\t\tconfig->mps = config->mps ? mps : MLX5_MPW_DISABLED;\n \tDRV_LOG(INFO, \"%sMPS is %s\",\n-\t\tconfig.mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n-\t\tconfig.mps == MLX5_MPW ? \"legacy \" : \"\",\n-\t\tconfig.mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n-\tif (config.cqe_comp && !cqe_comp) {\n+\t\tconfig->mps == MLX5_MPW_ENHANCED ? \"enhanced \" :\n+\t\tconfig->mps == MLX5_MPW ? \"legacy \" : \"\",\n+\t\tconfig->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n+\tif (config->cqe_comp && !cqe_comp) {\n \t\tDRV_LOG(WARNING, \"Rx CQE compression isn't supported\");\n-\t\tconfig.cqe_comp = 0;\n+\t\tconfig->cqe_comp = 0;\n \t}\n-\tif (config.cqe_pad && !cqe_pad) {\n+\tif (config->cqe_pad && !cqe_pad) {\n \t\tDRV_LOG(WARNING, \"Rx CQE padding isn't supported\");\n-\t\tconfig.cqe_pad = 0;\n-\t} else if (config.cqe_pad) {\n+\t\tconfig->cqe_pad = 0;\n+\t} else if (config->cqe_pad) {\n \t\tDRV_LOG(INFO, \"Rx CQE padding is enabled\");\n \t}\n-\tif (config.devx) {\n+\tif (config->devx) {\n \t\tpriv->counter_fallback = 0;\n-\t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);\n+\t\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);\n \t\tif (err) {\n \t\t\terr = -err;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.flow_counters_dump)\n+\t\tif (!config->hca_attr.flow_counters_dump)\n \t\t\tpriv->counter_fallback = 1;\n #ifndef HAVE_IBV_DEVX_ASYNC\n \t\tpriv->counter_fallback = 1;\n@@ -958,26 +958,27 @@\n \t\tif (priv->counter_fallback)\n \t\t\tDRV_LOG(INFO, \"Use fall-back DV counter management\");\n \t\t/* Check for LRO support. */\n-\t\tif (config.dest_tir && config.hca_attr.lro_cap &&\n-\t\t config.dv_flow_en) {\n+\t\tif (config->dest_tir && config->hca_attr.lro_cap &&\n+\t\t config->dv_flow_en) {\n \t\t\t/* TBD check tunnel lro caps. */\n-\t\t\tconfig.lro.supported = config.hca_attr.lro_cap;\n+\t\t\tconfig->lro.supported = config->hca_attr.lro_cap;\n \t\t\tDRV_LOG(DEBUG, \"Device supports LRO\");\n \t\t\t/*\n \t\t\t * If LRO timeout is not configured by application,\n \t\t\t * use the minimal supported value.\n \t\t\t */\n-\t\t\tif (!config.lro.timeout)\n-\t\t\t\tconfig.lro.timeout =\n-\t\t\t\tconfig.hca_attr.lro_timer_supported_periods[0];\n+\t\t\tif (!config->lro.timeout)\n+\t\t\t\tconfig->lro.timeout =\n+\t\t\t\tconfig->hca_attr.lro_timer_supported_periods[0];\n \t\t\tDRV_LOG(DEBUG, \"LRO session timeout set to %d usec\",\n-\t\t\t\tconfig.lro.timeout);\n+\t\t\t\tconfig->lro.timeout);\n \t\t}\n #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)\n-\t\tif (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&\n-\t\t config.dv_flow_en) {\n+\t\tif (config->hca_attr.qos.sup &&\n+\t\t config->hca_attr.qos.srtcm_sup &&\n+\t\t config->dv_flow_en) {\n \t\t\tuint8_t reg_c_mask =\n-\t\t\t\tconfig.hca_attr.qos.flow_meter_reg_c_ids;\n+\t\t\t\tconfig->hca_attr.qos.flow_meter_reg_c_ids;\n \t\t\t/*\n \t\t\t * Meter needs two REG_C's for color match and pre-sfx\n \t\t\t * flow match. Here get the REG_C for color match.\n@@ -993,64 +994,64 @@\n \t\t\t\t\t\t REG_C_0;\n \t\t\t\tpriv->mtr_en = 1;\n \t\t\t\tpriv->mtr_reg_share =\n-\t\t\t\t config.hca_attr.qos.flow_meter_reg_share;\n+\t\t\t\t config->hca_attr.qos.flow_meter_reg_share;\n \t\t\t\tDRV_LOG(DEBUG, \"The REG_C meter uses is %d\",\n \t\t\t\t\tpriv->mtr_color_reg);\n \t\t\t}\n \t\t}\n #endif\n \t}\n-\tif (config.tx_pp) {\n+\tif (config->tx_pp) {\n \t\tDRV_LOG(DEBUG, \"Timestamp counter frequency %u kHz\",\n-\t\t\tconfig.hca_attr.dev_freq_khz);\n+\t\t\tconfig->hca_attr.dev_freq_khz);\n \t\tDRV_LOG(DEBUG, \"Packet pacing is %ssupported\",\n-\t\t\tconfig.hca_attr.qos.packet_pacing ? \"\" : \"not \");\n+\t\t\tconfig->hca_attr.qos.packet_pacing ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Cross channel ops are %ssupported\",\n-\t\t\tconfig.hca_attr.cross_channel ? \"\" : \"not \");\n+\t\t\tconfig->hca_attr.cross_channel ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"WQE index ignore is %ssupported\",\n-\t\t\tconfig.hca_attr.wqe_index_ignore ? \"\" : \"not \");\n+\t\t\tconfig->hca_attr.wqe_index_ignore ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Non-wire SQ feature is %ssupported\",\n-\t\t\tconfig.hca_attr.non_wire_sq ? \"\" : \"not \");\n+\t\t\tconfig->hca_attr.non_wire_sq ? \"\" : \"not \");\n \t\tDRV_LOG(DEBUG, \"Static WQE SQ feature is %ssupported (%d)\",\n-\t\t\tconfig.hca_attr.log_max_static_sq_wq ? \"\" : \"not \",\n-\t\t\tconfig.hca_attr.log_max_static_sq_wq);\n+\t\t\tconfig->hca_attr.log_max_static_sq_wq ? \"\" : \"not \",\n+\t\t\tconfig->hca_attr.log_max_static_sq_wq);\n \t\tDRV_LOG(DEBUG, \"WQE rate PP mode is %ssupported\",\n-\t\t\tconfig.hca_attr.qos.wqe_rate_pp ? \"\" : \"not \");\n-\t\tif (!config.devx) {\n+\t\t\tconfig->hca_attr.qos.wqe_rate_pp ? \"\" : \"not \");\n+\t\tif (!config->devx) {\n \t\t\tDRV_LOG(ERR, \"DevX is required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.qos.packet_pacing) {\n+\t\tif (!config->hca_attr.qos.packet_pacing) {\n \t\t\tDRV_LOG(ERR, \"Packet pacing is not supported\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.cross_channel) {\n+\t\tif (!config->hca_attr.cross_channel) {\n \t\t\tDRV_LOG(ERR, \"Cross channel operations are\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.wqe_index_ignore) {\n+\t\tif (!config->hca_attr.wqe_index_ignore) {\n \t\t\tDRV_LOG(ERR, \"WQE index ignore feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.non_wire_sq) {\n+\t\tif (!config->hca_attr.non_wire_sq) {\n \t\t\tDRV_LOG(ERR, \"Non-wire SQ feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.log_max_static_sq_wq) {\n+\t\tif (!config->hca_attr.log_max_static_sq_wq) {\n \t\t\tDRV_LOG(ERR, \"Static WQE SQ feature is\"\n \t\t\t\t \" required for packet pacing\");\n \t\t\terr = ENODEV;\n \t\t\tgoto error;\n \t\t}\n-\t\tif (!config.hca_attr.qos.wqe_rate_pp) {\n+\t\tif (!config->hca_attr.qos.wqe_rate_pp) {\n \t\t\tDRV_LOG(ERR, \"WQE rate mode is required\"\n \t\t\t\t \" for packet pacing\");\n \t\t\terr = ENODEV;\n@@ -1063,7 +1064,7 @@\n \t\tgoto error;\n #endif\n \t}\n-\tif (config.devx) {\n+\tif (config->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n \n \t\terr = mlx5_devx_cmd_register_read\n@@ -1076,12 +1077,12 @@\n \t\t\tts_mode = MLX5_GET(register_mtutc, reg,\n \t\t\t\t\t time_stamp_mode);\n \t\t\tif (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)\n-\t\t\t\tconfig.rt_timestamp = 1;\n+\t\t\t\tconfig->rt_timestamp = 1;\n \t\t} else {\n \t\t\t/* Kernel does not support register reading. */\n-\t\t\tif (config.hca_attr.dev_freq_khz ==\n+\t\t\tif (config->hca_attr.dev_freq_khz ==\n \t\t\t\t\t\t (NS_PER_S / MS_PER_S))\n-\t\t\t\tconfig.rt_timestamp = 1;\n+\t\t\t\tconfig->rt_timestamp = 1;\n \t\t}\n \t}\n \t/*\n@@ -1089,15 +1090,15 @@\n \t * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip\n \t * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.\n \t */\n-\tif (config.hca_attr.scatter_fcs_w_decap_disable && config.decap_en)\n-\t\tconfig.hw_fcs_strip = 0;\n+\tif (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en)\n+\t\tconfig->hw_fcs_strip = 0;\n \tDRV_LOG(DEBUG, \"FCS stripping configuration is %ssupported\",\n-\t\t(config.hw_fcs_strip ? \"\" : \"not \"));\n-\tif (config.mprq.enabled && mprq) {\n-\t\tif (config.mprq.stride_num_n &&\n-\t\t (config.mprq.stride_num_n > mprq_max_stride_num_n ||\n-\t\t config.mprq.stride_num_n < mprq_min_stride_num_n)) {\n-\t\t\tconfig.mprq.stride_num_n =\n+\t\t(config->hw_fcs_strip ? \"\" : \"not \"));\n+\tif (config->mprq.enabled && mprq) {\n+\t\tif (config->mprq.stride_num_n &&\n+\t\t (config->mprq.stride_num_n > mprq_max_stride_num_n ||\n+\t\t config->mprq.stride_num_n < mprq_min_stride_num_n)) {\n+\t\t\tconfig->mprq.stride_num_n =\n \t\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,\n \t\t\t\t\t\tmprq_min_stride_num_n),\n \t\t\t\t\tmprq_max_stride_num_n);\n@@ -1105,12 +1106,12 @@\n \t\t\t\t\"the number of strides\"\n \t\t\t\t\" for Multi-Packet RQ is out of range,\"\n \t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config.mprq.stride_num_n);\n+\t\t\t\t1 << config->mprq.stride_num_n);\n \t\t}\n-\t\tif (config.mprq.stride_size_n &&\n-\t\t (config.mprq.stride_size_n > mprq_max_stride_size_n ||\n-\t\t config.mprq.stride_size_n < mprq_min_stride_size_n)) {\n-\t\t\tconfig.mprq.stride_size_n =\n+\t\tif (config->mprq.stride_size_n &&\n+\t\t (config->mprq.stride_size_n > mprq_max_stride_size_n ||\n+\t\t config->mprq.stride_size_n < mprq_min_stride_size_n)) {\n+\t\t\tconfig->mprq.stride_size_n =\n \t\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,\n \t\t\t\t\t\tmprq_min_stride_size_n),\n \t\t\t\t\tmprq_max_stride_size_n);\n@@ -1118,16 +1119,16 @@\n \t\t\t\t\"the size of a stride\"\n \t\t\t\t\" for Multi-Packet RQ is out of range,\"\n \t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config.mprq.stride_size_n);\n+\t\t\t\t1 << config->mprq.stride_size_n);\n \t\t}\n-\t\tconfig.mprq.min_stride_size_n = mprq_min_stride_size_n;\n-\t\tconfig.mprq.max_stride_size_n = mprq_max_stride_size_n;\n-\t} else if (config.mprq.enabled && !mprq) {\n+\t\tconfig->mprq.min_stride_size_n = mprq_min_stride_size_n;\n+\t\tconfig->mprq.max_stride_size_n = mprq_max_stride_size_n;\n+\t} else if (config->mprq.enabled && !mprq) {\n \t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported\");\n-\t\tconfig.mprq.enabled = 0;\n+\t\tconfig->mprq.enabled = 0;\n \t}\n-\tif (config.max_dump_files_num == 0)\n-\t\tconfig.max_dump_files_num = 128;\n+\tif (config->max_dump_files_num == 0)\n+\t\tconfig->max_dump_files_num = 128;\n \teth_dev = rte_eth_dev_allocate(name);\n \tif (eth_dev == NULL) {\n \t\tDRV_LOG(ERR, \"can not allocate rte ethdev\");\n@@ -1192,7 +1193,7 @@\n \teth_dev->dev_ops = &mlx5_os_dev_ops;\n \t/* Register MAC address. */\n \tclaim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));\n-\tif (config.vf && config.vf_nl_en)\n+\tif (config->vf && config->vf_nl_en)\n \t\tmlx5_nl_mac_addr_sync(priv->nl_socket_route,\n \t\t\t\t mlx5_ifindex(eth_dev),\n \t\t\t\t eth_dev->data->mac_addrs,\n@@ -1220,19 +1221,19 @@\n \t */\n \tmlx5_link_update(eth_dev, 0);\n #ifdef HAVE_MLX5DV_DR_ESWITCH\n-\tif (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&\n+\tif (!(config->hca_attr.eswitch_manager && config->dv_flow_en &&\n \t (switch_info->representor || switch_info->master)))\n-\t\tconfig.dv_esw_en = 0;\n+\t\tconfig->dv_esw_en = 0;\n #else\n-\tconfig.dv_esw_en = 0;\n+\tconfig->dv_esw_en = 0;\n #endif\n \t/* Detect minimal data bytes to inline. */\n-\tmlx5_set_min_inline(spawn, &config);\n+\tmlx5_set_min_inline(spawn, config);\n \t/* Store device configuration on private structure. */\n-\tpriv->config = config;\n+\tpriv->config = *config;\n \t/* Create context for virtual machine VLAN workaround. */\n \tpriv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);\n-\tif (config.dv_flow_en) {\n+\tif (config->dv_flow_en) {\n \t\terr = mlx5_alloc_shared_dr(priv);\n \t\tif (err)\n \t\t\tgoto error;\n@@ -1520,6 +1521,7 @@\n \tint bd = -1;\n \tstruct mlx5_dev_spawn_data *list = NULL;\n \tstruct mlx5_dev_config dev_config;\n+\tunsigned int dev_config_vf;\n \tint ret;\n \n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n@@ -1839,30 +1841,6 @@\n \t * (i.e. master first, then representors from lowest to highest ID).\n \t */\n \tqsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);\n-\t/* Default configuration. */\n-\tdev_config = (struct mlx5_dev_config){\n-\t\t.hw_padding = 0,\n-\t\t.mps = MLX5_ARG_UNSET,\n-\t\t.dbnc = MLX5_ARG_UNSET,\n-\t\t.rx_vec_en = 1,\n-\t\t.txq_inline_max = MLX5_ARG_UNSET,\n-\t\t.txq_inline_min = MLX5_ARG_UNSET,\n-\t\t.txq_inline_mpw = MLX5_ARG_UNSET,\n-\t\t.txqs_inline = MLX5_ARG_UNSET,\n-\t\t.vf_nl_en = 1,\n-\t\t.mr_ext_memseg_en = 1,\n-\t\t.mprq = {\n-\t\t\t.enabled = 0, /* Disabled by default. */\n-\t\t\t.stride_num_n = 0,\n-\t\t\t.stride_size_n = 0,\n-\t\t\t.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,\n-\t\t\t.min_rxqs_num = MLX5_MPRQ_MIN_RXQS,\n-\t\t},\n-\t\t.dv_esw_en = 1,\n-\t\t.dv_flow_en = 1,\n-\t\t.decap_en = 1,\n-\t\t.log_hp_size = MLX5_ARG_UNSET,\n-\t};\n \t/* Device specific configuration. */\n \tswitch (pci_dev->id.device_id) {\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n@@ -1872,17 +1850,36 @@\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:\n \tcase PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:\n-\t\tdev_config.vf = 1;\n+\t\tdev_config_vf = 1;\n \t\tbreak;\n \tdefault:\n+\t\tdev_config_vf = 0;\n \t\tbreak;\n \t}\n \tfor (i = 0; i != ns; ++i) {\n \t\tuint32_t restore;\n \n+\t\t/* Default configuration. */\n+\t\tmemset(&dev_config, 0, sizeof(struct mlx5_dev_config));\n+\t\tdev_config.vf = dev_config_vf;\n+\t\tdev_config.mps = MLX5_ARG_UNSET;\n+\t\tdev_config.dbnc = MLX5_ARG_UNSET;\n+\t\tdev_config.rx_vec_en = 1;\n+\t\tdev_config.txq_inline_max = MLX5_ARG_UNSET;\n+\t\tdev_config.txq_inline_min = MLX5_ARG_UNSET;\n+\t\tdev_config.txq_inline_mpw = MLX5_ARG_UNSET;\n+\t\tdev_config.txqs_inline = MLX5_ARG_UNSET;\n+\t\tdev_config.vf_nl_en = 1;\n+\t\tdev_config.mr_ext_memseg_en = 1;\n+\t\tdev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n+\t\tdev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n+\t\tdev_config.dv_esw_en = 1;\n+\t\tdev_config.dv_flow_en = 1;\n+\t\tdev_config.decap_en = 1;\n+\t\tdev_config.log_hp_size = MLX5_ARG_UNSET;\n \t\tlist[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,\n \t\t\t\t\t\t &list[i],\n-\t\t\t\t\t\t dev_config);\n+\t\t\t\t\t\t &dev_config);\n \t\tif (!list[i].eth_dev) {\n \t\t\tif (rte_errno != EBUSY && rte_errno != EEXIST)\n \t\t\t\tbreak;\n", "prefixes": [] }