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{
    "id": 74565,
    "url": "https://patches.dpdk.org/api/patches/74565/",
    "web_url": "https://patches.dpdk.org/patch/74565/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595331111-12151-5-git-send-email-radu.nicolau@intel.com>",
    "date": "2020-07-21T11:31:51",
    "name": "[v10,4/4] net/ixgbe: use WC store to update queue tail registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "80927d2cee7257f511f42e8108652f610fc0b0f3",
    "submitter": {
        "id": 743,
        "url": "https://patches.dpdk.org/api/people/743/",
        "name": "Nicolau, Radu",
        "email": "radu.nicolau@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/patch/74565/mbox/",
    "series": [
        {
            "id": 11202,
            "url": "https://patches.dpdk.org/api/series/11202/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11202",
            "date": "2020-07-21T11:31:47",
            "name": "eal: add WC store functions",
            "version": 10,
            "mbox": "https://patches.dpdk.org/series/11202/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74565/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/74565/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9688\"; a=\"214767037\"",
            "E=Sophos;i=\"5.75,378,1589266800\"; d=\"scan'208\";a=\"214767037\"",
            "E=Sophos;i=\"5.75,378,1589266800\"; d=\"scan'208\";a=\"462041863\""
        ],
        "IronPort-SDR": [
            "\n F5LGHU0S1TDH1wXBK2cBYWyCFB846Ji2iWtx1IIJ1ae+Oz/nKGp4WIIsHWzSYJHxS+gt5eSxMA\n 3EvnYZFU8pWw==",
            "\n JkWa1DoRh5cVwflUC3pRqgKE+GDiYtIOzOW5ubJOwe3KLZ/WDr9g4nqNkvOC58LFuX3mIjFm7H\n WP0/UijEBMyA=="
        ],
        "X-Amp-File-Uploaded": "False",
        "Precedence": "list",
        "X-Mailman-Version": "2.1.15",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<1591870283-7776-1-git-send-email-radu.nicolau@intel.com>\n <1595331111-12151-1-git-send-email-radu.nicolau@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v10 4/4] net/ixgbe: use WC store to update queue\n\ttail registers",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BDDEEA0526;\n\tTue, 21 Jul 2020 13:32:34 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 761611C05C;\n\tTue, 21 Jul 2020 13:32:12 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id E1A821BFE7\n for <dev@dpdk.org>; Tue, 21 Jul 2020 13:32:07 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 04:32:07 -0700",
            "from silpixa00383879.ir.intel.com ([10.237.222.142])\n by orsmga005.jf.intel.com with ESMTP; 21 Jul 2020 04:32:04 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Mailer": "git-send-email 2.7.4",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-ExtLoop1": "1",
        "Date": "Tue, 21 Jul 2020 12:31:51 +0100",
        "To": "dev@dpdk.org",
        "From": "Radu Nicolau <radu.nicolau@intel.com>",
        "In-Reply-To": "<1595331111-12151-1-git-send-email-radu.nicolau@intel.com>",
        "Cc": "beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, jerinjacobk@gmail.com,\n david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com,\n ruifeng.wang@arm.com, Radu Nicolau <radu.nicolau@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595331111-12151-5-git-send-email-radu.nicolau@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "Performance improvement: use a write combining store\ninstead of a regular mmio write to update queue tail\nregisters.\n\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_osdep.h   |  6 ++++++\n drivers/net/ixgbe/ixgbe_rxtx.c         | 15 ++++++++-------\n drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c |  4 ++--\n 3 files changed, 16 insertions(+), 9 deletions(-)",
    "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h\nindex dc712b7..cacf724 100644\n--- a/drivers/net/ixgbe/base/ixgbe_osdep.h\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h\n@@ -105,6 +105,12 @@ static inline uint32_t ixgbe_read_addr(volatile void* addr)\n #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value)\t\t\\\n \trte_write32_relaxed((rte_cpu_to_le_32(value)), reg)\n \n+#define IXGBE_PCI_REG_WC_WRITE(reg, value)\t\t\t\\\n+\trte_write32_wc((rte_cpu_to_le_32(value)), reg)\n+\n+#define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value)\t\t\\\n+\trte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)\n+\n #define IXGBE_PCI_REG_ADDR(hw, reg) \\\n \t((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))\n \ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 2e20e18..6701c07 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -308,7 +308,7 @@ tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \t/* update tail pointer */\n \trte_wmb();\n-\tIXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);\n+\tIXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);\n \n \treturn nb_pkts;\n }\n@@ -946,7 +946,7 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n \t\t   (unsigned) txq->port_id, (unsigned) txq->queue_id,\n \t\t   (unsigned) tx_id, (unsigned) nb_tx);\n-\tIXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);\n+\tIXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);\n \ttxq->tx_tail = tx_id;\n \n \treturn nb_tx;\n@@ -1692,7 +1692,7 @@ rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \t\t/* update tail pointer */\n \t\trte_wmb();\n-\t\tIXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,\n+\t\tIXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,\n \t\t\t\t\t    cur_free_trigger);\n \t}\n \n@@ -1918,7 +1918,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t   (unsigned) nb_rx);\n \t\trx_id = (uint16_t) ((rx_id == 0) ?\n \t\t\t\t     (rxq->nb_rx_desc - 1) : (rx_id - 1));\n-\t\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n+\t\tIXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);\n \t\tnb_hold = 0;\n \t}\n \trxq->nb_rx_hold = nb_hold;\n@@ -2096,8 +2096,9 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,\n \n \t\t\tif (!ixgbe_rx_alloc_bufs(rxq, false)) {\n \t\t\t\trte_wmb();\n-\t\t\t\tIXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,\n-\t\t\t\t\t\t\t    next_rdt);\n+\t\t\t\tIXGBE_PCI_REG_WC_WRITE_RELAXED(\n+\t\t\t\t\t\t\trxq->rdt_reg_addr,\n+\t\t\t\t\t\t\tnext_rdt);\n \t\t\t\tnb_hold -= rxq->rx_free_thresh;\n \t\t\t} else {\n \t\t\t\tPMD_RX_LOG(DEBUG, \"RX bulk alloc failed \"\n@@ -2262,7 +2263,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,\n \t\t\t   rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);\n \n \t\trte_wmb();\n-\t\tIXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);\n+\t\tIXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);\n \t\tnb_hold = 0;\n \t}\n \ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c\nindex 517ca31..e77a7f3 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c\n@@ -90,7 +90,7 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\n \t\t\t     (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n \n \t/* Update the tail pointer on the NIC */\n-\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n+\tIXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);\n }\n \n #ifdef RTE_LIBRTE_SECURITY\n@@ -697,7 +697,7 @@ ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \ttxq->tx_tail = tx_id;\n \n-\tIXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);\n+\tIXGBE_PCI_REG_WC_WRITE(txq->tdt_reg_addr, txq->tx_tail);\n \n \treturn nb_pkts;\n }\n",
    "prefixes": [
        "v10",
        "4/4"
    ]
}