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{
    "id": 74562,
    "url": "https://patches.dpdk.org/api/patches/74562/",
    "web_url": "https://patches.dpdk.org/patch/74562/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1595331111-12151-2-git-send-email-radu.nicolau@intel.com>",
    "date": "2020-07-21T11:31:48",
    "name": "[v10,1/4] eal: add WC store functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "abcc8bfe4219065c9791eef50d4b44e5287e3618",
    "submitter": {
        "id": 743,
        "url": "https://patches.dpdk.org/api/people/743/",
        "name": "Nicolau, Radu",
        "email": "radu.nicolau@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "https://patches.dpdk.org/api/users/24651/",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "https://patches.dpdk.org/patch/74562/mbox/",
    "series": [
        {
            "id": 11202,
            "url": "https://patches.dpdk.org/api/series/11202/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11202",
            "date": "2020-07-21T11:31:47",
            "name": "eal: add WC store functions",
            "version": 10,
            "mbox": "https://patches.dpdk.org/series/11202/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74562/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/74562/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9688\"; a=\"214767003\"",
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            "E=Sophos;i=\"5.75,378,1589266800\"; d=\"scan'208\";a=\"462041802\""
        ],
        "IronPort-SDR": [
            "\n 0HrBmblRWVcCmJ6FtBjhn6PTYt3IWq7v8l/86zGVcY/tsQAQsmp2DTTbYz1UBhB7jTNAR8bBQd\n 3P8iCAH0+ZxQ==",
            "\n ONfadtfVG0MZtxRd4yULsK7Il2OlJ8tnQrTlsp8RpVhfl5TqrJlOer4cSNjEgGypnKDz6r85B7\n kowEabb1eJgg=="
        ],
        "X-Amp-File-Uploaded": "False",
        "Precedence": "list",
        "X-Mailman-Version": "2.1.15",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<1591870283-7776-1-git-send-email-radu.nicolau@intel.com>\n <1595331111-12151-1-git-send-email-radu.nicolau@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v10 1/4] eal: add WC store functions",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B1818A0526;\n\tTue, 21 Jul 2020 13:32:06 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B27471C010;\n\tTue, 21 Jul 2020 13:32:01 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id B76871C00D\n for <dev@dpdk.org>; Tue, 21 Jul 2020 13:31:59 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 04:31:59 -0700",
            "from silpixa00383879.ir.intel.com ([10.237.222.142])\n by orsmga005.jf.intel.com with ESMTP; 21 Jul 2020 04:31:56 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Mailer": "git-send-email 2.7.4",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-ExtLoop1": "1",
        "Date": "Tue, 21 Jul 2020 12:31:48 +0100",
        "To": "dev@dpdk.org",
        "From": "Radu Nicolau <radu.nicolau@intel.com>",
        "In-Reply-To": "<1595331111-12151-1-git-send-email-radu.nicolau@intel.com>",
        "Cc": "beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, jerinjacobk@gmail.com,\n david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com,\n ruifeng.wang@arm.com, Radu Nicolau <radu.nicolau@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<1595331111-12151-2-git-send-email-radu.nicolau@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "Add rte_write32_wc and rte_write32_wc_relaxed functions\nthat implement 32bit stores using write combining memory protocol.\nProvided generic stubs and x86 implementation.\n\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\nAcked-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n lib/librte_eal/arm/include/rte_io_64.h  | 12 +++++++++\n lib/librte_eal/include/generic/rte_io.h | 48 +++++++++++++++++++++++++++++++++\n lib/librte_eal/x86/include/rte_io.h     | 42 +++++++++++++++++++++++++++++\n 3 files changed, 102 insertions(+)",
    "diff": "diff --git a/lib/librte_eal/arm/include/rte_io_64.h b/lib/librte_eal/arm/include/rte_io_64.h\nindex e534624..d07d9cb 100644\n--- a/lib/librte_eal/arm/include/rte_io_64.h\n+++ b/lib/librte_eal/arm/include/rte_io_64.h\n@@ -164,6 +164,18 @@ rte_write64(uint64_t value, volatile void *addr)\n \trte_write64_relaxed(value, addr);\n }\n \n+static __rte_always_inline void\n+rte_write32_wc(uint32_t value, volatile void *addr)\n+{\n+\trte_write32(value, addr);\n+}\n+\n+static __rte_always_inline void\n+rte_write32_wc_relaxed(uint32_t value, volatile void *addr)\n+{\n+\trte_write32_relaxed(value, addr);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/include/generic/rte_io.h b/lib/librte_eal/include/generic/rte_io.h\nindex da457f7..0669baa 100644\n--- a/lib/librte_eal/include/generic/rte_io.h\n+++ b/lib/librte_eal/include/generic/rte_io.h\n@@ -229,6 +229,40 @@ rte_write32(uint32_t value, volatile void *addr);\n static inline void\n rte_write64(uint64_t value, volatile void *addr);\n \n+/**\n+ * Write a 32-bit value to I/O device memory address addr using write\n+ * combining memory write protocol. Depending on the platform write combining\n+ * may not be available and/or may be treated as a hint and the behavior may\n+ * fallback to a regular store.\n+ *\n+ * @param value\n+ *  Value to write\n+ * @param addr\n+ *  I/O memory address to write the value to\n+ */\n+__rte_experimental\n+static inline void\n+rte_write32_wc(uint32_t value, volatile void *addr);\n+\n+/**\n+ * Write a 32-bit value to I/O device memory address addr using write\n+ * combining memory write protocol. Depending on the platform write combining\n+ * may not be available and/or may be treated as a hint and the behavior may\n+ * fallback to a regular store.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param value\n+ *  Value to write\n+ * @param addr\n+ *  I/O memory address to write the value to\n+ */\n+__rte_experimental\n+static inline void\n+rte_write32_wc_relaxed(uint32_t value, volatile void *addr);\n+\n #endif /* __DOXYGEN__ */\n \n #ifndef RTE_OVERRIDE_IO_H\n@@ -345,6 +379,20 @@ rte_write64(uint64_t value, volatile void *addr)\n \trte_write64_relaxed(value, addr);\n }\n \n+#ifndef RTE_NATIVE_WRITE32_WC\n+static __rte_always_inline void\n+rte_write32_wc(uint32_t value, volatile void *addr)\n+{\n+\trte_write32(value, addr);\n+}\n+\n+static __rte_always_inline void\n+rte_write32_wc_relaxed(uint32_t value, volatile void *addr)\n+{\n+\trte_write32_relaxed(value, addr);\n+}\n+#endif /* RTE_NATIVE_WRITE32_WC */\n+\n #endif /* RTE_OVERRIDE_IO_H */\n \n #endif /* _RTE_IO_H_ */\ndiff --git a/lib/librte_eal/x86/include/rte_io.h b/lib/librte_eal/x86/include/rte_io.h\nindex 2db71b1..4f4ff8b 100644\n--- a/lib/librte_eal/x86/include/rte_io.h\n+++ b/lib/librte_eal/x86/include/rte_io.h\n@@ -9,8 +9,50 @@\n extern \"C\" {\n #endif\n \n+#include \"rte_cpuflags.h\"\n+\n+#define RTE_NATIVE_WRITE32_WC\n #include \"generic/rte_io.h\"\n \n+/**\n+ * @internal\n+ * MOVDIRI wrapper.\n+ */\n+static __rte_always_inline void\n+_rte_x86_movdiri(uint32_t value, volatile void *addr)\n+{\n+\tasm volatile(\n+\t\t/* MOVDIRI */\n+\t\t\".byte 0x40, 0x0f, 0x38, 0xf9, 0x02\"\n+\t\t:\n+\t\t: \"a\" (value), \"d\" (addr));\n+}\n+\n+static __rte_always_inline void\n+rte_write32_wc_relaxed(uint32_t value, volatile void *addr)\n+{\n+\tstatic int _x86_movdiri_flag = -1;\n+\tif (_x86_movdiri_flag == 1) {\n+\t\t_rte_x86_movdiri(value, addr);\n+\t} else if (_x86_movdiri_flag == 0) {\n+\t\trte_write32_relaxed(value, addr);\n+\t} else {\n+\t\t_x86_movdiri_flag =\n+\t\t\t(rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIRI) > 0);\n+\t\tif (_x86_movdiri_flag == 1)\n+\t\t\t_rte_x86_movdiri(value, addr);\n+\t\telse\n+\t\t\trte_write32_relaxed(value, addr);\n+\t}\n+}\n+\n+static __rte_always_inline void\n+rte_write32_wc(uint32_t value, volatile void *addr)\n+{\n+\trte_wmb();\n+\trte_write32_wc_relaxed(value, addr);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n",
    "prefixes": [
        "v10",
        "1/4"
    ]
}