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{
    "id": 74545,
    "url": "https://patches.dpdk.org/api/patches/74545/",
    "web_url": "https://patches.dpdk.org/patch/74545/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20200721095140.719297-7-bruce.richardson@intel.com>",
    "date": "2020-07-21T09:51:26",
    "name": "[20.11,06/20] raw/ioat: make the HW register spec private",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "33f95fa08b73dc3982b21ee55f3c5741a021fac6",
    "submitter": {
        "id": 20,
        "url": "https://patches.dpdk.org/api/people/20/",
        "name": "Bruce Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/patch/74545/mbox/",
    "series": [
        {
            "id": 11200,
            "url": "https://patches.dpdk.org/api/series/11200/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11200",
            "date": "2020-07-21T09:51:20",
            "name": "raw/ioat: enhancements and new hardware support",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/11200/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/74545/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/74545/checks/",
    "tags": {},
    "headers": {
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9688\"; a=\"151440767\"",
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            "E=Sophos;i=\"5.75,378,1589266800\"; d=\"scan'208\";a=\"488023731\""
        ],
        "IronPort-SDR": [
            "\n kB2/v9jJ1lKV5irEg9i2IiBJ9+oSus7GFihXJuJTADzIkqgM6V0herGEeN+rBVAW96z4lIvCfI\n lelBnNPj9w5Q==",
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        ],
        "X-Amp-File-Uploaded": "False",
        "Precedence": "list",
        "X-Mailman-Version": "2.1.15",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "MIME-Version": "1.0",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "References": "<20200721095140.719297-1-bruce.richardson@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 20.11 06/20] raw/ioat: make the HW register spec\n\tprivate",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F7BBA0526;\n\tTue, 21 Jul 2020 11:52:57 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3BEB01C066;\n\tTue, 21 Jul 2020 11:52:25 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id D7DFC1C044\n for <dev@dpdk.org>; Tue, 21 Jul 2020 11:52:23 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 02:52:23 -0700",
            "from silpixa00399126.ir.intel.com ([10.237.222.36])\n by fmsmga005.fm.intel.com with ESMTP; 21 Jul 2020 02:52:21 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Mailer": "git-send-email 2.25.1",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-ExtLoop1": "1",
        "Date": "Tue, 21 Jul 2020 10:51:26 +0100",
        "Content-Transfer-Encoding": "8bit",
        "To": "dev@dpdk.org",
        "From": "Bruce Richardson <bruce.richardson@intel.com>",
        "In-Reply-To": "<20200721095140.719297-1-bruce.richardson@intel.com>",
        "Cc": "cheng1.jiang@intel.com, patrick.fu@intel.com, kevin.laatz@intel.com,\n Bruce Richardson <bruce.richardson@intel.com>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Message-Id": "<20200721095140.719297-7-bruce.richardson@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>"
    },
    "content": "Only a few definitions from the hardware spec are actually used in the\ndriver runtime, so we can copy over those few and make the rest of the spec\na private header in the driver.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n drivers/raw/ioat/ioat_rawdev.c                |  3 ++\n .../raw/ioat/{rte_ioat_spec.h => ioat_spec.h} | 26 -----------\n drivers/raw/ioat/meson.build                  |  3 +-\n drivers/raw/ioat/rte_ioat_rawdev_fns.h        | 44 +++++++++++++++++--\n 4 files changed, 44 insertions(+), 32 deletions(-)\n rename drivers/raw/ioat/{rte_ioat_spec.h => ioat_spec.h} (91%)",
    "diff": "diff --git a/drivers/raw/ioat/ioat_rawdev.c b/drivers/raw/ioat/ioat_rawdev.c\nindex 53b33c1a7..11c6a57e1 100644\n--- a/drivers/raw/ioat/ioat_rawdev.c\n+++ b/drivers/raw/ioat/ioat_rawdev.c\n@@ -4,10 +4,12 @@\n \n #include <rte_cycles.h>\n #include <rte_bus_pci.h>\n+#include <rte_memzone.h>\n #include <rte_string_fns.h>\n #include <rte_rawdev_pmd.h>\n \n #include \"rte_ioat_rawdev.h\"\n+#include \"ioat_spec.h\"\n \n static struct rte_pci_driver ioat_pmd_drv;\n \n@@ -260,6 +262,7 @@ ioat_rawdev_create(const char *name, struct rte_pci_device *dev)\n \tioat->rawdev = rawdev;\n \tioat->mz = mz;\n \tioat->regs = dev->mem_resource[0].addr;\n+\tioat->doorbell = &ioat->regs->dmacount;\n \tioat->ring_size = 0;\n \tioat->desc_ring = NULL;\n \tioat->status_addr = ioat->mz->iova +\ndiff --git a/drivers/raw/ioat/rte_ioat_spec.h b/drivers/raw/ioat/ioat_spec.h\nsimilarity index 91%\nrename from drivers/raw/ioat/rte_ioat_spec.h\nrename to drivers/raw/ioat/ioat_spec.h\nindex c6e7929b2..9645e16d4 100644\n--- a/drivers/raw/ioat/rte_ioat_spec.h\n+++ b/drivers/raw/ioat/ioat_spec.h\n@@ -86,32 +86,6 @@ struct rte_ioat_registers {\n \n #define RTE_IOAT_CHANCMP_ALIGN\t\t\t8\t/* CHANCMP address must be 64-bit aligned */\n \n-struct rte_ioat_generic_hw_desc {\n-\tuint32_t size;\n-\tunion {\n-\t\tuint32_t control_raw;\n-\t\tstruct {\n-\t\t\tuint32_t int_enable: 1;\n-\t\t\tuint32_t src_snoop_disable: 1;\n-\t\t\tuint32_t dest_snoop_disable: 1;\n-\t\t\tuint32_t completion_update: 1;\n-\t\t\tuint32_t fence: 1;\n-\t\t\tuint32_t reserved2: 1;\n-\t\t\tuint32_t src_page_break: 1;\n-\t\t\tuint32_t dest_page_break: 1;\n-\t\t\tuint32_t bundle: 1;\n-\t\t\tuint32_t dest_dca: 1;\n-\t\t\tuint32_t hint: 1;\n-\t\t\tuint32_t reserved: 13;\n-\t\t\tuint32_t op: 8;\n-\t\t} control;\n-\t} u;\n-\tuint64_t src_addr;\n-\tuint64_t dest_addr;\n-\tuint64_t next;\n-\tuint64_t op_specific[4];\n-};\n-\n struct rte_ioat_dma_hw_desc {\n \tuint32_t size;\n \tunion {\ndiff --git a/drivers/raw/ioat/meson.build b/drivers/raw/ioat/meson.build\nindex f66e9b605..06636f8a9 100644\n--- a/drivers/raw/ioat/meson.build\n+++ b/drivers/raw/ioat/meson.build\n@@ -8,5 +8,4 @@ sources = files('ioat_rawdev.c',\n deps += ['rawdev', 'bus_pci', 'mbuf']\n \n install_headers('rte_ioat_rawdev.h',\n-\t\t'rte_ioat_rawdev_fns.h',\n-\t\t'rte_ioat_spec.h')\n+\t\t'rte_ioat_rawdev_fns.h')\ndiff --git a/drivers/raw/ioat/rte_ioat_rawdev_fns.h b/drivers/raw/ioat/rte_ioat_rawdev_fns.h\nindex 06b4edcbb..0cee6b1b0 100644\n--- a/drivers/raw/ioat/rte_ioat_rawdev_fns.h\n+++ b/drivers/raw/ioat/rte_ioat_rawdev_fns.h\n@@ -5,9 +5,37 @@\n #define _RTE_IOAT_RAWDEV_FNS_H_\n \n #include <x86intrin.h>\n-#include <rte_memzone.h>\n #include <rte_prefetch.h>\n-#include \"rte_ioat_spec.h\"\n+\n+/**\n+ * @internal\n+ * Structure representing a device descriptor\n+ */\n+struct rte_ioat_generic_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t reserved2: 1;\n+\t\t\tuint32_t src_page_break: 1;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t op_specific[4];\n+};\n \n /**\n  * @internal\n@@ -18,7 +46,7 @@ struct rte_ioat_rawdev {\n \tconst struct rte_memzone *mz;\n \tconst struct rte_memzone *desc_mz;\n \n-\tvolatile struct rte_ioat_registers *regs;\n+\tvolatile uint16_t *doorbell;\n \tphys_addr_t status_addr;\n \tphys_addr_t ring_addr;\n \n@@ -39,8 +67,16 @@ struct rte_ioat_rawdev {\n \n \t/* to report completions, the device will write status back here */\n \tvolatile uint64_t status __rte_cache_aligned;\n+\n+\t/* pointer to the register bar */\n+\tvolatile struct rte_ioat_registers *regs;\n };\n \n+#define RTE_IOAT_CHANSTS_IDLE\t\t\t0x1\n+#define RTE_IOAT_CHANSTS_SUSPENDED\t\t0x2\n+#define RTE_IOAT_CHANSTS_HALTED\t\t0x3\n+#define RTE_IOAT_CHANSTS_ARMED\t\t\t0x4\n+\n /**\n  * Enqueue a copy operation onto the ioat device\n  */\n@@ -90,7 +126,7 @@ rte_ioat_do_copies(int dev_id)\n \tioat->desc_ring[(ioat->next_write - 1) & (ioat->ring_size - 1)].u\n \t\t\t.control.completion_update = 1;\n \trte_compiler_barrier();\n-\tioat->regs->dmacount = ioat->next_write;\n+\t*ioat->doorbell = ioat->next_write;\n \tioat->started = ioat->enqueued;\n }\n \n",
    "prefixes": [
        "20.11",
        "06/20"
    ]
}