Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/74469/?format=api
{ "id": 74469, "url": "https://patches.dpdk.org/api/patches/74469/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1595226378-81144-10-git-send-email-orika@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1595226378-81144-10-git-send-email-orika@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1595226378-81144-10-git-send-email-orika@mellanox.com", "date": "2020-07-20T06:26:13", "name": "[v6,09/13] regex/mlx5: add send queue support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bcb46a2275757e065f833adf4fabac7ead831544", "submitter": { "id": 795, "url": "https://patches.dpdk.org/api/people/795/?format=api", "name": "Ori Kam", "email": "orika@mellanox.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1595226378-81144-10-git-send-email-orika@mellanox.com/mbox/", "series": [ { "id": 11159, "url": "https://patches.dpdk.org/api/series/11159/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=11159", "date": "2020-07-20T06:26:04", "name": "add Mellanox RegEx PMD", "version": 6, "mbox": "https://patches.dpdk.org/series/11159/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/74469/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/74469/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4E4F3A0540;\n\tMon, 20 Jul 2020 08:28:16 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E366D1BF92;\n\tMon, 20 Jul 2020 08:27:07 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 5E4CF1BF92\n for <dev@dpdk.org>; Mon, 20 Jul 2020 08:26:58 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n orika@mellanox.com) with SMTP; 20 Jul 2020 09:26:53 +0300", "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n [10.210.16.126])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06K6QKul008177;\n Mon, 20 Jul 2020 09:26:53 +0300" ], "From": "Ori Kam <orika@mellanox.com>", "To": "jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com,\n viacheslavo@mellanox.com", "Cc": "guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com,\n shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com,\n alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com,\n nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com,\n harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn,\n zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com,\n wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com,\n davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com,\n oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org,\n fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net,\n orika@mellanox.com, rasland@mellanox.com", "Date": "Mon, 20 Jul 2020 06:26:13 +0000", "Message-Id": "<1595226378-81144-10-git-send-email-orika@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1595226378-81144-1-git-send-email-orika@mellanox.com>", "References": "<1593941027-86651-1-git-send-email-orika@mellanox.com>\n <1595226378-81144-1-git-send-email-orika@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v6 09/13] regex/mlx5: add send queue support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit introduce the SQ creation.\nThe SQ is used for enqueuing a job.\n\nIn order to support out of order matches, we create number\nos SQ per one application QP.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/regex/mlx5/mlx5_regex.h | 2 +\n drivers/regex/mlx5/mlx5_regex_control.c | 179 ++++++++++++++++++++++++++++++++\n 2 files changed, 181 insertions(+)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 21770ca..bf285a1 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -21,6 +21,7 @@ struct mlx5_regex_sq {\n \tuint32_t dbr_umem; /* Door bell record umem id. */\n \tuint8_t *wqe; /* The SQ ring buffer. */\n \tstruct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */\n+\tuint32_t *dbr;\n };\n \n struct mlx5_regex_cq {\n@@ -30,6 +31,7 @@ struct mlx5_regex_cq {\n \tuint32_t dbr_umem; /* Door bell record umem id. */\n \tvolatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */\n \tstruct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */\n+\tuint32_t *dbr;\n };\n \n struct mlx5_regex_qp {\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex 577965f..83d390a 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -105,6 +105,9 @@\n \t\tgoto error;\n \t}\n \tcq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);\n+\tcq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t (uintptr_t)cq->dbr_offset);\n+\n \tbuf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096);\n \tif (!buf) {\n \t\tDRV_LOG(ERR, \"Can't allocate cqe buffer.\");\n@@ -145,6 +148,170 @@\n \treturn -rte_errno;\n }\n \n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+static int\n+regex_get_pdn(void *pd, uint32_t *pdn)\n+{\n+\tstruct mlx5dv_obj obj;\n+\tstruct mlx5dv_pd pd_info;\n+\tint ret = 0;\n+\n+\tobj.pd.in = pd;\n+\tobj.pd.out = &pd_info;\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n+\tif (ret) {\n+\t\tDRV_LOG(DEBUG, \"Fail to get PD object info\");\n+\t\treturn ret;\n+\t}\n+\t*pdn = pd_info.pdn;\n+\treturn 0;\n+}\n+#endif\n+\n+/**\n+ * create the SQ object.\n+ *\n+ * @param priv\n+ * Pointer to the priv object.\n+ * @param qp\n+ * Pointer to the QP element\n+ * @param q_ind\n+ * The index of the queue.\n+ * @param log_nb_desc\n+ * Log 2 of the number of descriptors to be used.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n+\t\t uint16_t q_ind, uint16_t log_nb_desc)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tstruct mlx5_devx_create_sq_attr attr = { 0 };\n+\tstruct mlx5_devx_modify_sq_attr modify_attr = { 0 };\n+\tstruct mlx5_devx_wq_attr *wq_attr = &attr.wq_attr;\n+\tstruct mlx5_devx_dbr_page *dbr_page = NULL;\n+\tstruct mlx5_regex_sq *sq = &qp->sqs[q_ind];\n+\tvoid *buf = NULL;\n+\tuint32_t sq_size;\n+\tuint32_t pd_num = 0;\n+\tint ret;\n+\n+\tsq->log_nb_desc = log_nb_desc;\n+\tsq_size = 1 << sq->log_nb_desc;\n+\tsq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page);\n+\tif (sq->dbr_offset < 0) {\n+\t\tDRV_LOG(ERR, \"Can't allocate sq door bell record.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tsq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);\n+\tsq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +\n+\t\t\t (uintptr_t)sq->dbr_offset);\n+\n+\tbuf = rte_calloc(NULL, 1, 64 * sq_size, 4096);\n+\tif (!buf) {\n+\t\tDRV_LOG(ERR, \"Can't allocate wqe buffer.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tsq->wqe = buf;\n+\tsq->wqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf, 64 * sq_size,\n+\t\t\t\t\t\t7);\n+\tif (!sq->wqe_umem) {\n+\t\tDRV_LOG(ERR, \"Can't register wqe mem.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tattr.state = MLX5_SQC_STATE_RST;\n+\tattr.tis_lst_sz = 0;\n+\tattr.tis_num = 0;\n+\tattr.user_index = q_ind;\n+\tattr.cqn = qp->cq.obj->id;\n+\twq_attr->uar_page = priv->uar->page_id;\n+\tregex_get_pdn(priv->pd, &pd_num);\n+\twq_attr->pd = pd_num;\n+\twq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC;\n+\twq_attr->dbr_umem_id = sq->dbr_umem;\n+\twq_attr->dbr_addr = sq->dbr_offset;\n+\twq_attr->dbr_umem_valid = 1;\n+\twq_attr->wq_umem_id = mlx5_os_get_umem_id(sq->wqe_umem);\n+\twq_attr->wq_umem_offset = 0;\n+\twq_attr->wq_umem_valid = 1;\n+\twq_attr->log_wq_stride = 6;\n+\twq_attr->log_wq_sz = sq->log_nb_desc;\n+\tsq->obj = mlx5_devx_cmd_create_sq(priv->ctx, &attr);\n+\tif (!sq->obj) {\n+\t\tDRV_LOG(ERR, \"Can't create sq object.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tmodify_attr.state = MLX5_SQC_STATE_RDY;\n+\tret = mlx5_devx_cmd_modify_sq(sq->obj, &modify_attr);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Can't change sq state to ready.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\treturn 0;\n+error:\n+\tif (sq->wqe_umem)\n+\t\tmlx5_glue->devx_umem_dereg(sq->wqe_umem);\n+\tif (buf)\n+\t\trte_free(buf);\n+\tif (sq->dbr_offset)\n+\t\tmlx5_release_dbr(&priv->dbrpgs, sq->dbr_umem, sq->dbr_offset);\n+\treturn -rte_errno;\n+#else\n+\t(void)priv;\n+\t(void)qp;\n+\t(void)q_ind;\n+\t(void)log_nb_desc;\n+\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n+\treturn -ENOTSUP;\n+#endif\n+}\n+\n+/**\n+ * Destroy the SQ object.\n+ *\n+ * @param priv\n+ * Pointer to the priv object.\n+ * @param qp\n+ * Pointer to the QP element\n+ * @param q_ind\n+ * The index of the queue.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+regex_ctrl_destroy_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n+\t\t uint16_t q_ind)\n+{\n+\tstruct mlx5_regex_sq *sq = &qp->sqs[q_ind];\n+\n+\tif (sq->wqe_umem) {\n+\t\tmlx5_glue->devx_umem_dereg(sq->wqe_umem);\n+\t\tsq->wqe_umem = NULL;\n+\t}\n+\tif (sq->wqe) {\n+\t\trte_free((void *)(uintptr_t)sq->wqe);\n+\t\tsq->wqe = NULL;\n+\t}\n+\tif (sq->dbr_offset) {\n+\t\tmlx5_release_dbr(&priv->dbrpgs, sq->dbr_umem, sq->dbr_offset);\n+\t\tsq->dbr_offset = -1;\n+\t}\n+\tif (sq->obj) {\n+\t\tmlx5_devx_cmd_destroy(sq->obj);\n+\t\tsq->obj = NULL;\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Setup the qp.\n *\n@@ -164,7 +331,9 @@\n {\n \tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n \tstruct mlx5_regex_qp *qp;\n+\tint i;\n \tint ret;\n+\tuint16_t log_desc;\n \n \tqp = &priv->qps[qp_ind];\n \tqp->flags = cfg->qp_conf_flags;\n@@ -181,15 +350,25 @@\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n+\tlog_desc = rte_log2_u32(qp->nb_desc / qp->nb_obj);\n \tret = regex_ctrl_create_cq(priv, &qp->cq);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Can't create cq.\");\n \t\tgoto error;\n \t}\n+\tfor (i = 0; i < qp->nb_obj; i++) {\n+\t\tret = regex_ctrl_create_sq(priv, qp, i, log_desc);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Can't create sq.\");\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n \treturn 0;\n \n error:\n \tregex_ctrl_destroy_cq(priv, &qp->cq);\n+\tfor (i = 0; i < qp->nb_obj; i++)\n+\t\tret = regex_ctrl_destroy_sq(priv, qp, i);\n \treturn -rte_errno;\n \n }\n", "prefixes": [ "v6", "09/13" ] }