Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 7446,
    "url": "https://patches.dpdk.org/api/patches/7446/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1444067692-29645-7-git-send-email-adrien.mazarguil@6wind.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1444067692-29645-7-git-send-email-adrien.mazarguil@6wind.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1444067692-29645-7-git-send-email-adrien.mazarguil@6wind.com",
    "date": "2015-10-05T17:54:41",
    "name": "[dpdk-dev,06/17] mlx5: adapt indirection table size depending on RX queues number",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c3f2f50a46891355432ffbc6f725214669b3a3a6",
    "submitter": {
        "id": 165,
        "url": "https://patches.dpdk.org/api/people/165/?format=api",
        "name": "Adrien Mazarguil",
        "email": "adrien.mazarguil@6wind.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1444067692-29645-7-git-send-email-adrien.mazarguil@6wind.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/7446/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/7446/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1CB2393BC;\n\tMon,  5 Oct 2015 19:55:27 +0200 (CEST)",
            "from mail-wi0-f170.google.com (mail-wi0-f170.google.com\n\t[209.85.212.170]) by dpdk.org (Postfix) with ESMTP id 8E8D293BA\n\tfor <dev@dpdk.org>; Mon,  5 Oct 2015 19:55:26 +0200 (CEST)",
            "by wicfx3 with SMTP id fx3so131837544wic.1\n\tfor <dev@dpdk.org>; Mon, 05 Oct 2015 10:55:26 -0700 (PDT)",
            "from 6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tpk7sm28129867wjb.2.2015.10.05.10.55.25\n\t(version=TLSv1.2 cipher=RC4-SHA bits=128/128);\n\tMon, 05 Oct 2015 10:55:26 -0700 (PDT)"
        ],
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=WD8Qos+YtuevYZvyVxTE3792NDgE1GVc63O0ipibivk=;\n\tb=DoWqIr9fvzN9wg2OU02wEgrlHLKjDrFXOMCLZx4f83bTKn+lH+rG0Ri0HKkF5ycUl+\n\tLWepSAGZpaCPgJ6rm30zRsEUt7T8w2GWdxXeIr2ZJ1oEPGO10CBTqOSVzg/XPnsMSVB8\n\tFbbzq7BhfWLdBtqpW7ML2sWyc8uas7LGziXYYYe0CMB2utPfaScMTDDKvfs12MrKp1AG\n\tICdjFlmNseX9LadTWzFZhoslepwNtmSZofF6EgWOJT5dd7kppSiHbsDdfYx/uCF6oxCC\n\t37ykKLrThWUVY21cPPC4o6onUqyC1UboaL/dTQVn/H3M7PBvGLDoYueR7VFVEUg9C5zH\n\ttJBQ==",
        "X-Gm-Message-State": "ALoCoQm6coi37121lunc7skOmVDeyDXBQO8wpyR8OVz7pPaad0qdfAWhs3Lw+MAXyD2hjAqnKuVD",
        "X-Received": "by 10.180.39.193 with SMTP id r1mr12191549wik.57.1444067726471; \n\tMon, 05 Oct 2015 10:55:26 -0700 (PDT)",
        "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>",
        "To": "dev@dpdk.org",
        "Date": "Mon,  5 Oct 2015 19:54:41 +0200",
        "Message-Id": "<1444067692-29645-7-git-send-email-adrien.mazarguil@6wind.com>",
        "X-Mailer": "git-send-email 2.1.0",
        "In-Reply-To": "<1444067692-29645-1-git-send-email-adrien.mazarguil@6wind.com>",
        "References": "<1444067692-29645-1-git-send-email-adrien.mazarguil@6wind.com>",
        "Subject": "[dpdk-dev] [PATCH 06/17] mlx5: adapt indirection table size\n\tdepending on RX queues number",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\n\nUse the maximum size of the indirection table when the number of requested\nRX queues is not a power of two, this help to improve RSS balancing.\n\nA message informs users that balancing is not optimal in such cases.\n\nSigned-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n drivers/net/mlx5/mlx5.c      | 10 +++++++++-\n drivers/net/mlx5/mlx5.h      |  1 +\n drivers/net/mlx5/mlx5_defs.h |  3 +++\n drivers/net/mlx5/mlx5_rxq.c  | 21 ++++++++++++++-------\n 4 files changed, 27 insertions(+), 8 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex a316989..167e14b 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -301,7 +301,9 @@ mlx5_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tstruct ether_addr mac;\n \n #ifdef HAVE_EXP_QUERY_DEVICE\n-\t\texp_device_attr.comp_mask = IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS;\n+\t\texp_device_attr.comp_mask =\n+\t\t\tIBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |\n+\t\t\tIBV_EXP_DEVICE_ATTR_RX_HASH;\n #endif /* HAVE_EXP_QUERY_DEVICE */\n \n \t\tDEBUG(\"using port %u (%08\" PRIx32 \")\", port, test);\n@@ -365,6 +367,12 @@ mlx5_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tDEBUG(\"L2 tunnel checksum offloads are %ssupported\",\n \t\t      (priv->hw_csum_l2tun ? \"\" : \"not \"));\n \n+\t\tpriv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;\n+\t\tDEBUG(\"maximum RX indirection table size is %u\",\n+\t\t      priv->ind_table_max_size);\n+\n+#else /* HAVE_EXP_QUERY_DEVICE */\n+\t\tpriv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE;\n #endif /* HAVE_EXP_QUERY_DEVICE */\n \n \t\tpriv->vf = vf;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 08900f5..b099dac 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -114,6 +114,7 @@ struct priv {\n \t/* Indirection tables referencing all RX WQs. */\n \tstruct ibv_exp_rwq_ind_table *(*ind_tables)[];\n \tunsigned int ind_tables_n; /* Number of indirection tables. */\n+\tunsigned int ind_table_max_size; /* Maximum indirection table size. */\n \t/* Hash RX QPs feeding the indirection table. */\n \tstruct hash_rxq (*hash_rxqs)[];\n \tunsigned int hash_rxqs_n; /* Hash RX QPs array size. */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 79de609..e697764 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -53,6 +53,9 @@\n /* Request send completion once in every 64 sends, might be less. */\n #define MLX5_PMD_TX_PER_COMP_REQ 64\n \n+/* RSS Indirection table size. */\n+#define RSS_INDIRECTION_TABLE_SIZE 128\n+\n /* Maximum number of Scatter/Gather Elements per Work Request. */\n #ifndef MLX5_PMD_SGE_WR_N\n #define MLX5_PMD_SGE_WR_N 4\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b5084f8..606367c 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -224,7 +224,13 @@ priv_make_ind_table_init(struct priv *priv,\n int\n priv_create_hash_rxqs(struct priv *priv)\n {\n-\tunsigned int wqs_n = (1 << log2above(priv->rxqs_n));\n+\t/* If the requested number of WQs is not a power of two, use the\n+\t * maximum indirection table size for better balancing.\n+\t * The result is always rounded to the next power of two. */\n+\tunsigned int wqs_n =\n+\t\t(1 << log2above((priv->rxqs_n & (priv->rxqs_n - 1)) ?\n+\t\t\t\tpriv->ind_table_max_size :\n+\t\t\t\tpriv->rxqs_n));\n \tstruct ibv_exp_wq *wqs[wqs_n];\n \tstruct ind_table_init ind_table_init[IND_TABLE_INIT_N];\n \tunsigned int ind_tables_n =\n@@ -251,16 +257,17 @@ priv_create_hash_rxqs(struct priv *priv)\n \t\t      \" indirection table cannot be created\");\n \t\treturn EINVAL;\n \t}\n-\tif (wqs_n < priv->rxqs_n) {\n+\tif ((wqs_n < priv->rxqs_n) || (wqs_n > priv->ind_table_max_size)) {\n \t\tERROR(\"cannot handle this many RX queues (%u)\", priv->rxqs_n);\n \t\terr = ERANGE;\n \t\tgoto error;\n \t}\n-\tif (wqs_n != priv->rxqs_n)\n-\t\tWARN(\"%u RX queues are configured, consider rounding this\"\n-\t\t     \" number to the next power of two (%u) for optimal\"\n-\t\t     \" performance\",\n-\t\t     priv->rxqs_n, wqs_n);\n+\tif (wqs_n != priv->rxqs_n) {\n+\t\tINFO(\"%u RX queues are configured, consider rounding this\"\n+\t\t     \" number to the next power of two for better balancing\",\n+\t\t     priv->rxqs_n);\n+\t\tDEBUG(\"indirection table extended to assume %u WQs\", wqs_n);\n+\t}\n \t/* When the number of RX queues is not a power of two, the remaining\n \t * table entries are padded with reused WQs and hashes are not spread\n \t * uniformly. */\n",
    "prefixes": [
        "dpdk-dev",
        "06/17"
    ]
}